1*2d172691SDavid Lechner // SPDX-License-Identifier: GPL-2.0
2*2d172691SDavid Lechner /*
3*2d172691SDavid Lechner  * PLL clock driver for TI Davinci SoCs
4*2d172691SDavid Lechner  *
5*2d172691SDavid Lechner  * Copyright (C) 2018 David Lechner <david@lechnology.com>
6*2d172691SDavid Lechner  */
7*2d172691SDavid Lechner 
8*2d172691SDavid Lechner #ifndef __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__
9*2d172691SDavid Lechner #define __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__
10*2d172691SDavid Lechner 
11*2d172691SDavid Lechner #include <linux/regmap.h>
12*2d172691SDavid Lechner 
13*2d172691SDavid Lechner /**
14*2d172691SDavid Lechner  * davinci_pll_platform_data
15*2d172691SDavid Lechner  * @cfgchip: CFGCHIP syscon regmap
16*2d172691SDavid Lechner  */
17*2d172691SDavid Lechner struct davinci_pll_platform_data {
18*2d172691SDavid Lechner 	struct regmap *cfgchip;
19*2d172691SDavid Lechner };
20*2d172691SDavid Lechner 
21*2d172691SDavid Lechner #endif /* __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ */
22