1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 27ec94453SAneesh V /* 37ec94453SAneesh V * Definitions for TI EMIF device platform data 47ec94453SAneesh V * 57ec94453SAneesh V * Copyright (C) 2012 Texas Instruments, Inc. 67ec94453SAneesh V * 77ec94453SAneesh V * Aneesh V <aneesh@ti.com> 87ec94453SAneesh V */ 97ec94453SAneesh V #ifndef __EMIF_PLAT_H 107ec94453SAneesh V #define __EMIF_PLAT_H 117ec94453SAneesh V 127ec94453SAneesh V /* Low power modes - EMIF_PWR_MGMT_CTRL */ 137ec94453SAneesh V #define EMIF_LP_MODE_DISABLE 0 147ec94453SAneesh V #define EMIF_LP_MODE_CLOCK_STOP 1 157ec94453SAneesh V #define EMIF_LP_MODE_SELF_REFRESH 2 167ec94453SAneesh V #define EMIF_LP_MODE_PWR_DN 4 177ec94453SAneesh V 187ec94453SAneesh V /* Hardware capabilities */ 197ec94453SAneesh V #define EMIF_HW_CAPS_LL_INTERFACE 0x00000001 207ec94453SAneesh V 217ec94453SAneesh V /* 227ec94453SAneesh V * EMIF IP Revisions 237ec94453SAneesh V * EMIF4D - Used in OMAP4 247ec94453SAneesh V * EMIF4D5 - Used in OMAP5 257ec94453SAneesh V */ 267ec94453SAneesh V #define EMIF_4D 1 277ec94453SAneesh V #define EMIF_4D5 2 287ec94453SAneesh V 297ec94453SAneesh V /* 307ec94453SAneesh V * PHY types 317ec94453SAneesh V * ATTILAPHY - Used in OMAP4 327ec94453SAneesh V * INTELLIPHY - Used in OMAP5 337ec94453SAneesh V */ 347ec94453SAneesh V #define EMIF_PHY_TYPE_ATTILAPHY 1 357ec94453SAneesh V #define EMIF_PHY_TYPE_INTELLIPHY 2 367ec94453SAneesh V 377ec94453SAneesh V /* Custom config requests */ 387ec94453SAneesh V #define EMIF_CUSTOM_CONFIG_LPMODE 0x00000001 397ec94453SAneesh V #define EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL 0x00000002 40f91a595dSNishanth Menon #define EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART 0x00000004 417ec94453SAneesh V 427ec94453SAneesh V #ifndef __ASSEMBLY__ 437ec94453SAneesh V /** 447ec94453SAneesh V * struct ddr_device_info - All information about the DDR device except AC 457ec94453SAneesh V * timing parameters 467ec94453SAneesh V * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc) 477ec94453SAneesh V * @density: Device density 487ec94453SAneesh V * @io_width: Bus width 497ec94453SAneesh V * @cs1_used: Whether there is a DDR device attached to the second 507ec94453SAneesh V * chip-select(CS1) of this EMIF instance 517ec94453SAneesh V * @cal_resistors_per_cs: Whether there is one calibration resistor per 527ec94453SAneesh V * chip-select or whether it's a single one for both 537ec94453SAneesh V * @manufacturer: Manufacturer name string 547ec94453SAneesh V */ 557ec94453SAneesh V struct ddr_device_info { 567ec94453SAneesh V u32 type; 577ec94453SAneesh V u32 density; 587ec94453SAneesh V u32 io_width; 597ec94453SAneesh V u32 cs1_used; 607ec94453SAneesh V u32 cal_resistors_per_cs; 617ec94453SAneesh V char manufacturer[10]; 627ec94453SAneesh V }; 637ec94453SAneesh V 647ec94453SAneesh V /** 657ec94453SAneesh V * struct emif_custom_configs - Custom configuration parameters/policies 667ec94453SAneesh V * passed from the platform layer 677ec94453SAneesh V * @mask: Mask to indicate which configs are requested 687ec94453SAneesh V * @lpmode: LPMODE to be used in PWR_MGMT_CTRL register 697ec94453SAneesh V * @lpmode_timeout_performance: Timeout before LPMODE entry when higher 707ec94453SAneesh V * performance is desired at the cost of power (typically 717ec94453SAneesh V * at higher OPPs) 727ec94453SAneesh V * @lpmode_timeout_power: Timeout before LPMODE entry when better power 737ec94453SAneesh V * savings is desired and performance is not important 747ec94453SAneesh V * (typically at lower loads indicated by lower OPPs) 757ec94453SAneesh V * @lpmode_freq_threshold: The DDR frequency threshold to identify between 767ec94453SAneesh V * the above two cases: 777ec94453SAneesh V * timeout = (freq >= lpmode_freq_threshold) ? 787ec94453SAneesh V * lpmode_timeout_performance : 797ec94453SAneesh V * lpmode_timeout_power; 807ec94453SAneesh V * @temp_alert_poll_interval_ms: LPDDR2 MR4 polling interval at nominal 817ec94453SAneesh V * temperature(in milliseconds). When temperature is high 827ec94453SAneesh V * polling is done 4 times as frequently. 837ec94453SAneesh V */ 847ec94453SAneesh V struct emif_custom_configs { 857ec94453SAneesh V u32 mask; 867ec94453SAneesh V u32 lpmode; 877ec94453SAneesh V u32 lpmode_timeout_performance; 887ec94453SAneesh V u32 lpmode_timeout_power; 897ec94453SAneesh V u32 lpmode_freq_threshold; 907ec94453SAneesh V u32 temp_alert_poll_interval_ms; 917ec94453SAneesh V }; 927ec94453SAneesh V 937ec94453SAneesh V /** 947ec94453SAneesh V * struct emif_platform_data - Platform data passed on EMIF platform 957ec94453SAneesh V * device creation. Used by the driver. 967ec94453SAneesh V * @hw_caps: Hw capabilities of the EMIF IP in the respective SoC 977ec94453SAneesh V * @device_info: Device info structure containing information such 987ec94453SAneesh V * as type, bus width, density etc 997ec94453SAneesh V * @timings: Timings information from device datasheet passed 1007ec94453SAneesh V * as an array of 'struct lpddr2_timings'. Can be NULL 1017ec94453SAneesh V * if if default timings are ok 1027ec94453SAneesh V * @timings_arr_size: Size of the timings array. Depends on the number 1037ec94453SAneesh V * of different frequencies for which timings data 1047ec94453SAneesh V * is provided 1057ec94453SAneesh V * @min_tck: Minimum value of some timing parameters in terms 1067ec94453SAneesh V * of number of cycles. Can be NULL if default values 1077ec94453SAneesh V * are ok 1087ec94453SAneesh V * @custom_configs: Custom configurations requested by SoC or board 1097ec94453SAneesh V * code and the data for them. Can be NULL if default 1107ec94453SAneesh V * configurations done by the driver are ok. See 1117ec94453SAneesh V * documentation for 'struct emif_custom_configs' for 1127ec94453SAneesh V * more details 1137ec94453SAneesh V */ 1147ec94453SAneesh V struct emif_platform_data { 1157ec94453SAneesh V u32 hw_caps; 1167ec94453SAneesh V struct ddr_device_info *device_info; 1177ec94453SAneesh V const struct lpddr2_timings *timings; 1187ec94453SAneesh V u32 timings_arr_size; 1197ec94453SAneesh V const struct lpddr2_min_tck *min_tck; 1207ec94453SAneesh V struct emif_custom_configs *custom_configs; 1217ec94453SAneesh V u32 ip_rev; 1227ec94453SAneesh V u32 phy_type; 1237ec94453SAneesh V }; 1247ec94453SAneesh V #endif /* __ASSEMBLY__ */ 1257ec94453SAneesh V 1267ec94453SAneesh V #endif /* __LINUX_EMIF_H */ 127