1 #include "chip_offset_byte.h" 2 3 #define ACP3x_PHY_BASE_ADDRESS 0x1240000 4 #define ACP3x_I2S_MODE 0 5 #define ACP3x_REG_START 0x1240000 6 #define ACP3x_REG_END 0x1250200 7 #define I2S_MODE 0x04 8 #define BT_TX_THRESHOLD 26 9 #define BT_RX_THRESHOLD 25 10 #define ACP3x_POWER_ON 0x00 11 #define ACP3x_POWER_ON_IN_PROGRESS 0x01 12 #define ACP3x_POWER_OFF 0x02 13 #define ACP3x_POWER_OFF_IN_PROGRESS 0x03 14 #define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001 15 16 #define ACP_SRAM_PTE_OFFSET 0x02050000 17 #define PAGE_SIZE_4K_ENABLE 0x2 18 #define MEM_WINDOW_START 0x4000000 19 #define PLAYBACK_FIFO_ADDR_OFFSET 0x400 20 #define CAPTURE_FIFO_ADDR_OFFSET 0x500 21 22 #define PLAYBACK_MIN_NUM_PERIODS 2 23 #define PLAYBACK_MAX_NUM_PERIODS 8 24 #define PLAYBACK_MAX_PERIOD_SIZE 16384 25 #define PLAYBACK_MIN_PERIOD_SIZE 4096 26 #define CAPTURE_MIN_NUM_PERIODS 2 27 #define CAPTURE_MAX_NUM_PERIODS 8 28 #define CAPTURE_MAX_PERIOD_SIZE 16384 29 #define CAPTURE_MIN_PERIOD_SIZE 4096 30 31 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 32 #define MIN_BUFFER MAX_BUFFER 33 #define FIFO_SIZE 0x100 34 #define DMA_SIZE 0x40 35 36 static inline u32 rv_readl(void __iomem *base_addr) 37 { 38 return readl(base_addr - ACP3x_PHY_BASE_ADDRESS); 39 } 40 41 static inline void rv_writel(u32 val, void __iomem *base_addr) 42 { 43 writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS); 44 } 45