1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale DMA ALSA SoC PCM driver
4 //
5 // Author: Timur Tabi <timur@freescale.com>
6 //
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
8 //
9 // This driver implements ASoC support for the Elo DMA controller, which is
10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
11 // the PCM driver is what handles the DMA buffer.
12
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/delay.h>
19 #include <linux/gfp.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/list.h>
24 #include <linux/slab.h>
25
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30
31 #include <asm/io.h>
32
33 #include "fsl_dma.h"
34 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
35
36 #define DRV_NAME "fsl_dma"
37
38 /*
39 * The formats that the DMA controller supports, which is anything
40 * that is 8, 16, or 32 bits.
41 */
42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
43 SNDRV_PCM_FMTBIT_U8 | \
44 SNDRV_PCM_FMTBIT_S16_LE | \
45 SNDRV_PCM_FMTBIT_S16_BE | \
46 SNDRV_PCM_FMTBIT_U16_LE | \
47 SNDRV_PCM_FMTBIT_U16_BE | \
48 SNDRV_PCM_FMTBIT_S24_LE | \
49 SNDRV_PCM_FMTBIT_S24_BE | \
50 SNDRV_PCM_FMTBIT_U24_LE | \
51 SNDRV_PCM_FMTBIT_U24_BE | \
52 SNDRV_PCM_FMTBIT_S32_LE | \
53 SNDRV_PCM_FMTBIT_S32_BE | \
54 SNDRV_PCM_FMTBIT_U32_LE | \
55 SNDRV_PCM_FMTBIT_U32_BE)
56 struct dma_object {
57 struct snd_soc_component_driver dai;
58 dma_addr_t ssi_stx_phys;
59 dma_addr_t ssi_srx_phys;
60 unsigned int ssi_fifo_depth;
61 struct ccsr_dma_channel __iomem *channel;
62 unsigned int irq;
63 bool assigned;
64 };
65
66 /*
67 * The number of DMA links to use. Two is the bare minimum, but if you
68 * have really small links you might need more.
69 */
70 #define NUM_DMA_LINKS 2
71
72 /** fsl_dma_private: p-substream DMA data
73 *
74 * Each substream has a 1-to-1 association with a DMA channel.
75 *
76 * The link[] array is first because it needs to be aligned on a 32-byte
77 * boundary, so putting it first will ensure alignment without padding the
78 * structure.
79 *
80 * @link[]: array of link descriptors
81 * @dma_channel: pointer to the DMA channel's registers
82 * @irq: IRQ for this DMA channel
83 * @substream: pointer to the substream object, needed by the ISR
84 * @ssi_sxx_phys: bus address of the STX or SRX register to use
85 * @ld_buf_phys: physical address of the LD buffer
86 * @current_link: index into link[] of the link currently being processed
87 * @dma_buf_phys: physical address of the DMA buffer
88 * @dma_buf_next: physical address of the next period to process
89 * @dma_buf_end: physical address of the byte after the end of the DMA
90 * @buffer period_size: the size of a single period
91 * @num_periods: the number of periods in the DMA buffer
92 */
93 struct fsl_dma_private {
94 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
95 struct ccsr_dma_channel __iomem *dma_channel;
96 unsigned int irq;
97 struct snd_pcm_substream *substream;
98 dma_addr_t ssi_sxx_phys;
99 unsigned int ssi_fifo_depth;
100 dma_addr_t ld_buf_phys;
101 unsigned int current_link;
102 dma_addr_t dma_buf_phys;
103 dma_addr_t dma_buf_next;
104 dma_addr_t dma_buf_end;
105 size_t period_size;
106 unsigned int num_periods;
107 };
108
109 /**
110 * fsl_dma_hardare: define characteristics of the PCM hardware.
111 *
112 * The PCM hardware is the Freescale DMA controller. This structure defines
113 * the capabilities of that hardware.
114 *
115 * Since the sampling rate and data format are not controlled by the DMA
116 * controller, we specify no limits for those values. The only exception is
117 * period_bytes_min, which is set to a reasonably low value to prevent the
118 * DMA controller from generating too many interrupts per second.
119 *
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
122 * number of periods.
123 *
124 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
125 * limitation in the SSI driver requires the sample rates for playback and
126 * capture to be the same.
127 */
128 static const struct snd_pcm_hardware fsl_dma_hardware = {
129
130 .info = SNDRV_PCM_INFO_INTERLEAVED |
131 SNDRV_PCM_INFO_MMAP |
132 SNDRV_PCM_INFO_MMAP_VALID |
133 SNDRV_PCM_INFO_JOINT_DUPLEX |
134 SNDRV_PCM_INFO_PAUSE,
135 .formats = FSLDMA_PCM_FORMATS,
136 .period_bytes_min = 512, /* A reasonable limit */
137 .period_bytes_max = (u32) -1,
138 .periods_min = NUM_DMA_LINKS,
139 .periods_max = (unsigned int) -1,
140 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
141 };
142
143 /**
144 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
145 *
146 * This function should be called by the ISR whenever the DMA controller
147 * halts data transfer.
148 */
fsl_dma_abort_stream(struct snd_pcm_substream * substream)149 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
150 {
151 snd_pcm_stop_xrun(substream);
152 }
153
154 /**
155 * fsl_dma_update_pointers - update LD pointers to point to the next period
156 *
157 * As each period is completed, this function changes the link
158 * descriptor pointers for that period to point to the next period.
159 */
fsl_dma_update_pointers(struct fsl_dma_private * dma_private)160 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
161 {
162 struct fsl_dma_link_descriptor *link =
163 &dma_private->link[dma_private->current_link];
164
165 /* Update our link descriptors to point to the next period. On a 36-bit
166 * system, we also need to update the ESAD bits. We also set (keep) the
167 * snoop bits. See the comments in fsl_dma_hw_params() about snooping.
168 */
169 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
170 link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
171 #ifdef CONFIG_PHYS_64BIT
172 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
173 upper_32_bits(dma_private->dma_buf_next));
174 #endif
175 } else {
176 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
177 #ifdef CONFIG_PHYS_64BIT
178 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
179 upper_32_bits(dma_private->dma_buf_next));
180 #endif
181 }
182
183 /* Update our variables for next time */
184 dma_private->dma_buf_next += dma_private->period_size;
185
186 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
187 dma_private->dma_buf_next = dma_private->dma_buf_phys;
188
189 if (++dma_private->current_link >= NUM_DMA_LINKS)
190 dma_private->current_link = 0;
191 }
192
193 /**
194 * fsl_dma_isr: interrupt handler for the DMA controller
195 *
196 * @irq: IRQ of the DMA channel
197 * @dev_id: pointer to the dma_private structure for this DMA channel
198 */
fsl_dma_isr(int irq,void * dev_id)199 static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
200 {
201 struct fsl_dma_private *dma_private = dev_id;
202 struct snd_pcm_substream *substream = dma_private->substream;
203 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
204 struct device *dev = rtd->dev;
205 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
206 irqreturn_t ret = IRQ_NONE;
207 u32 sr, sr2 = 0;
208
209 /* We got an interrupt, so read the status register to see what we
210 were interrupted for.
211 */
212 sr = in_be32(&dma_channel->sr);
213
214 if (sr & CCSR_DMA_SR_TE) {
215 dev_err(dev, "dma transmit error\n");
216 fsl_dma_abort_stream(substream);
217 sr2 |= CCSR_DMA_SR_TE;
218 ret = IRQ_HANDLED;
219 }
220
221 if (sr & CCSR_DMA_SR_CH)
222 ret = IRQ_HANDLED;
223
224 if (sr & CCSR_DMA_SR_PE) {
225 dev_err(dev, "dma programming error\n");
226 fsl_dma_abort_stream(substream);
227 sr2 |= CCSR_DMA_SR_PE;
228 ret = IRQ_HANDLED;
229 }
230
231 if (sr & CCSR_DMA_SR_EOLNI) {
232 sr2 |= CCSR_DMA_SR_EOLNI;
233 ret = IRQ_HANDLED;
234 }
235
236 if (sr & CCSR_DMA_SR_CB)
237 ret = IRQ_HANDLED;
238
239 if (sr & CCSR_DMA_SR_EOSI) {
240 /* Tell ALSA we completed a period. */
241 snd_pcm_period_elapsed(substream);
242
243 /*
244 * Update our link descriptors to point to the next period. We
245 * only need to do this if the number of periods is not equal to
246 * the number of links.
247 */
248 if (dma_private->num_periods != NUM_DMA_LINKS)
249 fsl_dma_update_pointers(dma_private);
250
251 sr2 |= CCSR_DMA_SR_EOSI;
252 ret = IRQ_HANDLED;
253 }
254
255 if (sr & CCSR_DMA_SR_EOLSI) {
256 sr2 |= CCSR_DMA_SR_EOLSI;
257 ret = IRQ_HANDLED;
258 }
259
260 /* Clear the bits that we set */
261 if (sr2)
262 out_be32(&dma_channel->sr, sr2);
263
264 return ret;
265 }
266
267 /**
268 * fsl_dma_new: initialize this PCM driver.
269 *
270 * This function is called when the codec driver calls snd_soc_new_pcms(),
271 * once for each .dai_link in the machine driver's snd_soc_card
272 * structure.
273 *
274 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
275 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
276 * is specified. Therefore, any DMA buffers we allocate will always be in low
277 * memory, but we support for 36-bit physical addresses anyway.
278 *
279 * Regardless of where the memory is actually allocated, since the device can
280 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
281 */
fsl_dma_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)282 static int fsl_dma_new(struct snd_soc_component *component,
283 struct snd_soc_pcm_runtime *rtd)
284 {
285 struct snd_card *card = rtd->card->snd_card;
286 struct snd_pcm *pcm = rtd->pcm;
287 int ret;
288
289 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36));
290 if (ret)
291 return ret;
292
293 return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
294 card->dev,
295 fsl_dma_hardware.buffer_bytes_max);
296 }
297
298 /**
299 * fsl_dma_open: open a new substream.
300 *
301 * Each substream has its own DMA buffer.
302 *
303 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
304 * descriptors that ping-pong from one period to the next. For example, if
305 * there are six periods and two link descriptors, this is how they look
306 * before playback starts:
307 *
308 * The last link descriptor
309 * ____________ points back to the first
310 * | |
311 * V |
312 * ___ ___ |
313 * | |->| |->|
314 * |___| |___|
315 * | |
316 * | |
317 * V V
318 * _________________________________________
319 * | | | | | | | The DMA buffer is
320 * | | | | | | | divided into 6 parts
321 * |______|______|______|______|______|______|
322 *
323 * and here's how they look after the first period is finished playing:
324 *
325 * ____________
326 * | |
327 * V |
328 * ___ ___ |
329 * | |->| |->|
330 * |___| |___|
331 * | |
332 * |______________
333 * | |
334 * V V
335 * _________________________________________
336 * | | | | | | |
337 * | | | | | | |
338 * |______|______|______|______|______|______|
339 *
340 * The first link descriptor now points to the third period. The DMA
341 * controller is currently playing the second period. When it finishes, it
342 * will jump back to the first descriptor and play the third period.
343 *
344 * There are four reasons we do this:
345 *
346 * 1. The only way to get the DMA controller to automatically restart the
347 * transfer when it gets to the end of the buffer is to use chaining
348 * mode. Basic direct mode doesn't offer that feature.
349 * 2. We need to receive an interrupt at the end of every period. The DMA
350 * controller can generate an interrupt at the end of every link transfer
351 * (aka segment). Making each period into a DMA segment will give us the
352 * interrupts we need.
353 * 3. By creating only two link descriptors, regardless of the number of
354 * periods, we do not need to reallocate the link descriptors if the
355 * number of periods changes.
356 * 4. All of the audio data is still stored in a single, contiguous DMA
357 * buffer, which is what ALSA expects. We're just dividing it into
358 * contiguous parts, and creating a link descriptor for each one.
359 */
fsl_dma_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)360 static int fsl_dma_open(struct snd_soc_component *component,
361 struct snd_pcm_substream *substream)
362 {
363 struct snd_pcm_runtime *runtime = substream->runtime;
364 struct device *dev = component->dev;
365 struct dma_object *dma =
366 container_of(component->driver, struct dma_object, dai);
367 struct fsl_dma_private *dma_private;
368 struct ccsr_dma_channel __iomem *dma_channel;
369 dma_addr_t ld_buf_phys;
370 u64 temp_link; /* Pointer to next link descriptor */
371 u32 mr;
372 int ret = 0;
373 unsigned int i;
374
375 /*
376 * Reject any DMA buffer whose size is not a multiple of the period
377 * size. We need to make sure that the DMA buffer can be evenly divided
378 * into periods.
379 */
380 ret = snd_pcm_hw_constraint_integer(runtime,
381 SNDRV_PCM_HW_PARAM_PERIODS);
382 if (ret < 0) {
383 dev_err(dev, "invalid buffer size\n");
384 return ret;
385 }
386
387 if (dma->assigned) {
388 dev_err(dev, "dma channel already assigned\n");
389 return -EBUSY;
390 }
391
392 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
393 &ld_buf_phys, GFP_KERNEL);
394 if (!dma_private) {
395 dev_err(dev, "can't allocate dma private data\n");
396 return -ENOMEM;
397 }
398 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
399 dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
400 else
401 dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
402
403 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
404 dma_private->dma_channel = dma->channel;
405 dma_private->irq = dma->irq;
406 dma_private->substream = substream;
407 dma_private->ld_buf_phys = ld_buf_phys;
408 dma_private->dma_buf_phys = substream->dma_buffer.addr;
409
410 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
411 dma_private);
412 if (ret) {
413 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
414 dma_private->irq, ret);
415 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
416 dma_private, dma_private->ld_buf_phys);
417 return ret;
418 }
419
420 dma->assigned = true;
421
422 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
423 runtime->private_data = dma_private;
424
425 /* Program the fixed DMA controller parameters */
426
427 dma_channel = dma_private->dma_channel;
428
429 temp_link = dma_private->ld_buf_phys +
430 sizeof(struct fsl_dma_link_descriptor);
431
432 for (i = 0; i < NUM_DMA_LINKS; i++) {
433 dma_private->link[i].next = cpu_to_be64(temp_link);
434
435 temp_link += sizeof(struct fsl_dma_link_descriptor);
436 }
437 /* The last link descriptor points to the first */
438 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
439
440 /* Tell the DMA controller where the first link descriptor is */
441 out_be32(&dma_channel->clndar,
442 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
443 out_be32(&dma_channel->eclndar,
444 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
445
446 /* The manual says the BCR must be clear before enabling EMP */
447 out_be32(&dma_channel->bcr, 0);
448
449 /*
450 * Program the mode register for interrupts, external master control,
451 * and source/destination hold. Also clear the Channel Abort bit.
452 */
453 mr = in_be32(&dma_channel->mr) &
454 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
455
456 /*
457 * We want External Master Start and External Master Pause enabled,
458 * because the SSI is controlling the DMA controller. We want the DMA
459 * controller to be set up in advance, and then we signal only the SSI
460 * to start transferring.
461 *
462 * We want End-Of-Segment Interrupts enabled, because this will generate
463 * an interrupt at the end of each segment (each link descriptor
464 * represents one segment). Each DMA segment is the same thing as an
465 * ALSA period, so this is how we get an interrupt at the end of every
466 * period.
467 *
468 * We want Error Interrupt enabled, so that we can get an error if
469 * the DMA controller is mis-programmed somehow.
470 */
471 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
472 CCSR_DMA_MR_EMS_EN;
473
474 /* For playback, we want the destination address to be held. For
475 capture, set the source address to be held. */
476 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
477 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
478
479 out_be32(&dma_channel->mr, mr);
480
481 return 0;
482 }
483
484 /**
485 * fsl_dma_hw_params: continue initializing the DMA links
486 *
487 * This function obtains hardware parameters about the opened stream and
488 * programs the DMA controller accordingly.
489 *
490 * One drawback of big-endian is that when copying integers of different
491 * sizes to a fixed-sized register, the address to which the integer must be
492 * copied is dependent on the size of the integer.
493 *
494 * For example, if P is the address of a 32-bit register, and X is a 32-bit
495 * integer, then X should be copied to address P. However, if X is a 16-bit
496 * integer, then it should be copied to P+2. If X is an 8-bit register,
497 * then it should be copied to P+3.
498 *
499 * So for playback of 8-bit samples, the DMA controller must transfer single
500 * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
501 * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
502 *
503 * For 24-bit samples, the offset is 1 byte. However, the DMA controller
504 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
505 * and 8 bytes at a time). So we do not support packed 24-bit samples.
506 * 24-bit data must be padded to 32 bits.
507 */
fsl_dma_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)508 static int fsl_dma_hw_params(struct snd_soc_component *component,
509 struct snd_pcm_substream *substream,
510 struct snd_pcm_hw_params *hw_params)
511 {
512 struct snd_pcm_runtime *runtime = substream->runtime;
513 struct fsl_dma_private *dma_private = runtime->private_data;
514 struct device *dev = component->dev;
515
516 /* Number of bits per sample */
517 unsigned int sample_bits =
518 snd_pcm_format_physical_width(params_format(hw_params));
519
520 /* Number of bytes per frame */
521 unsigned int sample_bytes = sample_bits / 8;
522
523 /* Bus address of SSI STX register */
524 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
525
526 /* Size of the DMA buffer, in bytes */
527 size_t buffer_size = params_buffer_bytes(hw_params);
528
529 /* Number of bytes per period */
530 size_t period_size = params_period_bytes(hw_params);
531
532 /* Pointer to next period */
533 dma_addr_t temp_addr = substream->dma_buffer.addr;
534
535 /* Pointer to DMA controller */
536 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
537
538 u32 mr; /* DMA Mode Register */
539
540 unsigned int i;
541
542 /* Initialize our DMA tracking variables */
543 dma_private->period_size = period_size;
544 dma_private->num_periods = params_periods(hw_params);
545 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
546 dma_private->dma_buf_next = dma_private->dma_buf_phys +
547 (NUM_DMA_LINKS * period_size);
548
549 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
550 /* This happens if the number of periods == NUM_DMA_LINKS */
551 dma_private->dma_buf_next = dma_private->dma_buf_phys;
552
553 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
554 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
555
556 /* Due to a quirk of the SSI's STX register, the target address
557 * for the DMA operations depends on the sample size. So we calculate
558 * that offset here. While we're at it, also tell the DMA controller
559 * how much data to transfer per sample.
560 */
561 switch (sample_bits) {
562 case 8:
563 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
564 ssi_sxx_phys += 3;
565 break;
566 case 16:
567 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
568 ssi_sxx_phys += 2;
569 break;
570 case 32:
571 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
572 break;
573 default:
574 /* We should never get here */
575 dev_err(dev, "unsupported sample size %u\n", sample_bits);
576 return -EINVAL;
577 }
578
579 /*
580 * BWC determines how many bytes are sent/received before the DMA
581 * controller checks the SSI to see if it needs to stop. BWC should
582 * always be a multiple of the frame size, so that we always transmit
583 * whole frames. Each frame occupies two slots in the FIFO. The
584 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
585 * (MR[BWC] can only represent even powers of two).
586 *
587 * To simplify the process, we set BWC to the largest value that is
588 * less than or equal to the FIFO watermark. For playback, this ensures
589 * that we transfer the maximum amount without overrunning the FIFO.
590 * For capture, this ensures that we transfer the maximum amount without
591 * underrunning the FIFO.
592 *
593 * f = SSI FIFO depth
594 * w = SSI watermark value (which equals f - 2)
595 * b = DMA bandwidth count (in bytes)
596 * s = sample size (in bytes, which equals frame_size * 2)
597 *
598 * For playback, we never transmit more than the transmit FIFO
599 * watermark, otherwise we might write more data than the FIFO can hold.
600 * The watermark is equal to the FIFO depth minus two.
601 *
602 * For capture, two equations must hold:
603 * w > f - (b / s)
604 * w >= b / s
605 *
606 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set
607 * b = s * w, which is equal to
608 * (dma_private->ssi_fifo_depth - 2) * sample_bytes.
609 */
610 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
611
612 out_be32(&dma_channel->mr, mr);
613
614 for (i = 0; i < NUM_DMA_LINKS; i++) {
615 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
616
617 link->count = cpu_to_be32(period_size);
618
619 /* The snoop bit tells the DMA controller whether it should tell
620 * the ECM to snoop during a read or write to an address. For
621 * audio, we use DMA to transfer data between memory and an I/O
622 * device (the SSI's STX0 or SRX0 register). Snooping is only
623 * needed if there is a cache, so we need to snoop memory
624 * addresses only. For playback, that means we snoop the source
625 * but not the destination. For capture, we snoop the
626 * destination but not the source.
627 *
628 * Note that failing to snoop properly is unlikely to cause
629 * cache incoherency if the period size is larger than the
630 * size of L1 cache. This is because filling in one period will
631 * flush out the data for the previous period. So if you
632 * increased period_bytes_min to a large enough size, you might
633 * get more performance by not snooping, and you'll still be
634 * okay. You'll need to update fsl_dma_update_pointers() also.
635 */
636 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
637 link->source_addr = cpu_to_be32(temp_addr);
638 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
639 upper_32_bits(temp_addr));
640
641 link->dest_addr = cpu_to_be32(ssi_sxx_phys);
642 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
643 upper_32_bits(ssi_sxx_phys));
644 } else {
645 link->source_addr = cpu_to_be32(ssi_sxx_phys);
646 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
647 upper_32_bits(ssi_sxx_phys));
648
649 link->dest_addr = cpu_to_be32(temp_addr);
650 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
651 upper_32_bits(temp_addr));
652 }
653
654 temp_addr += period_size;
655 }
656
657 return 0;
658 }
659
660 /**
661 * fsl_dma_pointer: determine the current position of the DMA transfer
662 *
663 * This function is called by ALSA when ALSA wants to know where in the
664 * stream buffer the hardware currently is.
665 *
666 * For playback, the SAR register contains the physical address of the most
667 * recent DMA transfer. For capture, the value is in the DAR register.
668 *
669 * The base address of the buffer is stored in the source_addr field of the
670 * first link descriptor.
671 */
fsl_dma_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)672 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component,
673 struct snd_pcm_substream *substream)
674 {
675 struct snd_pcm_runtime *runtime = substream->runtime;
676 struct fsl_dma_private *dma_private = runtime->private_data;
677 struct device *dev = component->dev;
678 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
679 dma_addr_t position;
680 snd_pcm_uframes_t frames;
681
682 /* Obtain the current DMA pointer, but don't read the ESAD bits if we
683 * only have 32-bit DMA addresses. This function is typically called
684 * in interrupt context, so we need to optimize it.
685 */
686 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
687 position = in_be32(&dma_channel->sar);
688 #ifdef CONFIG_PHYS_64BIT
689 position |= (u64)(in_be32(&dma_channel->satr) &
690 CCSR_DMA_ATR_ESAD_MASK) << 32;
691 #endif
692 } else {
693 position = in_be32(&dma_channel->dar);
694 #ifdef CONFIG_PHYS_64BIT
695 position |= (u64)(in_be32(&dma_channel->datr) &
696 CCSR_DMA_ATR_ESAD_MASK) << 32;
697 #endif
698 }
699
700 /*
701 * When capture is started, the SSI immediately starts to fill its FIFO.
702 * This means that the DMA controller is not started until the FIFO is
703 * full. However, ALSA calls this function before that happens, when
704 * MR.DAR is still zero. In this case, just return zero to indicate
705 * that nothing has been received yet.
706 */
707 if (!position)
708 return 0;
709
710 if ((position < dma_private->dma_buf_phys) ||
711 (position > dma_private->dma_buf_end)) {
712 dev_err(dev, "dma pointer is out of range, halting stream\n");
713 return SNDRV_PCM_POS_XRUN;
714 }
715
716 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
717
718 /*
719 * If the current address is just past the end of the buffer, wrap it
720 * around.
721 */
722 if (frames == runtime->buffer_size)
723 frames = 0;
724
725 return frames;
726 }
727
728 /**
729 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
730 *
731 * Release the resources allocated in fsl_dma_hw_params() and de-program the
732 * registers.
733 *
734 * This function can be called multiple times.
735 */
fsl_dma_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)736 static int fsl_dma_hw_free(struct snd_soc_component *component,
737 struct snd_pcm_substream *substream)
738 {
739 struct snd_pcm_runtime *runtime = substream->runtime;
740 struct fsl_dma_private *dma_private = runtime->private_data;
741
742 if (dma_private) {
743 struct ccsr_dma_channel __iomem *dma_channel;
744
745 dma_channel = dma_private->dma_channel;
746
747 /* Stop the DMA */
748 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
749 out_be32(&dma_channel->mr, 0);
750
751 /* Reset all the other registers */
752 out_be32(&dma_channel->sr, -1);
753 out_be32(&dma_channel->clndar, 0);
754 out_be32(&dma_channel->eclndar, 0);
755 out_be32(&dma_channel->satr, 0);
756 out_be32(&dma_channel->sar, 0);
757 out_be32(&dma_channel->datr, 0);
758 out_be32(&dma_channel->dar, 0);
759 out_be32(&dma_channel->bcr, 0);
760 out_be32(&dma_channel->nlndar, 0);
761 out_be32(&dma_channel->enlndar, 0);
762 }
763
764 return 0;
765 }
766
767 /**
768 * fsl_dma_close: close the stream.
769 */
fsl_dma_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)770 static int fsl_dma_close(struct snd_soc_component *component,
771 struct snd_pcm_substream *substream)
772 {
773 struct snd_pcm_runtime *runtime = substream->runtime;
774 struct fsl_dma_private *dma_private = runtime->private_data;
775 struct device *dev = component->dev;
776 struct dma_object *dma =
777 container_of(component->driver, struct dma_object, dai);
778
779 if (dma_private) {
780 if (dma_private->irq)
781 free_irq(dma_private->irq, dma_private);
782
783 /* Deallocate the fsl_dma_private structure */
784 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
785 dma_private, dma_private->ld_buf_phys);
786 substream->runtime->private_data = NULL;
787 }
788
789 dma->assigned = false;
790
791 return 0;
792 }
793
794 /**
795 * find_ssi_node -- returns the SSI node that points to its DMA channel node
796 *
797 * Although this DMA driver attempts to operate independently of the other
798 * devices, it still needs to determine some information about the SSI device
799 * that it's working with. Unfortunately, the device tree does not contain
800 * a pointer from the DMA channel node to the SSI node -- the pointer goes the
801 * other way. So we need to scan the device tree for SSI nodes until we find
802 * the one that points to the given DMA channel node. It's ugly, but at least
803 * it's contained in this one function.
804 */
find_ssi_node(struct device_node * dma_channel_np)805 static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
806 {
807 struct device_node *ssi_np, *np;
808
809 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
810 /* Check each DMA phandle to see if it points to us. We
811 * assume that device_node pointers are a valid comparison.
812 */
813 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
814 of_node_put(np);
815 if (np == dma_channel_np)
816 return ssi_np;
817
818 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
819 of_node_put(np);
820 if (np == dma_channel_np)
821 return ssi_np;
822 }
823
824 return NULL;
825 }
826
fsl_soc_dma_probe(struct platform_device * pdev)827 static int fsl_soc_dma_probe(struct platform_device *pdev)
828 {
829 struct dma_object *dma;
830 struct device_node *np = pdev->dev.of_node;
831 struct device_node *ssi_np;
832 struct resource res;
833 const uint32_t *iprop;
834 int ret;
835
836 /* Find the SSI node that points to us. */
837 ssi_np = find_ssi_node(np);
838 if (!ssi_np) {
839 dev_err(&pdev->dev, "cannot find parent SSI node\n");
840 return -ENODEV;
841 }
842
843 ret = of_address_to_resource(ssi_np, 0, &res);
844 if (ret) {
845 dev_err(&pdev->dev, "could not determine resources for %pOF\n",
846 ssi_np);
847 of_node_put(ssi_np);
848 return ret;
849 }
850
851 dma = kzalloc(sizeof(*dma), GFP_KERNEL);
852 if (!dma) {
853 of_node_put(ssi_np);
854 return -ENOMEM;
855 }
856
857 dma->dai.name = DRV_NAME;
858 dma->dai.open = fsl_dma_open;
859 dma->dai.close = fsl_dma_close;
860 dma->dai.hw_params = fsl_dma_hw_params;
861 dma->dai.hw_free = fsl_dma_hw_free;
862 dma->dai.pointer = fsl_dma_pointer;
863 dma->dai.pcm_construct = fsl_dma_new;
864
865 /* Store the SSI-specific information that we need */
866 dma->ssi_stx_phys = res.start + REG_SSI_STX0;
867 dma->ssi_srx_phys = res.start + REG_SSI_SRX0;
868
869 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
870 if (iprop)
871 dma->ssi_fifo_depth = be32_to_cpup(iprop);
872 else
873 /* Older 8610 DTs didn't have the fifo-depth property */
874 dma->ssi_fifo_depth = 8;
875
876 of_node_put(ssi_np);
877
878 ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0);
879 if (ret) {
880 dev_err(&pdev->dev, "could not register platform\n");
881 kfree(dma);
882 return ret;
883 }
884
885 dma->channel = of_iomap(np, 0);
886 dma->irq = irq_of_parse_and_map(np, 0);
887
888 dev_set_drvdata(&pdev->dev, dma);
889
890 return 0;
891 }
892
fsl_soc_dma_remove(struct platform_device * pdev)893 static void fsl_soc_dma_remove(struct platform_device *pdev)
894 {
895 struct dma_object *dma = dev_get_drvdata(&pdev->dev);
896
897 iounmap(dma->channel);
898 irq_dispose_mapping(dma->irq);
899 kfree(dma);
900 }
901
902 static const struct of_device_id fsl_soc_dma_ids[] = {
903 { .compatible = "fsl,ssi-dma-channel", },
904 {}
905 };
906 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
907
908 static struct platform_driver fsl_soc_dma_driver = {
909 .driver = {
910 .name = "fsl-pcm-audio",
911 .of_match_table = fsl_soc_dma_ids,
912 },
913 .probe = fsl_soc_dma_probe,
914 .remove = fsl_soc_dma_remove,
915 };
916
917 module_platform_driver(fsl_soc_dma_driver);
918
919 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
920 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
921 MODULE_LICENSE("GPL v2");
922