1/* $NetBSD: atomic_swap.S,v 1.8 2013/11/08 22:42:52 matt Exp $ */ 2 3/*- 4 * Copyright (c) 2007,2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and Matt Thomas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include "atomic_op_asm.h" 33 34/* 35 * While SWP{B} is sufficient on its own for pre-ARMv7 CPUs, on MP ARMv7 cores 36 * SWP{B} is disabled since it's no longer atomic among multiple CPUs. They 37 * will actually raise an UNDEFINED exception. 38 * 39 * So if we use the LDREX/STREX template, but use a SWP instruction followed 40 * by a MOV instruction (using a temporary register), that gives a handler 41 * for the SWP UNDEFINED exception enough information to "patch" this instance 42 * SWP with correct forms of LDREX/STREX. (note that this would happen even 43 * "read-only" pages. If the page gets tossed, we will get another exception 44 * and fix yet again). 45 */ 46 47ENTRY_NP(_atomic_swap_32) 48 mov ip, r0 491: 50#ifdef _ARM_ARCH_6 51 ldrex r0, [ip] 52 cmp r0, r1 53#ifdef __thumb__ 54 beq 99f 55 strex r3, r1, [ip] 56 cmp r3, #0 57#else 58 strexne r3, r1, [ip] 59 cmpne r3, #0 60#endif 61#else 62 swp r0, r1, [ip] 63 cmp r0, r1 64 movnes r3, #0 65 cmpne r3, #0 66#endif 67 bne 1b 68#ifdef _ARM_ARCH_7 69 dmb 70#else 71 mcr p15, 0, r3, c7, c10, 5 /* data memory barrier */ 72#endif 7399: 74 RET 75END(_atomic_swap_32) 76 77ATOMIC_OP_ALIAS(atomic_swap_32,_atomic_swap_32) 78ATOMIC_OP_ALIAS(atomic_swap_uint,_atomic_swap_32) 79ATOMIC_OP_ALIAS(atomic_swap_ulong,_atomic_swap_32) 80ATOMIC_OP_ALIAS(atomic_swap_ptr,_atomic_swap_32) 81STRONG_ALIAS(__sync_lock_test_and_set_4,_atomic_swap_32) 82STRONG_ALIAS(_atomic_swap_uint,_atomic_swap_32) 83STRONG_ALIAS(_atomic_swap_ulong,_atomic_swap_32) 84STRONG_ALIAS(_atomic_swap_ptr,_atomic_swap_32) 85 86ENTRY_NP(__sync_lock_release_4) 87 mov r1, #0 88 strb r1, [r0] 89 RET 90END(__sync_lock_release_4) 91 92ENTRY_NP(_atomic_swap_8) 93 mov ip, r0 941: 95#ifdef _ARM_ARCH_6 96 ldrexb r0, [ip] 97 strexb r3, r1, [ip] 98#else 99 swpb r0, r1, [ip] 100 mov r3, #0 101#endif 102 cmp r3, #0 103 bne 1b 104#ifdef _ARM_ARCH_7 105 dmb 106#else 107 mcr p15, 0, ip, c7, c10, 5 /* data memory barrier */ 108#endif 109 RET 110END(_atomic_swap_8) 111 112ATOMIC_OP_ALIAS(atomic_swap_8,_atomic_swap_8) 113ATOMIC_OP_ALIAS(atomic_swap_char,_atomic_swap_8) 114ATOMIC_OP_ALIAS(atomic_swap_uchar,_atomic_swap_8) 115STRONG_ALIAS(__sync_lock_test_and_set_1,_atomic_swap_8) 116STRONG_ALIAS(_atomic_swap_char,_atomic_swap_8) 117STRONG_ALIAS(_atomic_swap_uchar,_atomic_swap_8) 118 119ENTRY_NP(__sync_lock_release_1) 120 mov r1, #0 121 strb r1, [r0] 122 RET 123END(__sync_lock_release_1) 124