1//===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TableGen definitions from which the ARM NEON header 11// file will be generated. See ARM document DUI0348B. 12// 13//===----------------------------------------------------------------------===// 14 15class Op; 16 17def OP_NONE : Op; 18def OP_UNAVAILABLE : Op; 19def OP_ADD : Op; 20def OP_ADDL : Op; 21def OP_ADDLHi : Op; 22def OP_ADDW : Op; 23def OP_ADDWHi : Op; 24def OP_SUB : Op; 25def OP_SUBL : Op; 26def OP_SUBLHi : Op; 27def OP_SUBW : Op; 28def OP_SUBWHi : Op; 29def OP_MUL : Op; 30def OP_MLA : Op; 31def OP_MLAL : Op; 32def OP_MULLHi : Op; 33def OP_MLALHi : Op; 34def OP_MLS : Op; 35def OP_MLSL : Op; 36def OP_MLSLHi : Op; 37def OP_MUL_N : Op; 38def OP_MLA_N : Op; 39def OP_MLS_N : Op; 40def OP_MLAL_N : Op; 41def OP_MLSL_N : Op; 42def OP_MUL_LN: Op; 43def OP_MULX_LN: Op; 44def OP_MULL_LN : Op; 45def OP_MULLHi_LN : Op; 46def OP_MLA_LN: Op; 47def OP_MLS_LN: Op; 48def OP_MLAL_LN : Op; 49def OP_MLALHi_LN : Op; 50def OP_MLSL_LN : Op; 51def OP_MLSLHi_LN : Op; 52def OP_QDMULL_LN : Op; 53def OP_QDMULLHi_LN : Op; 54def OP_QDMLAL_LN : Op; 55def OP_QDMLALHi_LN : Op; 56def OP_QDMLSL_LN : Op; 57def OP_QDMLSLHi_LN : Op; 58def OP_QDMULH_LN : Op; 59def OP_QRDMULH_LN : Op; 60def OP_FMS_LN : Op; 61def OP_FMS_LNQ : Op; 62def OP_TRN1 : Op; 63def OP_ZIP1 : Op; 64def OP_UZP1 : Op; 65def OP_TRN2 : Op; 66def OP_ZIP2 : Op; 67def OP_UZP2 : Op; 68def OP_EQ : Op; 69def OP_GE : Op; 70def OP_LE : Op; 71def OP_GT : Op; 72def OP_LT : Op; 73def OP_NEG : Op; 74def OP_NOT : Op; 75def OP_AND : Op; 76def OP_OR : Op; 77def OP_XOR : Op; 78def OP_ANDN : Op; 79def OP_ORN : Op; 80def OP_CAST : Op; 81def OP_HI : Op; 82def OP_LO : Op; 83def OP_CONC : Op; 84def OP_DUP : Op; 85def OP_DUP_LN: Op; 86def OP_SEL : Op; 87def OP_REV64 : Op; 88def OP_REV32 : Op; 89def OP_REV16 : Op; 90def OP_XTN : Op; 91def OP_SQXTUN : Op; 92def OP_QXTN : Op; 93def OP_VCVT_NA_HI : Op; 94def OP_VCVT_EX_HI : Op; 95def OP_VCVTX_HI : Op; 96def OP_REINT : Op; 97def OP_ADDHNHi : Op; 98def OP_RADDHNHi : Op; 99def OP_SUBHNHi : Op; 100def OP_RSUBHNHi : Op; 101def OP_ABDL : Op; 102def OP_ABDLHi : Op; 103def OP_ABA : Op; 104def OP_ABAL : Op; 105def OP_ABALHi : Op; 106def OP_QDMULLHi : Op; 107def OP_QDMLALHi : Op; 108def OP_QDMLSLHi : Op; 109def OP_DIV : Op; 110def OP_LONG_HI : Op; 111def OP_NARROW_HI : Op; 112def OP_MOVL_HI : Op; 113def OP_COPY_LN : Op; 114def OP_COPYQ_LN : Op; 115def OP_COPY_LNQ : Op; 116def OP_SCALAR_MUL_LN : Op; 117def OP_SCALAR_MUL_LNQ : Op; 118def OP_SCALAR_MULX_LN : Op; 119def OP_SCALAR_MULX_LNQ : Op; 120def OP_SCALAR_VMULX_LN : Op; 121def OP_SCALAR_VMULX_LNQ : Op; 122def OP_SCALAR_QDMULL_LN : Op; 123def OP_SCALAR_QDMULL_LNQ : Op; 124def OP_SCALAR_QDMULH_LN : Op; 125def OP_SCALAR_QDMULH_LNQ : Op; 126def OP_SCALAR_QRDMULH_LN : Op; 127def OP_SCALAR_QRDMULH_LNQ : Op; 128 129class Inst <string n, string p, string t, Op o> { 130 string Name = n; 131 string Prototype = p; 132 string Types = t; 133 Op Operand = o; 134 bit isShift = 0; 135 bit isScalarShift = 0; 136 bit isVCVT_N = 0; 137 bit isA64 = 0; 138 bit isCrypto = 0; 139 140 // Certain intrinsics have different names than their representative 141 // instructions. This field allows us to handle this correctly when we 142 // are generating tests. 143 string InstName = ""; 144 145 // Certain intrinsics even though they are not a WOpInst or LOpInst, 146 // generate a WOpInst/LOpInst instruction (see below for definition 147 // of a WOpInst/LOpInst). For testing purposes we need to know 148 // this. Ex: vset_lane which outputs vmov instructions. 149 bit isHiddenWInst = 0; 150 bit isHiddenLInst = 0; 151} 152 153// The following instruction classes are implemented via builtins. 154// These declarations are used to generate Builtins.def: 155// 156// SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 157// IInst: Instruction with generic integer suffix (e.g., "i8") 158// WInst: Instruction with only bit size suffix (e.g., "8") 159class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 160class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 161class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 162 163// The following instruction classes are implemented via operators 164// instead of builtins. As such these declarations are only used for 165// the purpose of generating tests. 166// 167// SOpInst: Instruction with signed/unsigned suffix (e.g., "s8", 168// "u8", "p8"). 169// IOpInst: Instruction with generic integer suffix (e.g., "i8"). 170// WOpInst: Instruction with bit size only suffix (e.g., "8"). 171// LOpInst: Logical instruction with no bit size suffix. 172// NoTestOpInst: Intrinsic that has no corresponding instruction. 173class SOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 174class IOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 175class WOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 176class LOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 177class NoTestOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 178 179// prototype: return (arg, arg, ...) 180// v: void 181// t: best-fit integer (int/poly args) 182// x: signed integer (int/float args) 183// u: unsigned integer (int/float args) 184// f: float (int args) 185// d: default 186// g: default, ignore 'Q' size modifier. 187// j: default, force 'Q' size modifier. 188// w: double width elements, same num elts 189// n: double width elements, half num elts 190// h: half width elements, double num elts 191// q: half width elements, quad num elts 192// e: half width elements, double num elts, unsigned 193// m: half width elements, same num elts 194// i: constant int 195// l: constant uint64 196// s: scalar of element type 197// z: scalar of half width element type, signed 198// r: scalar of double width element type, signed 199// a: scalar of element type (splat to vector type) 200// b: scalar of unsigned integer/long type (int/float args) 201// $: scalar of signed integer/long type (int/float args) 202// y: scalar of float 203// o: scalar of double 204// k: default elt width, double num elts 205// 2,3,4: array of default vectors 206// B,C,D: array of default elts, force 'Q' size modifier. 207// p: pointer type 208// c: const pointer type 209 210// sizes: 211// c: char 212// s: short 213// i: int 214// l: long 215// f: float 216// h: half-float 217// d: double 218 219// size modifiers: 220// S: scalar, only used for function mangling. 221// U: unsigned 222// Q: 128b 223// H: 128b without mangling 'q' 224// P: polynomial 225 226//////////////////////////////////////////////////////////////////////////////// 227// E.3.1 Addition 228def VADD : IOpInst<"vadd", "ddd", 229 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 230def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>; 231def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>; 232def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 233def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 234def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 235def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">; 236def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">; 237 238//////////////////////////////////////////////////////////////////////////////// 239// E.3.2 Multiplication 240def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 241def VMULP : SInst<"vmul", "ddd", "PcQPc">; 242def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 243def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>; 244def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 245def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>; 246def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">; 247def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">; 248def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">; 249def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">; 250def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">; 251def VQDMULL : SInst<"vqdmull", "wdd", "si">; 252 253//////////////////////////////////////////////////////////////////////////////// 254// E.3.3 Subtraction 255def VSUB : IOpInst<"vsub", "ddd", 256 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 257def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>; 258def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>; 259def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 260def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 261def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">; 262def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">; 263 264//////////////////////////////////////////////////////////////////////////////// 265// E.3.4 Comparison 266def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 267def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 268let InstName = "vcge" in 269def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 270def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 271let InstName = "vcgt" in 272def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 273let InstName = "vacge" in { 274def VCAGE : IInst<"vcage", "udd", "fQf">; 275def VCALE : IInst<"vcale", "udd", "fQf">; 276} 277let InstName = "vacgt" in { 278def VCAGT : IInst<"vcagt", "udd", "fQf">; 279def VCALT : IInst<"vcalt", "udd", "fQf">; 280} 281def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">; 282 283//////////////////////////////////////////////////////////////////////////////// 284// E.3.5 Absolute Difference 285def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 286def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>; 287def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 288def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>; 289 290//////////////////////////////////////////////////////////////////////////////// 291// E.3.6 Max/Min 292def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 293def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 294 295//////////////////////////////////////////////////////////////////////////////// 296// E.3.7 Pairwise Addition 297def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">; 298def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">; 299def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">; 300 301//////////////////////////////////////////////////////////////////////////////// 302// E.3.8-9 Folding Max/Min 303def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">; 304def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">; 305 306//////////////////////////////////////////////////////////////////////////////// 307// E.3.10 Reciprocal/Sqrt 308def VRECPS : IInst<"vrecps", "ddd", "fQf">; 309def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">; 310 311//////////////////////////////////////////////////////////////////////////////// 312// E.3.11 Shifts by signed variable 313def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 314def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 315def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 316def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 317 318//////////////////////////////////////////////////////////////////////////////// 319// E.3.12 Shifts by constant 320let isShift = 1 in { 321def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 322def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 323def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 324def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 325def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 326def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 327def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">; 328def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">; 329def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">; 330def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">; 331def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">; 332def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">; 333def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">; 334def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">; 335 336//////////////////////////////////////////////////////////////////////////////// 337// E.3.13 Shifts with insert 338def VSRI_N : WInst<"vsri_n", "dddi", 339 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 340def VSLI_N : WInst<"vsli_n", "dddi", 341 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 342} 343 344//////////////////////////////////////////////////////////////////////////////// 345// E.3.14 Loads and stores of a single vector 346def VLD1 : WInst<"vld1", "dc", 347 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 348def VLD1_LANE : WInst<"vld1_lane", "dcdi", 349 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 350def VLD1_DUP : WInst<"vld1_dup", "dc", 351 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 352def VST1 : WInst<"vst1", "vpd", 353 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 354def VST1_LANE : WInst<"vst1_lane", "vpdi", 355 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 356 357//////////////////////////////////////////////////////////////////////////////// 358// E.3.15 Loads and stores of an N-element structure 359def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 360def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 361def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 362def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">; 363def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">; 364def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">; 365def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 366def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 367def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 368def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 369def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 370def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 371def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 372def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 373def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 374 375//////////////////////////////////////////////////////////////////////////////// 376// E.3.16 Extract lanes from a vector 377let InstName = "vmov" in 378def VGET_LANE : IInst<"vget_lane", "sdi", 379 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 380 381//////////////////////////////////////////////////////////////////////////////// 382// E.3.17 Set lanes within a vector 383let InstName = "vmov" in 384def VSET_LANE : IInst<"vset_lane", "dsdi", 385 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 386 387//////////////////////////////////////////////////////////////////////////////// 388// E.3.18 Initialize a vector from bit pattern 389def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>; 390 391//////////////////////////////////////////////////////////////////////////////// 392// E.3.19 Set all lanes to same value 393let InstName = "vmov" in { 394def VDUP_N : WOpInst<"vdup_n", "ds", 395 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 396def VMOV_N : WOpInst<"vmov_n", "ds", 397 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 398} 399let InstName = "" in 400def VDUP_LANE: WOpInst<"vdup_lane", "dgi", 401 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", 402 OP_DUP_LN>; 403 404//////////////////////////////////////////////////////////////////////////////// 405// E.3.20 Combining vectors 406def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>; 407 408//////////////////////////////////////////////////////////////////////////////// 409// E.3.21 Splitting vectors 410let InstName = "vmov" in { 411def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>; 412def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; 413} 414 415//////////////////////////////////////////////////////////////////////////////// 416// E.3.22 Converting vectors 417def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; 418def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; 419def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">; 420def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; 421def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">; 422let isVCVT_N = 1 in { 423def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; 424def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; 425def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; 426} 427def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; 428def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; 429def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; 430def VQMOVUN : SInst<"vqmovun", "ek", "sil">; 431 432//////////////////////////////////////////////////////////////////////////////// 433// E.3.23-24 Table lookup, Extended table lookup 434let InstName = "vtbl" in { 435def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">; 436def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">; 437def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">; 438def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">; 439} 440let InstName = "vtbx" in { 441def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">; 442def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">; 443def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">; 444def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">; 445} 446 447//////////////////////////////////////////////////////////////////////////////// 448// E.3.25 Operations with a scalar value 449def VMLA_LANE : IOpInst<"vmla_lane", "dddgi", 450 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 451def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>; 452def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 453def VMLS_LANE : IOpInst<"vmls_lane", "dddgi", 454 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 455def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>; 456def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>; 457def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 458def VMUL_LANE : IOpInst<"vmul_lane", "ddgi", 459 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 460def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">; 461def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>; 462def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">; 463def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>; 464def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">; 465def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>; 466def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">; 467def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>; 468def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 469def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>; 470def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">; 471def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 472def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>; 473def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">; 474 475//////////////////////////////////////////////////////////////////////////////// 476// E.3.26 Vector Extract 477def VEXT : WInst<"vext", "dddi", 478 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 479 480//////////////////////////////////////////////////////////////////////////////// 481// E.3.27 Reverse vector elements 482def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 483 OP_REV64>; 484def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 485def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>; 486 487//////////////////////////////////////////////////////////////////////////////// 488// E.3.28 Other single operand arithmetic 489def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">; 490def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">; 491def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>; 492def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">; 493def VCLS : SInst<"vcls", "dd", "csiQcQsQi">; 494def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">; 495def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">; 496def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">; 497def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">; 498 499//////////////////////////////////////////////////////////////////////////////// 500// E.3.29 Logical operations 501def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 502def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 503def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 504def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 505def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 506def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 507let isHiddenLInst = 1 in 508def VBSL : SInst<"vbsl", "dudd", 509 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 510 511//////////////////////////////////////////////////////////////////////////////// 512// E.3.30 Transposition operations 513def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 514def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 515def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 516 517//////////////////////////////////////////////////////////////////////////////// 518// E.3.31 Vector reinterpret cast operations 519def VREINTERPRET 520 : NoTestOpInst<"vreinterpret", "dd", 521 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT>; 522 523//////////////////////////////////////////////////////////////////////////////// 524// Vector fused multiply-add operations 525 526def VFMA : SInst<"vfma", "dddd", "fQf">; 527 528//////////////////////////////////////////////////////////////////////////////// 529// AArch64 Intrinsics 530 531let isA64 = 1 in { 532 533//////////////////////////////////////////////////////////////////////////////// 534// Load/Store 535// With additional QUl, Ql, d, Qd, Pl, QPl type. 536def LD1 : WInst<"vld1", "dc", 537 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 538def LD2 : WInst<"vld2", "2c", 539 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 540def LD3 : WInst<"vld3", "3c", 541 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 542def LD4 : WInst<"vld4", "4c", 543 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 544def ST1 : WInst<"vst1", "vpd", 545 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 546def ST2 : WInst<"vst2", "vp2", 547 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 548def ST3 : WInst<"vst3", "vp3", 549 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 550def ST4 : WInst<"vst4", "vp4", 551 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 552 553def LD1_X2 : WInst<"vld1_x2", "2c", 554 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 555def LD3_x3 : WInst<"vld1_x3", "3c", 556 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 557def LD4_x4 : WInst<"vld1_x4", "4c", 558 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 559 560def ST1_X2 : WInst<"vst1_x2", "vp2", 561 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 562def ST1_X3 : WInst<"vst1_x3", "vp3", 563 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 564def ST1_X4 : WInst<"vst1_x4", "vp4", 565 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 566 567// With additional QUl, Ql, d, Qd, Pl, QPl type. 568def LD1_LANE : WInst<"vld1_lane", "dcdi", 569 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 570def LD2_LANE : WInst<"vld2_lane", "2c2i", 571 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 572def LD3_LANE : WInst<"vld3_lane", "3c3i", 573 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 574def LD4_LANE : WInst<"vld4_lane", "4c4i", 575 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 576def ST1_LANE : WInst<"vst1_lane", "vpdi", 577 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 578def ST2_LANE : WInst<"vst2_lane", "vp2i", 579 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 580def ST3_LANE : WInst<"vst3_lane", "vp3i", 581 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 582def ST4_LANE : WInst<"vst4_lane", "vp4i", 583 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 584 585def LD1_DUP : WInst<"vld1_dup", "dc", 586 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 587def LD2_DUP : WInst<"vld2_dup", "2c", 588 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 589def LD3_DUP : WInst<"vld3_dup", "3c", 590 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 591def LD4_DUP : WInst<"vld4_dup", "4c", 592 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 593 594//////////////////////////////////////////////////////////////////////////////// 595// Addition 596// With additional Qd type. 597def ADD : IOpInst<"vadd", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", OP_ADD>; 598 599//////////////////////////////////////////////////////////////////////////////// 600// Subtraction 601// With additional Qd type. 602def SUB : IOpInst<"vsub", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", OP_SUB>; 603 604//////////////////////////////////////////////////////////////////////////////// 605// Multiplication 606// With additional Qd type. 607def MUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MUL>; 608def MLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLA>; 609def MLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLS>; 610 611//////////////////////////////////////////////////////////////////////////////// 612// Multiplication Extended 613def MULX : SInst<"vmulx", "ddd", "fdQfQd">; 614 615//////////////////////////////////////////////////////////////////////////////// 616// Division 617def FDIV : IOpInst<"vdiv", "ddd", "fQfQd", OP_DIV>; 618 619//////////////////////////////////////////////////////////////////////////////// 620// Vector fused multiply-add operations 621// With additional Qd type. 622def FMLA : SInst<"vfma", "dddd", "fQfQd">; 623def FMLS : SInst<"vfms", "dddd", "fQfQd">; 624 625//////////////////////////////////////////////////////////////////////////////// 626// Logical operations 627// With additional Qd, Ql, QPl type. 628def BSL : SInst<"vbsl", "dudd", 629 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPsQdPlQPl">; 630 631//////////////////////////////////////////////////////////////////////////////// 632// Absolute Difference 633// With additional Qd type. 634def ABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 635 636//////////////////////////////////////////////////////////////////////////////// 637// saturating absolute/negate 638// With additional Qd/Ql type. 639def ABS : SInst<"vabs", "dd", "csifQcQsQiQfQlQd">; 640def QABS : SInst<"vqabs", "dd", "csiQcQsQiQl">; 641def NEG : SOpInst<"vneg", "dd", "csifQcQsQiQfQdQl", OP_NEG>; 642def QNEG : SInst<"vqneg", "dd", "csiQcQsQiQl">; 643 644//////////////////////////////////////////////////////////////////////////////// 645// Signed Saturating Accumulated of Unsigned Value 646def SUQADD : SInst<"vuqadd", "ddd", "csiQcQsQiQl">; 647 648//////////////////////////////////////////////////////////////////////////////// 649// Unsigned Saturating Accumulated of Signed Value 650def USQADD : SInst<"vsqadd", "ddd", "UcUsUiQUcQUsQUiQUl">; 651 652//////////////////////////////////////////////////////////////////////////////// 653// Reciprocal/Sqrt 654// With additional Qd type. 655def FRECPS : IInst<"vrecps", "ddd", "fQfQd">; 656def FRSQRTS : IInst<"vrsqrts", "ddd", "fQfQd">; 657 658//////////////////////////////////////////////////////////////////////////////// 659// bitwise reverse 660def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">; 661 662//////////////////////////////////////////////////////////////////////////////// 663// Integer extract and narrow to high 664def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>; 665 666//////////////////////////////////////////////////////////////////////////////// 667// Signed integer saturating extract and unsigned narrow to high 668def SQXTUN2 : SOpInst<"vqmovun_high", "qhk", "sil", OP_SQXTUN>; 669 670//////////////////////////////////////////////////////////////////////////////// 671// Integer saturating extract and narrow to high 672def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>; 673 674//////////////////////////////////////////////////////////////////////////////// 675// Converting vectors 676def VCVT_HIGH_F16 : SOpInst<"vcvt_high_f16", "qhj", "f", OP_VCVT_NA_HI>; 677def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI>; 678def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "fj", "d">; 679def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI>; 680def VCVT_F64_F32 : SInst<"vcvt_f64", "wd", "f">; 681def VCVT_F64 : SInst<"vcvt_f64", "fd", "QlQUl">; 682def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI>; 683def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">; 684def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>; 685def FRINTN : SInst<"vrndn", "dd", "fQfQd">; 686def FRINTA : SInst<"vrnda", "dd", "fQfQd">; 687def FRINTP : SInst<"vrndp", "dd", "fQfQd">; 688def FRINTM : SInst<"vrndm", "dd", "fQfQd">; 689def FRINTX : SInst<"vrndx", "dd", "fQfQd">; 690def FRINTZ : SInst<"vrnd", "dd", "fQfQd">; 691def FRINTI : SInst<"vrndi", "dd", "fQfQd">; 692def VCVT_S64 : SInst<"vcvt_s64", "xd", "Qd">; 693def VCVT_U64 : SInst<"vcvt_u64", "ud", "Qd">; 694def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">; 695def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "Qd">; 696def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">; 697def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "Qd">; 698def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">; 699def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "Qd">; 700def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">; 701def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "Qd">; 702def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">; 703def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "Qd">; 704def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">; 705def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "Qd">; 706def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">; 707def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "Qd">; 708def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">; 709def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "Qd">; 710def FRECPE : SInst<"vrecpe", "dd", "fUiQfQUiQd">; 711def FRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUiQd">; 712def FSQRT : SInst<"vsqrt", "dd", "fQfQd">; 713 714//////////////////////////////////////////////////////////////////////////////// 715// Comparison 716// With additional Qd, Ql, QPl type. 717def VVCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPcPlQPl", 718 OP_EQ>; 719def FCAGE : IInst<"vcage", "udd", "fQfQd">; 720def FCAGT : IInst<"vcagt", "udd", "fQfQd">; 721def FCALE : IInst<"vcale", "udd", "fQfQd">; 722def FCALT : IInst<"vcalt", "udd", "fQfQd">; 723// With additional Ql, QUl, Qd types. 724def CMTST : WInst<"vtst", "udd", 725 "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPslUlQlQUlPlQPl">; 726def CFMEQ : SOpInst<"vceq", "udd", 727 "csifUcUsUiPcQcQsQiQlQfQUcQUsQUiQUlQPcQd", OP_EQ>; 728def CFMGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_GE>; 729def CFMLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_LE>; 730def CFMGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_GT>; 731def CFMLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_LT>; 732 733def CMEQ : SInst<"vceqz", "ud", 734 "csifUcUsUiPcPsQcQsQiQlQfQUcQUsQUiQUlQPcQPsQd">; 735def CMGE : SInst<"vcgez", "ud", "csifdQcQsQiQlQfQd">; 736def CMLE : SInst<"vclez", "ud", "csifdQcQsQiQlQfQd">; 737def CMGT : SInst<"vcgtz", "ud", "csifdQcQsQiQlQfQd">; 738def CMLT : SInst<"vcltz", "ud", "csifdQcQsQiQlQfQd">; 739 740//////////////////////////////////////////////////////////////////////////////// 741// Max/Min Integer 742// With additional Qd type. 743def MAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 744def MIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 745 746//////////////////////////////////////////////////////////////////////////////// 747// MaxNum/MinNum Floating Point 748def FMAXNM : SInst<"vmaxnm", "ddd", "fQfQd">; 749def FMINNM : SInst<"vminnm", "ddd", "fQfQd">; 750 751//////////////////////////////////////////////////////////////////////////////// 752// Pairwise Max/Min 753// With additional Qc Qs Qi QUc QUs QUi Qf Qd types. 754def MAXP : SInst<"vpmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 755def MINP : SInst<"vpmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 756 757//////////////////////////////////////////////////////////////////////////////// 758// Pairwise MaxNum/MinNum Floating Point 759def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">; 760def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">; 761 762//////////////////////////////////////////////////////////////////////////////// 763// Pairwise Addition 764// With additional Qc Qs Qi QUc QUs QUi Qf Qd types. 765def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 766 767//////////////////////////////////////////////////////////////////////////////// 768// Shifts by constant 769let isShift = 1 in { 770// Left shift long high 771def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi", 772 OP_LONG_HI>; 773 774//////////////////////////////////////////////////////////////////////////////// 775// Shifts with insert, with additional Ql, QPl type. 776def SRI_N : WInst<"vsri_n", "dddi", 777 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPsPlQPl">; 778def SLI_N : WInst<"vsli_n", "dddi", 779 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPsPlQPl">; 780 781// Right shift narrow high 782def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi", 783 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 784def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi", 785 "HsHiHl", OP_NARROW_HI>; 786def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi", 787 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 788def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi", 789 "HsHiHl", OP_NARROW_HI>; 790def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi", 791 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 792def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi", 793 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 794} 795 796//////////////////////////////////////////////////////////////////////////////// 797// Converting vectors 798def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>; 799 800let isVCVT_N = 1 in { 801def CVTF_N_F64 : SInst<"vcvt_n_f64", "fdi", "QlQUl">; 802def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "Qd">; 803def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "Qd">; 804} 805 806//////////////////////////////////////////////////////////////////////////////// 807// 3VDiff class using high 64-bit in operands 808def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>; 809def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>; 810def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>; 811def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>; 812 813def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>; 814def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>; 815 816def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>; 817def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>; 818def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>; 819 820def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>; 821def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>; 822def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>; 823def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>; 824 825def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>; 826def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>; 827def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>; 828 829//////////////////////////////////////////////////////////////////////////////// 830// Extract or insert element from vector 831def GET_LANE : IInst<"vget_lane", "sdi", 832 "csilPcPsUcUsUiUlQcQsQiQlQUcQUsQUiQUlPcPsQPcQPsfdQfQdPlQPl">; 833def SET_LANE : IInst<"vset_lane", "dsdi", 834 "csilPcPsUcUsUiUlQcQsQiQlQUcQUsQUiQUlPcPsQPcQPsfdQfQdPlQPl">; 835def COPY_LANE : IOpInst<"vcopy_lane", "ddidi", 836 "csiPcPsUcUsUiPcPsfPl", OP_COPY_LN>; 837def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi", 838 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPYQ_LN>; 839def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki", 840 "csiPcPsUcUsUif", OP_COPY_LNQ>; 841def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi", 842 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfdQPl", OP_COPY_LN>; 843 844//////////////////////////////////////////////////////////////////////////////// 845// Set all lanes to same value 846def VDUP_LANE1: WOpInst<"vdup_lane", "dgi", 847 "csilPcPsUcUsUiUlhfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 848 OP_DUP_LN>; 849def VDUP_LANE2: WOpInst<"vdup_laneq", "dki", 850 "csilPcPsUcUsUiUlhfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 851 OP_DUP_LN>; 852def DUP_N : WOpInst<"vdup_n", "ds", 853 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUldQdPlQPl", 854 OP_DUP>; 855def MOV_N : WOpInst<"vmov_n", "ds", 856 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUldQd", 857 OP_DUP>; 858 859//////////////////////////////////////////////////////////////////////////////// 860// Combining vectors, with additional Pl 861def COMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPsPl", OP_CONC>; 862 863//////////////////////////////////////////////////////////////////////////////// 864//Initialize a vector from bit pattern, with additional Pl 865def CREATE : NoTestOpInst<"vcreate", "dl", "csihfdUcUsUiUlPcPslPl", OP_CAST>; 866 867//////////////////////////////////////////////////////////////////////////////// 868 869def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji", 870 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 871def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji", 872 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 873 874def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">; 875def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd">; 876def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>; 877def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>; 878 879def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>; 880def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi", 881 OP_MLALHi_LN>; 882def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi", 883 OP_MLALHi_LN>; 884def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>; 885def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi", 886 OP_MLSLHi_LN>; 887def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi", 888 OP_MLSLHi_LN>; 889 890def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>; 891def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si", 892 OP_QDMLALHi_LN>; 893def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si", 894 OP_QDMLALHi_LN>; 895def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>; 896def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si", 897 OP_QDMLSLHi_LN>; 898def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si", 899 OP_QDMLSLHi_LN>; 900 901// Newly add double parameter for vmul_lane in aarch64 902// Note: d type is handled by SCALAR_VMUL_LANE 903def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>; 904 905// Note: d type is handled by SCALAR_VMUL_LANEQ 906def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji", 907 "sifUsUiQsQiQfQUsQUiQfQd", OP_MUL_LN>; 908def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>; 909def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi", 910 OP_MULLHi_LN>; 911def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi", 912 OP_MULLHi_LN>; 913 914def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>; 915def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si", 916 OP_QDMULLHi_LN>; 917def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si", 918 OP_QDMULLHi_LN>; 919 920def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>; 921def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>; 922 923// Note: d type implemented by SCALAR_VMULX_LANE 924def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>; 925// Note: d type is implemented by SCALAR_VMULX_LANEQ 926def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>; 927 928//////////////////////////////////////////////////////////////////////////////// 929// Across vectors class 930def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">; 931def VMAXV : SInst<"vmaxv", "sd", "csiUcUsUiQcQsQiQUcQUsQUiQf">; 932def VMINV : SInst<"vminv", "sd", "csiUcUsUiQcQsQiQUcQUsQUiQf">; 933def VADDV : SInst<"vaddv", "sd", "csiUcUsUiQcQsQiQUcQUsQUi">; 934def FMAXNMV : SInst<"vmaxnmv", "sd", "Qf">; 935def FMINNMV : SInst<"vminnmv", "sd", "Qf">; 936 937//////////////////////////////////////////////////////////////////////////////// 938// Newly added Vector Extract for f64 939def VEXT_A64 : WInst<"vext", "dddi", 940 "cUcPcsUsPsiUilUlfdQcQUcQPcQsQUsQPsQiQUiQlQUlQfQdPlQPl">; 941 942//////////////////////////////////////////////////////////////////////////////// 943// Crypto 944let isCrypto = 1 in { 945def AESE : SInst<"vaese", "ddd", "QUc">; 946def AESD : SInst<"vaesd", "ddd", "QUc">; 947def AESMC : SInst<"vaesmc", "dd", "QUc">; 948def AESIMC : SInst<"vaesimc", "dd", "QUc">; 949 950def SHA1H : SInst<"vsha1h", "ss", "Ui">; 951def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">; 952def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">; 953 954def SHA1C : SInst<"vsha1c", "ddsd", "QUi">; 955def SHA1P : SInst<"vsha1p", "ddsd", "QUi">; 956def SHA1M : SInst<"vsha1m", "ddsd", "QUi">; 957def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">; 958def SHA256H : SInst<"vsha256h", "dddd", "QUi">; 959def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">; 960def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">; 961} 962 963//////////////////////////////////////////////////////////////////////////////// 964// Permutation 965def VTRN1 : SOpInst<"vtrn1", "ddd", 966 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>; 967def VZIP1 : SOpInst<"vzip1", "ddd", 968 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>; 969def VUZP1 : SOpInst<"vuzp1", "ddd", 970 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>; 971def VTRN2 : SOpInst<"vtrn2", "ddd", 972 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>; 973def VZIP2 : SOpInst<"vzip2", "ddd", 974 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>; 975def VUZP2 : SOpInst<"vuzp2", "ddd", 976 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>; 977 978//////////////////////////////////////////////////////////////////////////////// 979// Table lookup 980let InstName = "vtbl" in { 981def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">; 982def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">; 983def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">; 984def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">; 985} 986let InstName = "vtbx" in { 987def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">; 988def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">; 989def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">; 990def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">; 991} 992 993//////////////////////////////////////////////////////////////////////////////// 994// Vector reinterpret cast operations 995// With additional d, Qd, pl, Qpl types 996def REINTERPRET 997 : NoTestOpInst<"vreinterpret", "dd", 998 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPl", OP_REINT>; 999 1000 1001//////////////////////////////////////////////////////////////////////////////// 1002// Scalar Intrinsics 1003// Scalar Arithmetic 1004 1005// Scalar Addition 1006def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">; 1007// Scalar Saturating Add 1008def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1009 1010// Scalar Subtraction 1011def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">; 1012// Scalar Saturating Sub 1013def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1014 1015let InstName = "vmov" in { 1016def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "csilhfdUcUsUiUlPcPsPl", 1017 OP_HI>; 1018def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "csilhfdUcUsUiUlPcPsPl", 1019 OP_LO>; 1020} 1021 1022//////////////////////////////////////////////////////////////////////////////// 1023// Scalar Shift 1024// Scalar Shift Left 1025def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">; 1026// Scalar Saturating Shift Left 1027def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1028// Scalar Saturating Rounding Shift Left 1029def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1030// Scalar Shift Rouding Left 1031def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">; 1032 1033//////////////////////////////////////////////////////////////////////////////// 1034// Scalar Shift (Immediate) 1035let isScalarShift = 1 in { 1036// Signed/Unsigned Shift Right (Immediate) 1037def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">; 1038// Signed/Unsigned Rounding Shift Right (Immediate) 1039def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">; 1040 1041// Signed/Unsigned Shift Right and Accumulate (Immediate) 1042def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">; 1043// Signed/Unsigned Rounding Shift Right and Accumulate (Immediate) 1044def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">; 1045 1046// Shift Left (Immediate) 1047def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">; 1048// Signed/Unsigned Saturating Shift Left (Immediate) 1049def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">; 1050// Signed Saturating Shift Left Unsigned (Immediate) 1051def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">; 1052 1053// Shift Right And Insert (Immediate) 1054def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">; 1055// Shift Left And Insert (Immediate) 1056def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">; 1057 1058// Signed/Unsigned Saturating Shift Right Narrow (Immediate) 1059def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1060// Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) 1061def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1062// Signed Saturating Shift Right Unsigned Narrow (Immediate) 1063def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">; 1064// Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) 1065def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">; 1066 1067//////////////////////////////////////////////////////////////////////////////// 1068// Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate) 1069def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">; 1070def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">; 1071 1072//////////////////////////////////////////////////////////////////////////////// 1073// Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate) 1074def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">; 1075def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">; 1076def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">; 1077def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">; 1078} 1079 1080//////////////////////////////////////////////////////////////////////////////// 1081// Scalar Reduce Pairwise Addition (Scalar and Floating Point) 1082def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHd">; 1083 1084//////////////////////////////////////////////////////////////////////////////// 1085// Scalar Reduce Floating Point Pairwise Max/Min 1086def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">; 1087 1088def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">; 1089 1090//////////////////////////////////////////////////////////////////////////////// 1091// Scalar Reduce Floating Point Pairwise maxNum/minNum 1092def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">; 1093def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">; 1094 1095//////////////////////////////////////////////////////////////////////////////// 1096// Scalar Integer Saturating Doubling Multiply Half High 1097def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">; 1098 1099//////////////////////////////////////////////////////////////////////////////// 1100// Scalar Integer Saturating Rounding Doubling Multiply Half High 1101def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">; 1102 1103//////////////////////////////////////////////////////////////////////////////// 1104// Scalar Floating-point Multiply Extended 1105def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">; 1106 1107//////////////////////////////////////////////////////////////////////////////// 1108// Scalar Floating-point Reciprocal Step 1109def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">; 1110 1111//////////////////////////////////////////////////////////////////////////////// 1112// Scalar Floating-point Reciprocal Square Root Step 1113def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">; 1114 1115//////////////////////////////////////////////////////////////////////////////// 1116// Scalar Signed Integer Convert To Floating-point 1117def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">; 1118def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">; 1119 1120//////////////////////////////////////////////////////////////////////////////// 1121// Scalar Unsigned Integer Convert To Floating-point 1122def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">; 1123def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">; 1124 1125//////////////////////////////////////////////////////////////////////////////// 1126// Scalar Floating-point Reciprocal Estimate 1127def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">; 1128 1129//////////////////////////////////////////////////////////////////////////////// 1130// Scalar Floating-point Reciprocal Exponent 1131def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">; 1132 1133//////////////////////////////////////////////////////////////////////////////// 1134// Scalar Floating-point Reciprocal Square Root Estimate 1135def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">; 1136 1137//////////////////////////////////////////////////////////////////////////////// 1138// Scalar Integer Comparison 1139def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">; 1140def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">; 1141def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">; 1142def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">; 1143def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">; 1144def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">; 1145def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">; 1146def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">; 1147def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">; 1148def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">; 1149def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">; 1150def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">; 1151def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">; 1152 1153//////////////////////////////////////////////////////////////////////////////// 1154// Scalar Floating-point Comparison 1155def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">; 1156def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">; 1157def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">; 1158def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">; 1159def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">; 1160def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">; 1161def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">; 1162def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">; 1163def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">; 1164def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">; 1165 1166//////////////////////////////////////////////////////////////////////////////// 1167// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal 1168def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">; 1169def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">; 1170 1171//////////////////////////////////////////////////////////////////////////////// 1172// Scalar Floating-point Absolute Compare Mask Greater Than 1173def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">; 1174def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">; 1175 1176//////////////////////////////////////////////////////////////////////////////// 1177// Scalar Absolute Value 1178def SCALAR_ABS : SInst<"vabs", "ss", "Sl">; 1179 1180//////////////////////////////////////////////////////////////////////////////// 1181// Scalar Signed Saturating Absolute Value 1182def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">; 1183 1184//////////////////////////////////////////////////////////////////////////////// 1185// Scalar Negate 1186def SCALAR_NEG : SInst<"vneg", "ss", "Sl">; 1187 1188//////////////////////////////////////////////////////////////////////////////// 1189// Scalar Signed Saturating Negate 1190def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">; 1191 1192//////////////////////////////////////////////////////////////////////////////// 1193// Scalar Signed Saturating Accumulated of Unsigned Value 1194def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">; 1195 1196//////////////////////////////////////////////////////////////////////////////// 1197// Scalar Unsigned Saturating Accumulated of Signed Value 1198def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">; 1199 1200//////////////////////////////////////////////////////////////////////////////// 1201// Signed Saturating Doubling Multiply-Add Long 1202def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">; 1203 1204//////////////////////////////////////////////////////////////////////////////// 1205// Signed Saturating Doubling Multiply-Subtract Long 1206def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">; 1207 1208//////////////////////////////////////////////////////////////////////////////// 1209// Signed Saturating Doubling Multiply Long 1210def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">; 1211 1212//////////////////////////////////////////////////////////////////////////////// 1213// Scalar Signed Saturating Extract Unsigned Narrow 1214def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">; 1215 1216//////////////////////////////////////////////////////////////////////////////// 1217// Scalar Signed Saturating Extract Narrow 1218def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">; 1219 1220//////////////////////////////////////////////////////////////////////////////// 1221// Scalar Unsigned Saturating Extract Narrow 1222def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">; 1223 1224// Scalar Floating Point multiply (scalar, by element) 1225def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>; 1226def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LNQ>; 1227 1228// Scalar Floating Point multiply extended (scalar, by element) 1229def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>; 1230def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LNQ>; 1231 1232def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">; 1233 1234// VMUL_LANE_A64 d type implemented using scalar mul lane 1235def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">; 1236 1237// VMUL_LANEQ d type implemented using scalar mul lane 1238def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d">; 1239 1240// VMULX_LANE d type implemented using scalar vmulx_lane 1241def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>; 1242 1243// VMULX_LANEQ d type implemented using scalar vmulx_laneq 1244def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>; 1245 1246// Scalar Floating Point fused multiply-add (scalar, by element) 1247def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">; 1248def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">; 1249 1250// Scalar Floating Point fused multiply-subtract (scalar, by element) 1251def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>; 1252def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>; 1253 1254// Signed Saturating Doubling Multiply Long (scalar by element) 1255def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>; 1256def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LNQ>; 1257 1258// Signed Saturating Doubling Multiply-Add Long (scalar by element) 1259def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">; 1260def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">; 1261 1262// Signed Saturating Doubling Multiply-Subtract Long (scalar by element) 1263def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">; 1264def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">; 1265 1266// Scalar Integer Saturating Doubling Multiply Half High (scalar by element) 1267def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>; 1268def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LNQ>; 1269 1270// Scalar Integer Saturating Rounding Doubling Multiply Half High 1271def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>; 1272def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LNQ>; 1273 1274def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1275def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1276} 1277