1 //=- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-=====//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // This class implements a deterministic finite automaton (DFA) based
10 // packetizing mechanism for VLIW architectures. It provides APIs to
11 // determine whether there exists a legal mapping of instructions to
12 // functional unit assignments in a packet. The DFA is auto-generated from
13 // the target's Schedule.td file.
14 //
15 // A DFA consists of 3 major elements: states, inputs, and transitions. For
16 // the packetizing mechanism, the input is the set of instruction classes for
17 // a target. The state models all possible combinations of functional unit
18 // consumption for a given set of instructions in a packet. A transition
19 // models the addition of an instruction to a packet. In the DFA constructed
20 // by this class, if an instruction can be added to a packet, then a valid
21 // transition exists from the corresponding state. Invalid transitions
22 // indicate that the instruction cannot be added to the current packet.
23 //
24 //===----------------------------------------------------------------------===//
25 
26 #ifndef LLVM_CODEGEN_DFAPACKETIZER_H
27 #define LLVM_CODEGEN_DFAPACKETIZER_H
28 
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include <map>
32 
33 namespace llvm {
34 
35 class MCInstrDesc;
36 class MachineInstr;
37 class MachineLoopInfo;
38 class MachineDominatorTree;
39 class InstrItineraryData;
40 class DefaultVLIWScheduler;
41 class SUnit;
42 
43 class DFAPacketizer {
44 private:
45   typedef std::pair<unsigned, unsigned> UnsignPair;
46   const InstrItineraryData *InstrItins;
47   int CurrentState;
48   const int (*DFAStateInputTable)[2];
49   const unsigned *DFAStateEntryTable;
50 
51   // CachedTable is a map from <FromState, Input> to ToState.
52   DenseMap<UnsignPair, unsigned> CachedTable;
53 
54   // ReadTable - Read the DFA transition table and update CachedTable.
55   void ReadTable(unsigned int state);
56 
57 public:
58   DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
59                 const unsigned *SET);
60 
61   // Reset the current state to make all resources available.
clearResources()62   void clearResources() {
63     CurrentState = 0;
64   }
65 
66   // canReserveResources - Check if the resources occupied by a MCInstrDesc
67   // are available in the current state.
68   bool canReserveResources(const llvm::MCInstrDesc *MID);
69 
70   // reserveResources - Reserve the resources occupied by a MCInstrDesc and
71   // change the current state to reflect that change.
72   void reserveResources(const llvm::MCInstrDesc *MID);
73 
74   // canReserveResources - Check if the resources occupied by a machine
75   // instruction are available in the current state.
76   bool canReserveResources(llvm::MachineInstr *MI);
77 
78   // reserveResources - Reserve the resources occupied by a machine
79   // instruction and change the current state to reflect that change.
80   void reserveResources(llvm::MachineInstr *MI);
81 
getInstrItins()82   const InstrItineraryData *getInstrItins() const { return InstrItins; }
83 };
84 
85 // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The
86 // packetizer works on machine basic blocks. For each instruction I in BB, the
87 // packetizer consults the DFA to see if machine resources are available to
88 // execute I. If so, the packetizer checks if I depends on any instruction J in
89 // the current packet. If no dependency is found, I is added to current packet
90 // and machine resource is marked as taken. If any dependency is found, a target
91 // API call is made to prune the dependence.
92 class VLIWPacketizerList {
93 protected:
94   const MachineFunction &MF;
95   const TargetInstrInfo *TII;
96 
97   // The VLIW Scheduler.
98   DefaultVLIWScheduler *VLIWScheduler;
99 
100   // Vector of instructions assigned to the current packet.
101   std::vector<MachineInstr*> CurrentPacketMIs;
102   // DFA resource tracker.
103   DFAPacketizer *ResourceTracker;
104 
105   // Generate MI -> SU map.
106   std::map<MachineInstr*, SUnit*> MIToSUnit;
107 
108 public:
109   VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA);
110 
111   virtual ~VLIWPacketizerList();
112 
113   // PacketizeMIs - Implement this API in the backend to bundle instructions.
114   void PacketizeMIs(MachineBasicBlock *MBB,
115                     MachineBasicBlock::iterator BeginItr,
116                     MachineBasicBlock::iterator EndItr);
117 
118   // getResourceTracker - return ResourceTracker
getResourceTracker()119   DFAPacketizer *getResourceTracker() {return ResourceTracker;}
120 
121   // addToPacket - Add MI to the current packet.
addToPacket(MachineInstr * MI)122   virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
123     MachineBasicBlock::iterator MII = MI;
124     CurrentPacketMIs.push_back(MI);
125     ResourceTracker->reserveResources(MI);
126     return MII;
127   }
128 
129   // endPacket - End the current packet.
130   void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
131 
132   // initPacketizerState - perform initialization before packetizing
133   // an instruction. This function is supposed to be overrided by
134   // the target dependent packetizer.
initPacketizerState()135   virtual void initPacketizerState() { return; }
136 
137   // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
ignorePseudoInstruction(MachineInstr * I,MachineBasicBlock * MBB)138   virtual bool ignorePseudoInstruction(MachineInstr *I,
139                                        MachineBasicBlock *MBB) {
140     return false;
141   }
142 
143   // isSoloInstruction - return true if instruction MI can not be packetized
144   // with any other instruction, which means that MI itself is a packet.
isSoloInstruction(MachineInstr * MI)145   virtual bool isSoloInstruction(MachineInstr *MI) {
146     return true;
147   }
148 
149   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
150   // together.
isLegalToPacketizeTogether(SUnit * SUI,SUnit * SUJ)151   virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
152     return false;
153   }
154 
155   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
156   // and SUJ.
isLegalToPruneDependencies(SUnit * SUI,SUnit * SUJ)157   virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
158     return false;
159   }
160 
161 };
162 }
163 
164 #endif
165