1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the declaration of the MachineInstr class, which is the 11 // basic representation for all target dependent machine instructions used by 12 // the back end. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H 17 #define LLVM_CODEGEN_MACHINEINSTR_H 18 19 #include "llvm/ADT/ArrayRef.h" 20 #include "llvm/ADT/DenseMapInfo.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/StringRef.h" 23 #include "llvm/ADT/ilist.h" 24 #include "llvm/ADT/ilist_node.h" 25 #include "llvm/ADT/iterator_range.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/IR/DebugInfo.h" 28 #include "llvm/IR/DebugLoc.h" 29 #include "llvm/IR/InlineAsm.h" 30 #include "llvm/MC/MCInstrDesc.h" 31 #include "llvm/Support/ArrayRecycler.h" 32 #include "llvm/Target/TargetOpcodes.h" 33 34 namespace llvm { 35 36 template <typename T> class SmallVectorImpl; 37 class AliasAnalysis; 38 class TargetInstrInfo; 39 class TargetRegisterClass; 40 class TargetRegisterInfo; 41 class MachineFunction; 42 class MachineMemOperand; 43 44 //===----------------------------------------------------------------------===// 45 /// MachineInstr - Representation of each machine instruction. 46 /// 47 /// This class isn't a POD type, but it must have a trivial destructor. When a 48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated 49 /// without having their destructor called. 50 /// 51 class MachineInstr : public ilist_node<MachineInstr> { 52 public: 53 typedef MachineMemOperand **mmo_iterator; 54 55 /// Flags to specify different kinds of comments to output in 56 /// assembly code. These flags carry semantic information not 57 /// otherwise easily derivable from the IR text. 58 /// 59 enum CommentFlag { 60 ReloadReuse = 0x1 61 }; 62 63 enum MIFlag { 64 NoFlags = 0, 65 FrameSetup = 1 << 0, // Instruction is used as a part of 66 // function frame setup code. 67 BundledPred = 1 << 1, // Instruction has bundled predecessors. 68 BundledSucc = 1 << 2 // Instruction has bundled successors. 69 }; 70 private: 71 const MCInstrDesc *MCID; // Instruction descriptor. 72 MachineBasicBlock *Parent; // Pointer to the owning basic block. 73 74 // Operands are allocated by an ArrayRecycler. 75 MachineOperand *Operands; // Pointer to the first operand. 76 unsigned NumOperands; // Number of operands on instruction. 77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity; 78 OperandCapacity CapOperands; // Capacity of the Operands array. 79 80 uint8_t Flags; // Various bits of additional 81 // information about machine 82 // instruction. 83 84 uint8_t AsmPrinterFlags; // Various bits of information used by 85 // the AsmPrinter to emit helpful 86 // comments. This is *not* semantic 87 // information. Do not use this for 88 // anything other than to convey comment 89 // information to AsmPrinter. 90 91 uint8_t NumMemRefs; // Information on memory references. 92 mmo_iterator MemRefs; 93 94 DebugLoc debugLoc; // Source line information. 95 96 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION; 97 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION; 98 // Use MachineFunction::DeleteMachineInstr() instead. 99 ~MachineInstr() LLVM_DELETED_FUNCTION; 100 101 // Intrusive list support 102 friend struct ilist_traits<MachineInstr>; 103 friend struct ilist_traits<MachineBasicBlock>; 104 void setParent(MachineBasicBlock *P) { Parent = P; } 105 106 /// MachineInstr ctor - This constructor creates a copy of the given 107 /// MachineInstr in the given MachineFunction. 108 MachineInstr(MachineFunction &, const MachineInstr &); 109 110 /// MachineInstr ctor - This constructor create a MachineInstr and add the 111 /// implicit operands. It reserves space for number of operands specified by 112 /// MCInstrDesc. An explicit DebugLoc is supplied. 113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID, 114 const DebugLoc dl, bool NoImp = false); 115 116 // MachineInstrs are pool-allocated and owned by MachineFunction. 117 friend class MachineFunction; 118 119 public: 120 const MachineBasicBlock* getParent() const { return Parent; } 121 MachineBasicBlock* getParent() { return Parent; } 122 123 /// getAsmPrinterFlags - Return the asm printer flags bitvector. 124 /// 125 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } 126 127 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector 128 /// 129 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } 130 131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set. 132 /// 133 bool getAsmPrinterFlag(CommentFlag Flag) const { 134 return AsmPrinterFlags & Flag; 135 } 136 137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter. 138 /// 139 void setAsmPrinterFlag(CommentFlag Flag) { 140 AsmPrinterFlags |= (uint8_t)Flag; 141 } 142 143 /// clearAsmPrinterFlag - clear specific AsmPrinter flags 144 /// 145 void clearAsmPrinterFlag(CommentFlag Flag) { 146 AsmPrinterFlags &= ~Flag; 147 } 148 149 /// getFlags - Return the MI flags bitvector. 150 uint8_t getFlags() const { 151 return Flags; 152 } 153 154 /// getFlag - Return whether an MI flag is set. 155 bool getFlag(MIFlag Flag) const { 156 return Flags & Flag; 157 } 158 159 /// setFlag - Set a MI flag. 160 void setFlag(MIFlag Flag) { 161 Flags |= (uint8_t)Flag; 162 } 163 164 void setFlags(unsigned flags) { 165 // Filter out the automatically maintained flags. 166 unsigned Mask = BundledPred | BundledSucc; 167 Flags = (Flags & Mask) | (flags & ~Mask); 168 } 169 170 /// clearFlag - Clear a MI flag. 171 void clearFlag(MIFlag Flag) { 172 Flags &= ~((uint8_t)Flag); 173 } 174 175 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI 176 /// in a bundle). 177 /// 178 /// A bundle looks like this before it's finalized: 179 /// ---------------- 180 /// | MI | 181 /// ---------------- 182 /// | 183 /// ---------------- 184 /// | MI * | 185 /// ---------------- 186 /// | 187 /// ---------------- 188 /// | MI * | 189 /// ---------------- 190 /// In this case, the first MI starts a bundle but is not inside a bundle, the 191 /// next 2 MIs are considered "inside" the bundle. 192 /// 193 /// After a bundle is finalized, it looks like this: 194 /// ---------------- 195 /// | Bundle | 196 /// ---------------- 197 /// | 198 /// ---------------- 199 /// | MI * | 200 /// ---------------- 201 /// | 202 /// ---------------- 203 /// | MI * | 204 /// ---------------- 205 /// | 206 /// ---------------- 207 /// | MI * | 208 /// ---------------- 209 /// The first instruction has the special opcode "BUNDLE". It's not "inside" 210 /// a bundle, but the next three MIs are. 211 bool isInsideBundle() const { 212 return getFlag(BundledPred); 213 } 214 215 /// isBundled - Return true if this instruction part of a bundle. This is true 216 /// if either itself or its following instruction is marked "InsideBundle". 217 bool isBundled() const { 218 return isBundledWithPred() || isBundledWithSucc(); 219 } 220 221 /// Return true if this instruction is part of a bundle, and it is not the 222 /// first instruction in the bundle. 223 bool isBundledWithPred() const { return getFlag(BundledPred); } 224 225 /// Return true if this instruction is part of a bundle, and it is not the 226 /// last instruction in the bundle. 227 bool isBundledWithSucc() const { return getFlag(BundledSucc); } 228 229 /// Bundle this instruction with its predecessor. This can be an unbundled 230 /// instruction, or it can be the first instruction in a bundle. 231 void bundleWithPred(); 232 233 /// Bundle this instruction with its successor. This can be an unbundled 234 /// instruction, or it can be the last instruction in a bundle. 235 void bundleWithSucc(); 236 237 /// Break bundle above this instruction. 238 void unbundleFromPred(); 239 240 /// Break bundle below this instruction. 241 void unbundleFromSucc(); 242 243 /// getDebugLoc - Returns the debug location id of this MachineInstr. 244 /// 245 DebugLoc getDebugLoc() const { return debugLoc; } 246 247 /// \brief Return the debug variable referenced by 248 /// this DBG_VALUE instruction. 249 DIVariable getDebugVariable() const { 250 assert(isDebugValue() && "not a DBG_VALUE"); 251 DIVariable Var(getOperand(2).getMetadata()); 252 assert(Var.Verify() && "not a DIVariable"); 253 return Var; 254 } 255 256 /// \brief Return the complex address expression referenced by 257 /// this DBG_VALUE instruction. 258 DIExpression getDebugExpression() const { 259 assert(isDebugValue() && "not a DBG_VALUE"); 260 DIExpression Expr(getOperand(3).getMetadata()); 261 assert(Expr.Verify() && "not a DIExpression"); 262 return Expr; 263 } 264 265 /// emitError - Emit an error referring to the source location of this 266 /// instruction. This should only be used for inline assembly that is somehow 267 /// impossible to compile. Other errors should have been handled much 268 /// earlier. 269 /// 270 /// If this method returns, the caller should try to recover from the error. 271 /// 272 void emitError(StringRef Msg) const; 273 274 /// getDesc - Returns the target instruction descriptor of this 275 /// MachineInstr. 276 const MCInstrDesc &getDesc() const { return *MCID; } 277 278 /// getOpcode - Returns the opcode of this MachineInstr. 279 /// 280 int getOpcode() const { return MCID->Opcode; } 281 282 /// Access to explicit operands of the instruction. 283 /// 284 unsigned getNumOperands() const { return NumOperands; } 285 286 const MachineOperand& getOperand(unsigned i) const { 287 assert(i < getNumOperands() && "getOperand() out of range!"); 288 return Operands[i]; 289 } 290 MachineOperand& getOperand(unsigned i) { 291 assert(i < getNumOperands() && "getOperand() out of range!"); 292 return Operands[i]; 293 } 294 295 /// getNumExplicitOperands - Returns the number of non-implicit operands. 296 /// 297 unsigned getNumExplicitOperands() const; 298 299 /// iterator/begin/end - Iterate over all operands of a machine instruction. 300 typedef MachineOperand *mop_iterator; 301 typedef const MachineOperand *const_mop_iterator; 302 303 mop_iterator operands_begin() { return Operands; } 304 mop_iterator operands_end() { return Operands + NumOperands; } 305 306 const_mop_iterator operands_begin() const { return Operands; } 307 const_mop_iterator operands_end() const { return Operands + NumOperands; } 308 309 iterator_range<mop_iterator> operands() { 310 return iterator_range<mop_iterator>(operands_begin(), operands_end()); 311 } 312 iterator_range<const_mop_iterator> operands() const { 313 return iterator_range<const_mop_iterator>(operands_begin(), operands_end()); 314 } 315 iterator_range<mop_iterator> explicit_operands() { 316 return iterator_range<mop_iterator>( 317 operands_begin(), operands_begin() + getNumExplicitOperands()); 318 } 319 iterator_range<const_mop_iterator> explicit_operands() const { 320 return iterator_range<const_mop_iterator>( 321 operands_begin(), operands_begin() + getNumExplicitOperands()); 322 } 323 iterator_range<mop_iterator> implicit_operands() { 324 return iterator_range<mop_iterator>(explicit_operands().end(), 325 operands_end()); 326 } 327 iterator_range<const_mop_iterator> implicit_operands() const { 328 return iterator_range<const_mop_iterator>(explicit_operands().end(), 329 operands_end()); 330 } 331 iterator_range<mop_iterator> defs() { 332 return iterator_range<mop_iterator>( 333 operands_begin(), operands_begin() + getDesc().getNumDefs()); 334 } 335 iterator_range<const_mop_iterator> defs() const { 336 return iterator_range<const_mop_iterator>( 337 operands_begin(), operands_begin() + getDesc().getNumDefs()); 338 } 339 iterator_range<mop_iterator> uses() { 340 return iterator_range<mop_iterator>( 341 operands_begin() + getDesc().getNumDefs(), operands_end()); 342 } 343 iterator_range<const_mop_iterator> uses() const { 344 return iterator_range<const_mop_iterator>( 345 operands_begin() + getDesc().getNumDefs(), operands_end()); 346 } 347 348 /// Access to memory operands of the instruction 349 mmo_iterator memoperands_begin() const { return MemRefs; } 350 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; } 351 bool memoperands_empty() const { return NumMemRefs == 0; } 352 353 iterator_range<mmo_iterator> memoperands() { 354 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end()); 355 } 356 iterator_range<mmo_iterator> memoperands() const { 357 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end()); 358 } 359 360 /// hasOneMemOperand - Return true if this instruction has exactly one 361 /// MachineMemOperand. 362 bool hasOneMemOperand() const { 363 return NumMemRefs == 1; 364 } 365 366 /// API for querying MachineInstr properties. They are the same as MCInstrDesc 367 /// queries but they are bundle aware. 368 369 enum QueryType { 370 IgnoreBundle, // Ignore bundles 371 AnyInBundle, // Return true if any instruction in bundle has property 372 AllInBundle // Return true if all instructions in bundle have property 373 }; 374 375 /// hasProperty - Return true if the instruction (or in the case of a bundle, 376 /// the instructions inside the bundle) has the specified property. 377 /// The first argument is the property being queried. 378 /// The second argument indicates whether the query should look inside 379 /// instruction bundles. 380 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { 381 // Inline the fast path for unbundled or bundle-internal instructions. 382 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) 383 return getDesc().getFlags() & (1 << MCFlag); 384 385 // If this is the first instruction in a bundle, take the slow path. 386 return hasPropertyInBundle(1 << MCFlag, Type); 387 } 388 389 /// isVariadic - Return true if this instruction can have a variable number of 390 /// operands. In this case, the variable operands will be after the normal 391 /// operands but before the implicit definitions and uses (if any are 392 /// present). 393 bool isVariadic(QueryType Type = IgnoreBundle) const { 394 return hasProperty(MCID::Variadic, Type); 395 } 396 397 /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 398 /// ARM instructions which can set condition code if 's' bit is set. 399 bool hasOptionalDef(QueryType Type = IgnoreBundle) const { 400 return hasProperty(MCID::HasOptionalDef, Type); 401 } 402 403 /// isPseudo - Return true if this is a pseudo instruction that doesn't 404 /// correspond to a real machine instruction. 405 /// 406 bool isPseudo(QueryType Type = IgnoreBundle) const { 407 return hasProperty(MCID::Pseudo, Type); 408 } 409 410 bool isReturn(QueryType Type = AnyInBundle) const { 411 return hasProperty(MCID::Return, Type); 412 } 413 414 bool isCall(QueryType Type = AnyInBundle) const { 415 return hasProperty(MCID::Call, Type); 416 } 417 418 /// isBarrier - Returns true if the specified instruction stops control flow 419 /// from executing the instruction immediately following it. Examples include 420 /// unconditional branches and return instructions. 421 bool isBarrier(QueryType Type = AnyInBundle) const { 422 return hasProperty(MCID::Barrier, Type); 423 } 424 425 /// isTerminator - Returns true if this instruction part of the terminator for 426 /// a basic block. Typically this is things like return and branch 427 /// instructions. 428 /// 429 /// Various passes use this to insert code into the bottom of a basic block, 430 /// but before control flow occurs. 431 bool isTerminator(QueryType Type = AnyInBundle) const { 432 return hasProperty(MCID::Terminator, Type); 433 } 434 435 /// isBranch - Returns true if this is a conditional, unconditional, or 436 /// indirect branch. Predicates below can be used to discriminate between 437 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 438 /// get more information. 439 bool isBranch(QueryType Type = AnyInBundle) const { 440 return hasProperty(MCID::Branch, Type); 441 } 442 443 /// isIndirectBranch - Return true if this is an indirect branch, such as a 444 /// branch through a register. 445 bool isIndirectBranch(QueryType Type = AnyInBundle) const { 446 return hasProperty(MCID::IndirectBranch, Type); 447 } 448 449 /// isConditionalBranch - Return true if this is a branch which may fall 450 /// through to the next instruction or may transfer control flow to some other 451 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 452 /// information about this branch. 453 bool isConditionalBranch(QueryType Type = AnyInBundle) const { 454 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type); 455 } 456 457 /// isUnconditionalBranch - Return true if this is a branch which always 458 /// transfers control flow to some other block. The 459 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 460 /// about this branch. 461 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { 462 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type); 463 } 464 465 /// Return true if this instruction has a predicate operand that 466 /// controls execution. It may be set to 'always', or may be set to other 467 /// values. There are various methods in TargetInstrInfo that can be used to 468 /// control and modify the predicate in this instruction. 469 bool isPredicable(QueryType Type = AllInBundle) const { 470 // If it's a bundle than all bundled instructions must be predicable for this 471 // to return true. 472 return hasProperty(MCID::Predicable, Type); 473 } 474 475 /// isCompare - Return true if this instruction is a comparison. 476 bool isCompare(QueryType Type = IgnoreBundle) const { 477 return hasProperty(MCID::Compare, Type); 478 } 479 480 /// isMoveImmediate - Return true if this instruction is a move immediate 481 /// (including conditional moves) instruction. 482 bool isMoveImmediate(QueryType Type = IgnoreBundle) const { 483 return hasProperty(MCID::MoveImm, Type); 484 } 485 486 /// isBitcast - Return true if this instruction is a bitcast instruction. 487 /// 488 bool isBitcast(QueryType Type = IgnoreBundle) const { 489 return hasProperty(MCID::Bitcast, Type); 490 } 491 492 /// isSelect - Return true if this instruction is a select instruction. 493 /// 494 bool isSelect(QueryType Type = IgnoreBundle) const { 495 return hasProperty(MCID::Select, Type); 496 } 497 498 /// isNotDuplicable - Return true if this instruction cannot be safely 499 /// duplicated. For example, if the instruction has a unique labels attached 500 /// to it, duplicating it would cause multiple definition errors. 501 bool isNotDuplicable(QueryType Type = AnyInBundle) const { 502 return hasProperty(MCID::NotDuplicable, Type); 503 } 504 505 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 506 /// which must be filled by the code generator. 507 bool hasDelaySlot(QueryType Type = AnyInBundle) const { 508 return hasProperty(MCID::DelaySlot, Type); 509 } 510 511 /// canFoldAsLoad - Return true for instructions that can be folded as 512 /// memory operands in other instructions. The most common use for this 513 /// is instructions that are simple loads from memory that don't modify 514 /// the loaded value in any way, but it can also be used for instructions 515 /// that can be expressed as constant-pool loads, such as V_SETALLONES 516 /// on x86, to allow them to be folded when it is beneficial. 517 /// This should only be set on instructions that return a value in their 518 /// only virtual register definition. 519 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { 520 return hasProperty(MCID::FoldableAsLoad, Type); 521 } 522 523 /// \brief Return true if this instruction behaves 524 /// the same way as the generic REG_SEQUENCE instructions. 525 /// E.g., on ARM, 526 /// dX VMOVDRR rY, rZ 527 /// is equivalent to 528 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 529 /// 530 /// Note that for the optimizers to be able to take advantage of 531 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 532 /// override accordingly. 533 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { 534 return hasProperty(MCID::RegSequence, Type); 535 } 536 537 /// \brief Return true if this instruction behaves 538 /// the same way as the generic EXTRACT_SUBREG instructions. 539 /// E.g., on ARM, 540 /// rX, rY VMOVRRD dZ 541 /// is equivalent to two EXTRACT_SUBREG: 542 /// rX = EXTRACT_SUBREG dZ, ssub_0 543 /// rY = EXTRACT_SUBREG dZ, ssub_1 544 /// 545 /// Note that for the optimizers to be able to take advantage of 546 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 547 /// override accordingly. 548 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const { 549 return hasProperty(MCID::ExtractSubreg, Type); 550 } 551 552 /// \brief Return true if this instruction behaves 553 /// the same way as the generic INSERT_SUBREG instructions. 554 /// E.g., on ARM, 555 /// dX = VSETLNi32 dY, rZ, Imm 556 /// is equivalent to a INSERT_SUBREG: 557 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 558 /// 559 /// Note that for the optimizers to be able to take advantage of 560 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 561 /// override accordingly. 562 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { 563 return hasProperty(MCID::InsertSubreg, Type); 564 } 565 566 //===--------------------------------------------------------------------===// 567 // Side Effect Analysis 568 //===--------------------------------------------------------------------===// 569 570 /// mayLoad - Return true if this instruction could possibly read memory. 571 /// Instructions with this flag set are not necessarily simple load 572 /// instructions, they may load a value and modify it, for example. 573 bool mayLoad(QueryType Type = AnyInBundle) const { 574 if (isInlineAsm()) { 575 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 576 if (ExtraInfo & InlineAsm::Extra_MayLoad) 577 return true; 578 } 579 return hasProperty(MCID::MayLoad, Type); 580 } 581 582 583 /// mayStore - Return true if this instruction could possibly modify memory. 584 /// Instructions with this flag set are not necessarily simple store 585 /// instructions, they may store a modified value based on their operands, or 586 /// may not actually modify anything, for example. 587 bool mayStore(QueryType Type = AnyInBundle) const { 588 if (isInlineAsm()) { 589 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 590 if (ExtraInfo & InlineAsm::Extra_MayStore) 591 return true; 592 } 593 return hasProperty(MCID::MayStore, Type); 594 } 595 596 //===--------------------------------------------------------------------===// 597 // Flags that indicate whether an instruction can be modified by a method. 598 //===--------------------------------------------------------------------===// 599 600 /// isCommutable - Return true if this may be a 2- or 3-address 601 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 602 /// result if Y and Z are exchanged. If this flag is set, then the 603 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 604 /// instruction. 605 /// 606 /// Note that this flag may be set on instructions that are only commutable 607 /// sometimes. In these cases, the call to commuteInstruction will fail. 608 /// Also note that some instructions require non-trivial modification to 609 /// commute them. 610 bool isCommutable(QueryType Type = IgnoreBundle) const { 611 return hasProperty(MCID::Commutable, Type); 612 } 613 614 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 615 /// which can be changed into a 3-address instruction if needed. Doing this 616 /// transformation can be profitable in the register allocator, because it 617 /// means that the instruction can use a 2-address form if possible, but 618 /// degrade into a less efficient form if the source and dest register cannot 619 /// be assigned to the same register. For example, this allows the x86 620 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 621 /// is the same speed as the shift but has bigger code size. 622 /// 623 /// If this returns true, then the target must implement the 624 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 625 /// is allowed to fail if the transformation isn't valid for this specific 626 /// instruction (e.g. shl reg, 4 on x86). 627 /// 628 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { 629 return hasProperty(MCID::ConvertibleTo3Addr, Type); 630 } 631 632 /// usesCustomInsertionHook - Return true if this instruction requires 633 /// custom insertion support when the DAG scheduler is inserting it into a 634 /// machine basic block. If this is true for the instruction, it basically 635 /// means that it is a pseudo instruction used at SelectionDAG time that is 636 /// expanded out into magic code by the target when MachineInstrs are formed. 637 /// 638 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 639 /// is used to insert this into the MachineBasicBlock. 640 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { 641 return hasProperty(MCID::UsesCustomInserter, Type); 642 } 643 644 /// hasPostISelHook - Return true if this instruction requires *adjustment* 645 /// after instruction selection by calling a target hook. For example, this 646 /// can be used to fill in ARM 's' optional operand depending on whether 647 /// the conditional flag register is used. 648 bool hasPostISelHook(QueryType Type = IgnoreBundle) const { 649 return hasProperty(MCID::HasPostISelHook, Type); 650 } 651 652 /// isRematerializable - Returns true if this instruction is a candidate for 653 /// remat. This flag is deprecated, please don't use it anymore. If this 654 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 655 /// verify the instruction is really rematable. 656 bool isRematerializable(QueryType Type = AllInBundle) const { 657 // It's only possible to re-mat a bundle if all bundled instructions are 658 // re-materializable. 659 return hasProperty(MCID::Rematerializable, Type); 660 } 661 662 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 663 /// less) than a move instruction. This is useful during certain types of 664 /// optimizations (e.g., remat during two-address conversion or machine licm) 665 /// where we would like to remat or hoist the instruction, but not if it costs 666 /// more than moving the instruction into the appropriate register. Note, we 667 /// are not marking copies from and to the same register class with this flag. 668 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { 669 // Only returns true for a bundle if all bundled instructions are cheap. 670 return hasProperty(MCID::CheapAsAMove, Type); 671 } 672 673 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 674 /// have special register allocation requirements that are not captured by the 675 /// operand register classes. e.g. ARM::STRD's two source registers must be an 676 /// even / odd pair, ARM::STM registers have to be in ascending order. 677 /// Post-register allocation passes should not attempt to change allocations 678 /// for sources of instructions with this flag. 679 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const { 680 return hasProperty(MCID::ExtraSrcRegAllocReq, Type); 681 } 682 683 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 684 /// have special register allocation requirements that are not captured by the 685 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 686 /// even / odd pair, ARM::LDM registers have to be in ascending order. 687 /// Post-register allocation passes should not attempt to change allocations 688 /// for definitions of instructions with this flag. 689 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const { 690 return hasProperty(MCID::ExtraDefRegAllocReq, Type); 691 } 692 693 694 enum MICheckType { 695 CheckDefs, // Check all operands for equality 696 CheckKillDead, // Check all operands including kill / dead markers 697 IgnoreDefs, // Ignore all definitions 698 IgnoreVRegDefs // Ignore virtual register definitions 699 }; 700 701 /// isIdenticalTo - Return true if this instruction is identical to (same 702 /// opcode and same operands as) the specified instruction. 703 bool isIdenticalTo(const MachineInstr *Other, 704 MICheckType Check = CheckDefs) const; 705 706 /// Unlink 'this' from the containing basic block, and return it without 707 /// deleting it. 708 /// 709 /// This function can not be used on bundled instructions, use 710 /// removeFromBundle() to remove individual instructions from a bundle. 711 MachineInstr *removeFromParent(); 712 713 /// Unlink this instruction from its basic block and return it without 714 /// deleting it. 715 /// 716 /// If the instruction is part of a bundle, the other instructions in the 717 /// bundle remain bundled. 718 MachineInstr *removeFromBundle(); 719 720 /// Unlink 'this' from the containing basic block and delete it. 721 /// 722 /// If this instruction is the header of a bundle, the whole bundle is erased. 723 /// This function can not be used for instructions inside a bundle, use 724 /// eraseFromBundle() to erase individual bundled instructions. 725 void eraseFromParent(); 726 727 /// Unlink 'this' from the containing basic block and delete it. 728 /// 729 /// For all definitions mark their uses in DBG_VALUE nodes 730 /// as undefined. Otherwise like eraseFromParent(). 731 void eraseFromParentAndMarkDBGValuesForRemoval(); 732 733 /// Unlink 'this' form its basic block and delete it. 734 /// 735 /// If the instruction is part of a bundle, the other instructions in the 736 /// bundle remain bundled. 737 void eraseFromBundle(); 738 739 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 740 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 741 742 /// isLabel - Returns true if the MachineInstr represents a label. 743 /// 744 bool isLabel() const { return isEHLabel() || isGCLabel(); } 745 bool isCFIInstruction() const { 746 return getOpcode() == TargetOpcode::CFI_INSTRUCTION; 747 } 748 749 // True if the instruction represents a position in the function. 750 bool isPosition() const { return isLabel() || isCFIInstruction(); } 751 752 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 753 /// A DBG_VALUE is indirect iff the first operand is a register and 754 /// the second operand is an immediate. 755 bool isIndirectDebugValue() const { 756 return isDebugValue() 757 && getOperand(0).isReg() 758 && getOperand(1).isImm(); 759 } 760 761 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } 762 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 763 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 764 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } 765 bool isMSInlineAsm() const { 766 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect(); 767 } 768 bool isStackAligningInlineAsm() const; 769 InlineAsm::AsmDialect getInlineAsmDialect() const; 770 bool isInsertSubreg() const { 771 return getOpcode() == TargetOpcode::INSERT_SUBREG; 772 } 773 bool isSubregToReg() const { 774 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 775 } 776 bool isRegSequence() const { 777 return getOpcode() == TargetOpcode::REG_SEQUENCE; 778 } 779 bool isBundle() const { 780 return getOpcode() == TargetOpcode::BUNDLE; 781 } 782 bool isCopy() const { 783 return getOpcode() == TargetOpcode::COPY; 784 } 785 bool isFullCopy() const { 786 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 787 } 788 bool isExtractSubreg() const { 789 return getOpcode() == TargetOpcode::EXTRACT_SUBREG; 790 } 791 792 /// isCopyLike - Return true if the instruction behaves like a copy. 793 /// This does not include native copy instructions. 794 bool isCopyLike() const { 795 return isCopy() || isSubregToReg(); 796 } 797 798 /// isIdentityCopy - Return true is the instruction is an identity copy. 799 bool isIdentityCopy() const { 800 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && 801 getOperand(0).getSubReg() == getOperand(1).getSubReg(); 802 } 803 804 /// isTransient - Return true if this is a transient instruction that is 805 /// either very likely to be eliminated during register allocation (such as 806 /// copy-like instructions), or if this instruction doesn't have an 807 /// execution-time cost. 808 bool isTransient() const { 809 switch(getOpcode()) { 810 default: return false; 811 // Copy-like instructions are usually eliminated during register allocation. 812 case TargetOpcode::PHI: 813 case TargetOpcode::COPY: 814 case TargetOpcode::INSERT_SUBREG: 815 case TargetOpcode::SUBREG_TO_REG: 816 case TargetOpcode::REG_SEQUENCE: 817 // Pseudo-instructions that don't produce any real output. 818 case TargetOpcode::IMPLICIT_DEF: 819 case TargetOpcode::KILL: 820 case TargetOpcode::CFI_INSTRUCTION: 821 case TargetOpcode::EH_LABEL: 822 case TargetOpcode::GC_LABEL: 823 case TargetOpcode::DBG_VALUE: 824 return true; 825 } 826 } 827 828 /// Return the number of instructions inside the MI bundle, excluding the 829 /// bundle header. 830 /// 831 /// This is the number of instructions that MachineBasicBlock::iterator 832 /// skips, 0 for unbundled instructions. 833 unsigned getBundleSize() const; 834 835 /// readsRegister - Return true if the MachineInstr reads the specified 836 /// register. If TargetRegisterInfo is passed, then it also checks if there 837 /// is a read of a super-register. 838 /// This does not count partial redefines of virtual registers as reads: 839 /// %reg1024:6 = OP. 840 bool readsRegister(unsigned Reg, 841 const TargetRegisterInfo *TRI = nullptr) const { 842 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 843 } 844 845 /// readsVirtualRegister - Return true if the MachineInstr reads the specified 846 /// virtual register. Take into account that a partial define is a 847 /// read-modify-write operation. 848 bool readsVirtualRegister(unsigned Reg) const { 849 return readsWritesVirtualRegister(Reg).first; 850 } 851 852 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 853 /// indicating if this instruction reads or writes Reg. This also considers 854 /// partial defines. 855 /// If Ops is not null, all operand indices for Reg are added. 856 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg, 857 SmallVectorImpl<unsigned> *Ops = nullptr) const; 858 859 /// killsRegister - Return true if the MachineInstr kills the specified 860 /// register. If TargetRegisterInfo is passed, then it also checks if there is 861 /// a kill of a super-register. 862 bool killsRegister(unsigned Reg, 863 const TargetRegisterInfo *TRI = nullptr) const { 864 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 865 } 866 867 /// definesRegister - Return true if the MachineInstr fully defines the 868 /// specified register. If TargetRegisterInfo is passed, then it also checks 869 /// if there is a def of a super-register. 870 /// NOTE: It's ignoring subreg indices on virtual registers. 871 bool definesRegister(unsigned Reg, 872 const TargetRegisterInfo *TRI = nullptr) const { 873 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 874 } 875 876 /// modifiesRegister - Return true if the MachineInstr modifies (fully define 877 /// or partially define) the specified register. 878 /// NOTE: It's ignoring subreg indices on virtual registers. 879 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const { 880 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 881 } 882 883 /// registerDefIsDead - Returns true if the register is dead in this machine 884 /// instruction. If TargetRegisterInfo is passed, then it also checks 885 /// if there is a dead def of a super-register. 886 bool registerDefIsDead(unsigned Reg, 887 const TargetRegisterInfo *TRI = nullptr) const { 888 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; 889 } 890 891 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of 892 /// the specific register or -1 if it is not found. It further tightens 893 /// the search criteria to a use that kills the register if isKill is true. 894 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 895 const TargetRegisterInfo *TRI = nullptr) const; 896 897 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns 898 /// a pointer to the MachineOperand rather than an index. 899 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, 900 const TargetRegisterInfo *TRI = nullptr) { 901 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 902 return (Idx == -1) ? nullptr : &getOperand(Idx); 903 } 904 905 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of 906 /// the specified register or -1 if it is not found. If isDead is true, defs 907 /// that are not dead are skipped. If Overlap is true, then it also looks for 908 /// defs that merely overlap the specified register. If TargetRegisterInfo is 909 /// non-null, then it also checks if there is a def of a super-register. 910 /// This may also return a register mask operand when Overlap is true. 911 int findRegisterDefOperandIdx(unsigned Reg, 912 bool isDead = false, bool Overlap = false, 913 const TargetRegisterInfo *TRI = nullptr) const; 914 915 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns 916 /// a pointer to the MachineOperand rather than an index. 917 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, 918 const TargetRegisterInfo *TRI = nullptr) { 919 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI); 920 return (Idx == -1) ? nullptr : &getOperand(Idx); 921 } 922 923 /// findFirstPredOperandIdx() - Find the index of the first operand in the 924 /// operand list that is used to represent the predicate. It returns -1 if 925 /// none is found. 926 int findFirstPredOperandIdx() const; 927 928 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that 929 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if 930 /// getOperand(OpIdx) does not belong to an inline asm operand group. 931 /// 932 /// If GroupNo is not NULL, it will receive the number of the operand group 933 /// containing OpIdx. 934 /// 935 /// The flag operand is an immediate that can be decoded with methods like 936 /// InlineAsm::hasRegClassConstraint(). 937 /// 938 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; 939 940 /// getRegClassConstraint - Compute the static register class constraint for 941 /// operand OpIdx. For normal instructions, this is derived from the 942 /// MCInstrDesc. For inline assembly it is derived from the flag words. 943 /// 944 /// Returns NULL if the static register classs constraint cannot be 945 /// determined. 946 /// 947 const TargetRegisterClass* 948 getRegClassConstraint(unsigned OpIdx, 949 const TargetInstrInfo *TII, 950 const TargetRegisterInfo *TRI) const; 951 952 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to 953 /// the given \p CurRC. 954 /// If \p ExploreBundle is set and MI is part of a bundle, all the 955 /// instructions inside the bundle will be taken into account. In other words, 956 /// this method accumulates all the constrains of the operand of this MI and 957 /// the related bundle if MI is a bundle or inside a bundle. 958 /// 959 /// Returns the register class that statisfies both \p CurRC and the 960 /// constraints set by MI. Returns NULL if such a register class does not 961 /// exist. 962 /// 963 /// \pre CurRC must not be NULL. 964 const TargetRegisterClass *getRegClassConstraintEffectForVReg( 965 unsigned Reg, const TargetRegisterClass *CurRC, 966 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, 967 bool ExploreBundle = false) const; 968 969 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand 970 /// to the given \p CurRC. 971 /// 972 /// Returns the register class that statisfies both \p CurRC and the 973 /// constraints set by \p OpIdx MI. Returns NULL if such a register class 974 /// does not exist. 975 /// 976 /// \pre CurRC must not be NULL. 977 /// \pre The operand at \p OpIdx must be a register. 978 const TargetRegisterClass * 979 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, 980 const TargetInstrInfo *TII, 981 const TargetRegisterInfo *TRI) const; 982 983 /// tieOperands - Add a tie between the register operands at DefIdx and 984 /// UseIdx. The tie will cause the register allocator to ensure that the two 985 /// operands are assigned the same physical register. 986 /// 987 /// Tied operands are managed automatically for explicit operands in the 988 /// MCInstrDesc. This method is for exceptional cases like inline asm. 989 void tieOperands(unsigned DefIdx, unsigned UseIdx); 990 991 /// findTiedOperandIdx - Given the index of a tied register operand, find the 992 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the 993 /// index of the tied operand which must exist. 994 unsigned findTiedOperandIdx(unsigned OpIdx) const; 995 996 /// isRegTiedToUseOperand - Given the index of a register def operand, 997 /// check if the register def is tied to a source operand, due to either 998 /// two-address elimination or inline assembly constraints. Returns the 999 /// first tied use operand index by reference if UseOpIdx is not null. 1000 bool isRegTiedToUseOperand(unsigned DefOpIdx, 1001 unsigned *UseOpIdx = nullptr) const { 1002 const MachineOperand &MO = getOperand(DefOpIdx); 1003 if (!MO.isReg() || !MO.isDef() || !MO.isTied()) 1004 return false; 1005 if (UseOpIdx) 1006 *UseOpIdx = findTiedOperandIdx(DefOpIdx); 1007 return true; 1008 } 1009 1010 /// isRegTiedToDefOperand - Return true if the use operand of the specified 1011 /// index is tied to a def operand. It also returns the def operand index by 1012 /// reference if DefOpIdx is not null. 1013 bool isRegTiedToDefOperand(unsigned UseOpIdx, 1014 unsigned *DefOpIdx = nullptr) const { 1015 const MachineOperand &MO = getOperand(UseOpIdx); 1016 if (!MO.isReg() || !MO.isUse() || !MO.isTied()) 1017 return false; 1018 if (DefOpIdx) 1019 *DefOpIdx = findTiedOperandIdx(UseOpIdx); 1020 return true; 1021 } 1022 1023 /// clearKillInfo - Clears kill flags on all operands. 1024 /// 1025 void clearKillInfo(); 1026 1027 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx, 1028 /// properly composing subreg indices where necessary. 1029 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, 1030 const TargetRegisterInfo &RegInfo); 1031 1032 /// addRegisterKilled - We have determined MI kills a register. Look for the 1033 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 1034 /// add a implicit operand if it's not found. Returns true if the operand 1035 /// exists / is added. 1036 bool addRegisterKilled(unsigned IncomingReg, 1037 const TargetRegisterInfo *RegInfo, 1038 bool AddIfNotFound = false); 1039 1040 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is 1041 /// provided, this includes super-register kills. 1042 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo); 1043 1044 /// addRegisterDead - We have determined MI defined a register without a use. 1045 /// Look for the operand that defines it and mark it as IsDead. If 1046 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 1047 /// true if the operand exists / is added. 1048 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, 1049 bool AddIfNotFound = false); 1050 1051 /// addRegisterDefined - We have determined MI defines a register. Make sure 1052 /// there is an operand defining Reg. 1053 void addRegisterDefined(unsigned Reg, 1054 const TargetRegisterInfo *RegInfo = nullptr); 1055 1056 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as 1057 /// dead except those in the UsedRegs list. 1058 /// 1059 /// On instructions with register mask operands, also add implicit-def 1060 /// operands for all registers in UsedRegs. 1061 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1062 const TargetRegisterInfo &TRI); 1063 1064 /// isSafeToMove - Return true if it is safe to move this instruction. If 1065 /// SawStore is set to true, it means that there is a store (or call) between 1066 /// the instruction's location and its intended destination. 1067 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA, 1068 bool &SawStore) const; 1069 1070 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered 1071 /// or volatile memory reference, or if the information describing the memory 1072 /// reference is not available. Return false if it is known to have no 1073 /// ordered or volatile memory references. 1074 bool hasOrderedMemoryRef() const; 1075 1076 /// isInvariantLoad - Return true if this instruction is loading from a 1077 /// location whose value is invariant across the function. For example, 1078 /// loading a value from the constant pool or from the argument area of 1079 /// a function if it does not change. This should only return true of *all* 1080 /// loads the instruction does are invariant (if it does multiple loads). 1081 bool isInvariantLoad(AliasAnalysis *AA) const; 1082 1083 /// isConstantValuePHI - If the specified instruction is a PHI that always 1084 /// merges together the same virtual register, return the register, otherwise 1085 /// return 0. 1086 unsigned isConstantValuePHI() const; 1087 1088 /// hasUnmodeledSideEffects - Return true if this instruction has side 1089 /// effects that are not modeled by mayLoad / mayStore, etc. 1090 /// For all instructions, the property is encoded in MCInstrDesc::Flags 1091 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is 1092 /// INLINEASM instruction, in which case the side effect property is encoded 1093 /// in one of its operands (see InlineAsm::Extra_HasSideEffect). 1094 /// 1095 bool hasUnmodeledSideEffects() const; 1096 1097 /// allDefsAreDead - Return true if all the defs of this instruction are dead. 1098 /// 1099 bool allDefsAreDead() const; 1100 1101 /// copyImplicitOps - Copy implicit register operands from specified 1102 /// instruction to this instruction. 1103 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI); 1104 1105 // 1106 // Debugging support 1107 // 1108 void print(raw_ostream &OS, const TargetMachine *TM = nullptr, 1109 bool SkipOpers = false) const; 1110 void dump() const; 1111 1112 //===--------------------------------------------------------------------===// 1113 // Accessors used to build up machine instructions. 1114 1115 /// Add the specified operand to the instruction. If it is an implicit 1116 /// operand, it is added to the end of the operand list. If it is an 1117 /// explicit operand it is added at the end of the explicit operand list 1118 /// (before the first implicit operand). 1119 /// 1120 /// MF must be the machine function that was used to allocate this 1121 /// instruction. 1122 /// 1123 /// MachineInstrBuilder provides a more convenient interface for creating 1124 /// instructions and adding operands. 1125 void addOperand(MachineFunction &MF, const MachineOperand &Op); 1126 1127 /// Add an operand without providing an MF reference. This only works for 1128 /// instructions that are inserted in a basic block. 1129 /// 1130 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be 1131 /// preferred. 1132 void addOperand(const MachineOperand &Op); 1133 1134 /// setDesc - Replace the instruction descriptor (thus opcode) of 1135 /// the current instruction with a new one. 1136 /// 1137 void setDesc(const MCInstrDesc &tid) { MCID = &tid; } 1138 1139 /// setDebugLoc - Replace current source information with new such. 1140 /// Avoid using this, the constructor argument is preferable. 1141 /// 1142 void setDebugLoc(const DebugLoc dl) { 1143 debugLoc = dl; 1144 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); 1145 } 1146 1147 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 1148 /// fewer operand than it started with. 1149 /// 1150 void RemoveOperand(unsigned i); 1151 1152 /// addMemOperand - Add a MachineMemOperand to the machine instruction. 1153 /// This function should be used only occasionally. The setMemRefs function 1154 /// is the primary method for setting up a MachineInstr's MemRefs list. 1155 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 1156 1157 /// setMemRefs - Assign this MachineInstr's memory reference descriptor 1158 /// list. This does not transfer ownership. 1159 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) { 1160 MemRefs = NewMemRefs; 1161 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs); 1162 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs"); 1163 } 1164 1165 private: 1166 /// getRegInfo - If this instruction is embedded into a MachineFunction, 1167 /// return the MachineRegisterInfo object for the current function, otherwise 1168 /// return null. 1169 MachineRegisterInfo *getRegInfo(); 1170 1171 /// untieRegOperand - Break any tie involving OpIdx. 1172 void untieRegOperand(unsigned OpIdx) { 1173 MachineOperand &MO = getOperand(OpIdx); 1174 if (MO.isReg() && MO.isTied()) { 1175 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0; 1176 MO.TiedTo = 0; 1177 } 1178 } 1179 1180 /// addImplicitDefUseOperands - Add all implicit def and use operands to 1181 /// this instruction. 1182 void addImplicitDefUseOperands(MachineFunction &MF); 1183 1184 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 1185 /// this instruction from their respective use lists. This requires that the 1186 /// operands already be on their use lists. 1187 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); 1188 1189 /// AddRegOperandsToUseLists - Add all of the register operands in 1190 /// this instruction from their respective use lists. This requires that the 1191 /// operands not be on their use lists yet. 1192 void AddRegOperandsToUseLists(MachineRegisterInfo&); 1193 1194 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a 1195 /// bundle. 1196 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const; 1197 1198 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the 1199 /// this MI and the given operand index \p OpIdx. 1200 /// If the related operand does not constrained Reg, this returns CurRC. 1201 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( 1202 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, 1203 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; 1204 }; 1205 1206 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare 1207 /// MachineInstr* by *value* of the instruction rather than by pointer value. 1208 /// The hashing and equality testing functions ignore definitions so this is 1209 /// useful for CSE, etc. 1210 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { 1211 static inline MachineInstr *getEmptyKey() { 1212 return nullptr; 1213 } 1214 1215 static inline MachineInstr *getTombstoneKey() { 1216 return reinterpret_cast<MachineInstr*>(-1); 1217 } 1218 1219 static unsigned getHashValue(const MachineInstr* const &MI); 1220 1221 static bool isEqual(const MachineInstr* const &LHS, 1222 const MachineInstr* const &RHS) { 1223 if (RHS == getEmptyKey() || RHS == getTombstoneKey() || 1224 LHS == getEmptyKey() || LHS == getTombstoneKey()) 1225 return LHS == RHS; 1226 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs); 1227 } 1228 }; 1229 1230 //===----------------------------------------------------------------------===// 1231 // Debugging Support 1232 1233 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 1234 MI.print(OS); 1235 return OS; 1236 } 1237 1238 } // End llvm namespace 1239 1240 #endif 1241