1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines interfaces to access the target independent code generation 11 // passes provided by the LLVM backend. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_PASSES_H 16 #define LLVM_CODEGEN_PASSES_H 17 18 #include "llvm/Pass.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include <string> 21 22 namespace llvm { 23 24 class FunctionPass; 25 class MachineFunctionPass; 26 class PassConfigImpl; 27 class PassInfo; 28 class ScheduleDAGInstrs; 29 class TargetLowering; 30 class TargetLoweringBase; 31 class TargetRegisterClass; 32 class raw_ostream; 33 struct MachineSchedContext; 34 35 // The old pass manager infrastructure is hidden in a legacy namespace now. 36 namespace legacy { 37 class PassManagerBase; 38 } 39 using legacy::PassManagerBase; 40 41 /// Discriminated union of Pass ID types. 42 /// 43 /// The PassConfig API prefers dealing with IDs because they are safer and more 44 /// efficient. IDs decouple configuration from instantiation. This way, when a 45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to 46 /// refer to a Pass pointer after adding it to a pass manager, which deletes 47 /// redundant pass instances. 48 /// 49 /// However, it is convient to directly instantiate target passes with 50 /// non-default ctors. These often don't have a registered PassInfo. Rather than 51 /// force all target passes to implement the pass registry boilerplate, allow 52 /// the PassConfig API to handle either type. 53 /// 54 /// AnalysisID is sadly char*, so PointerIntPair won't work. 55 class IdentifyingPassPtr { 56 union { 57 AnalysisID ID; 58 Pass *P; 59 }; 60 bool IsInstance; 61 public: IdentifyingPassPtr()62 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {} IdentifyingPassPtr(AnalysisID IDPtr)63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {} IdentifyingPassPtr(Pass * InstancePtr)64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {} 65 isValid()66 bool isValid() const { return P; } isInstance()67 bool isInstance() const { return IsInstance; } 68 getID()69 AnalysisID getID() const { 70 assert(!IsInstance && "Not a Pass ID"); 71 return ID; 72 } getInstance()73 Pass *getInstance() const { 74 assert(IsInstance && "Not a Pass Instance"); 75 return P; 76 } 77 }; 78 79 template <> struct isPodLike<IdentifyingPassPtr> { 80 static const bool value = true; 81 }; 82 83 /// Target-Independent Code Generator Pass Configuration Options. 84 /// 85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options 86 /// to the internals of other CodeGen passes. 87 class TargetPassConfig : public ImmutablePass { 88 public: 89 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they 90 /// are unregistered pass IDs. They are only useful for use with 91 /// TargetPassConfig APIs to identify multiple occurrences of the same pass. 92 /// 93 94 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early 95 /// during codegen, on SSA form. 96 static char EarlyTailDuplicateID; 97 98 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine 99 /// optimization after regalloc. 100 static char PostRAMachineLICMID; 101 102 private: 103 PassManagerBase *PM; 104 AnalysisID StartAfter; 105 AnalysisID StopAfter; 106 bool Started; 107 bool Stopped; 108 bool AddingMachinePasses; 109 110 protected: 111 TargetMachine *TM; 112 PassConfigImpl *Impl; // Internal data structures 113 bool Initialized; // Flagged after all passes are configured. 114 115 // Target Pass Options 116 // Targets provide a default setting, user flags override. 117 // 118 bool DisableVerify; 119 120 /// Default setting for -enable-tail-merge on this target. 121 bool EnableTailMerge; 122 123 public: 124 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); 125 // Dummy constructor. 126 TargetPassConfig(); 127 128 virtual ~TargetPassConfig(); 129 130 static char ID; 131 132 /// Get the right type of TargetMachine for this target. 133 template<typename TMC> TMC &getTM() const { 134 return *static_cast<TMC*>(TM); 135 } 136 137 // 138 void setInitialized() { Initialized = true; } 139 140 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } 141 142 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow 143 /// running only a portion of the normal code-gen pass sequence. If the 144 /// Start pass ID is zero, then compilation will begin at the normal point; 145 /// otherwise, clear the Started flag to indicate that passes should not be 146 /// added until the starting pass is seen. If the Stop pass ID is zero, 147 /// then compilation will continue to the end. 148 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) { 149 StartAfter = Start; 150 StopAfter = Stop; 151 Started = (StartAfter == nullptr); 152 } 153 154 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 155 156 bool getEnableTailMerge() const { return EnableTailMerge; } 157 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 158 159 /// Allow the target to override a specific pass without overriding the pass 160 /// pipeline. When passes are added to the standard pipeline at the 161 /// point where StandardID is expected, add TargetID in its place. 162 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID); 163 164 /// Insert InsertedPassID pass after TargetPassID pass. 165 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID); 166 167 /// Allow the target to enable a specific standard pass by default. 168 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } 169 170 /// Allow the target to disable a specific standard pass by default. 171 void disablePass(AnalysisID PassID) { 172 substitutePass(PassID, IdentifyingPassPtr()); 173 } 174 175 /// Return the pass substituted for StandardID by the target. 176 /// If no substitution exists, return StandardID. 177 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const; 178 179 /// Return true if the optimized regalloc pipeline is enabled. 180 bool getOptimizeRegAlloc() const; 181 182 /// Return true if the default global register allocator is in use and 183 /// has not be overriden on the command line with '-regalloc=...' 184 bool usingDefaultRegAlloc() const; 185 186 /// Add common target configurable passes that perform LLVM IR to IR 187 /// transforms following machine independent optimization. 188 virtual void addIRPasses(); 189 190 /// Add passes to lower exception handling for the code generator. 191 void addPassesToHandleExceptions(); 192 193 /// Add pass to prepare the LLVM IR for code generation. This should be done 194 /// before exception handling preparation passes. 195 virtual void addCodeGenPrepare(); 196 197 /// Add common passes that perform LLVM IR to IR transforms in preparation for 198 /// instruction selection. 199 virtual void addISelPrepare(); 200 201 /// addInstSelector - This method should install an instruction selector pass, 202 /// which converts from LLVM code to machine instructions. 203 virtual bool addInstSelector() { 204 return true; 205 } 206 207 /// Add the complete, standard set of LLVM CodeGen passes. 208 /// Fully developed targets will not generally override this. 209 virtual void addMachinePasses(); 210 211 /// Create an instance of ScheduleDAGInstrs to be run within the standard 212 /// MachineScheduler pass for this function and target at the current 213 /// optimization level. 214 /// 215 /// This can also be used to plug a new MachineSchedStrategy into an instance 216 /// of the standard ScheduleDAGMI: 217 /// return new ScheduleDAGMI(C, new MyStrategy(C)) 218 /// 219 /// Return NULL to select the default (generic) machine scheduler. 220 virtual ScheduleDAGInstrs * 221 createMachineScheduler(MachineSchedContext *C) const { 222 return nullptr; 223 } 224 225 /// Similar to createMachineScheduler but used when postRA machine scheduling 226 /// is enabled. 227 virtual ScheduleDAGInstrs * 228 createPostMachineScheduler(MachineSchedContext *C) const { 229 return nullptr; 230 } 231 232 protected: 233 // Helper to verify the analysis is really immutable. 234 void setOpt(bool &Opt, bool Val); 235 236 /// Methods with trivial inline returns are convenient points in the common 237 /// codegen pass pipeline where targets may insert passes. Methods with 238 /// out-of-line standard implementations are major CodeGen stages called by 239 /// addMachinePasses. Some targets may override major stages when inserting 240 /// passes is insufficient, but maintaining overriden stages is more work. 241 /// 242 243 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 244 /// passes (which are run just before instruction selector). 245 virtual bool addPreISel() { 246 return true; 247 } 248 249 /// addMachineSSAOptimization - Add standard passes that optimize machine 250 /// instructions in SSA form. 251 virtual void addMachineSSAOptimization(); 252 253 /// Add passes that optimize instruction level parallelism for out-of-order 254 /// targets. These passes are run while the machine code is still in SSA 255 /// form, so they can use MachineTraceMetrics to control their heuristics. 256 /// 257 /// All passes added here should preserve the MachineDominatorTree, 258 /// MachineLoopInfo, and MachineTraceMetrics analyses. 259 virtual bool addILPOpts() { 260 return false; 261 } 262 263 /// This method may be implemented by targets that want to run passes 264 /// immediately before register allocation. 265 virtual void addPreRegAlloc() { } 266 267 /// createTargetRegisterAllocator - Create the register allocator pass for 268 /// this target at the current optimization level. 269 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 270 271 /// addFastRegAlloc - Add the minimum set of target-independent passes that 272 /// are required for fast register allocation. 273 virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 274 275 /// addOptimizedRegAlloc - Add passes related to register allocation. 276 /// LLVMTargetMachine provides standard regalloc passes for most targets. 277 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 278 279 /// addPreRewrite - Add passes to the optimized register allocation pipeline 280 /// after register allocation is complete, but before virtual registers are 281 /// rewritten to physical registers. 282 /// 283 /// These passes must preserve VirtRegMap and LiveIntervals, and when running 284 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 285 /// When these passes run, VirtRegMap contains legal physreg assignments for 286 /// all virtual registers. 287 virtual bool addPreRewrite() { 288 return false; 289 } 290 291 /// This method may be implemented by targets that want to run passes after 292 /// register allocation pass pipeline but before prolog-epilog insertion. 293 virtual void addPostRegAlloc() { } 294 295 /// Add passes that optimize machine instructions after register allocation. 296 virtual void addMachineLateOptimization(); 297 298 /// This method may be implemented by targets that want to run passes after 299 /// prolog-epilog insertion and before the second instruction scheduling pass. 300 virtual void addPreSched2() { } 301 302 /// addGCPasses - Add late codegen passes that analyze code for garbage 303 /// collection. This should return true if GC info should be printed after 304 /// these passes. 305 virtual bool addGCPasses(); 306 307 /// Add standard basic block placement passes. 308 virtual void addBlockPlacement(); 309 310 /// This pass may be implemented by targets that want to run passes 311 /// immediately before machine code is emitted. 312 virtual void addPreEmitPass() { } 313 314 /// Utilities for targets to add passes to the pass manager. 315 /// 316 317 /// Add a CodeGen pass at this point in the pipeline after checking overrides. 318 /// Return the pass that was added, or zero if no pass was added. 319 /// @p printAfter if true and adding a machine function pass add an extra 320 /// machine printer pass afterwards 321 /// @p verifyAfter if true and adding a machine function pass add an extra 322 /// machine verification pass afterwards. 323 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true, 324 bool printAfter = true); 325 326 /// Add a pass to the PassManager if that pass is supposed to be run, as 327 /// determined by the StartAfter and StopAfter options. Takes ownership of the 328 /// pass. 329 /// @p printAfter if true and adding a machine function pass add an extra 330 /// machine printer pass afterwards 331 /// @p verifyAfter if true and adding a machine function pass add an extra 332 /// machine verification pass afterwards. 333 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true); 334 335 /// addMachinePasses helper to create the target-selected or overriden 336 /// regalloc pass. 337 FunctionPass *createRegAllocPass(bool Optimized); 338 339 /// printAndVerify - Add a pass to dump then verify the machine function, if 340 /// those steps are enabled. 341 /// 342 void printAndVerify(const std::string &Banner); 343 344 /// Add a pass to print the machine function if printing is enabled. 345 void addPrintPass(const std::string &Banner); 346 347 /// Add a pass to perform basic verification of the machine function if 348 /// verification is enabled. 349 void addVerifyPass(const std::string &Banner); 350 }; 351 } // namespace llvm 352 353 /// List of target independent CodeGen pass IDs. 354 namespace llvm { 355 FunctionPass *createAtomicExpandPass(const TargetMachine *TM); 356 357 /// \brief Create a basic TargetTransformInfo analysis pass. 358 /// 359 /// This pass implements the target transform info analysis using the target 360 /// independent information available to the LLVM code generator. 361 ImmutablePass * 362 createBasicTargetTransformInfoPass(const TargetMachine *TM); 363 364 /// createUnreachableBlockEliminationPass - The LLVM code generator does not 365 /// work well with unreachable basic blocks (what live ranges make sense for a 366 /// block that cannot be reached?). As such, a code generator should either 367 /// not instruction select unreachable blocks, or run this pass as its 368 /// last LLVM modifying pass to clean up blocks that are not reachable from 369 /// the entry block. 370 FunctionPass *createUnreachableBlockEliminationPass(); 371 372 /// MachineFunctionPrinter pass - This pass prints out the machine function to 373 /// the given stream as a debugging tool. 374 MachineFunctionPass * 375 createMachineFunctionPrinterPass(raw_ostream &OS, 376 const std::string &Banner =""); 377 378 /// createCodeGenPreparePass - Transform the code to expose more pattern 379 /// matching during instruction selection. 380 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr); 381 382 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg 383 /// load-linked/store-conditional loops. 384 extern char &AtomicExpandID; 385 386 /// MachineLoopInfo - This pass is a loop analysis pass. 387 extern char &MachineLoopInfoID; 388 389 /// MachineDominators - This pass is a machine dominators analysis pass. 390 extern char &MachineDominatorsID; 391 392 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass. 393 extern char &MachineDominanceFrontierID; 394 395 /// EdgeBundles analysis - Bundle machine CFG edges. 396 extern char &EdgeBundlesID; 397 398 /// LiveVariables pass - This pass computes the set of blocks in which each 399 /// variable is life and sets machine operand kill flags. 400 extern char &LiveVariablesID; 401 402 /// PHIElimination - This pass eliminates machine instruction PHI nodes 403 /// by inserting copy instructions. This destroys SSA information, but is the 404 /// desired input for some register allocators. This pass is "required" by 405 /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 406 extern char &PHIEliminationID; 407 408 /// LiveIntervals - This analysis keeps track of the live ranges of virtual 409 /// and physical registers. 410 extern char &LiveIntervalsID; 411 412 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 413 extern char &LiveStacksID; 414 415 /// TwoAddressInstruction - This pass reduces two-address instructions to 416 /// use two operands. This destroys SSA information but it is desired by 417 /// register allocators. 418 extern char &TwoAddressInstructionPassID; 419 420 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 421 extern char &ProcessImplicitDefsID; 422 423 /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 424 extern char &RegisterCoalescerID; 425 426 /// MachineScheduler - This pass schedules machine instructions. 427 extern char &MachineSchedulerID; 428 429 /// PostMachineScheduler - This pass schedules machine instructions postRA. 430 extern char &PostMachineSchedulerID; 431 432 /// SpillPlacement analysis. Suggest optimal placement of spill code between 433 /// basic blocks. 434 extern char &SpillPlacementID; 435 436 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 437 /// assigned in VirtRegMap. 438 extern char &VirtRegRewriterID; 439 440 /// UnreachableMachineBlockElimination - This pass removes unreachable 441 /// machine basic blocks. 442 extern char &UnreachableMachineBlockElimID; 443 444 /// DeadMachineInstructionElim - This pass removes dead machine instructions. 445 extern char &DeadMachineInstructionElimID; 446 447 /// FastRegisterAllocation Pass - This pass register allocates as fast as 448 /// possible. It is best suited for debug code where live ranges are short. 449 /// 450 FunctionPass *createFastRegisterAllocator(); 451 452 /// BasicRegisterAllocation Pass - This pass implements a degenerate global 453 /// register allocator using the basic regalloc framework. 454 /// 455 FunctionPass *createBasicRegisterAllocator(); 456 457 /// Greedy register allocation pass - This pass implements a global register 458 /// allocator for optimized builds. 459 /// 460 FunctionPass *createGreedyRegisterAllocator(); 461 462 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 463 /// Quadratic Prograaming (PBQP) based register allocator. 464 /// 465 FunctionPass *createDefaultPBQPRegisterAllocator(); 466 467 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 468 /// and eliminates abstract frame references. 469 extern char &PrologEpilogCodeInserterID; 470 471 /// ExpandPostRAPseudos - This pass expands pseudo instructions after 472 /// register allocation. 473 extern char &ExpandPostRAPseudosID; 474 475 /// createPostRAScheduler - This pass performs post register allocation 476 /// scheduling. 477 extern char &PostRASchedulerID; 478 479 /// BranchFolding - This pass performs machine code CFG based 480 /// optimizations to delete branches to branches, eliminate branches to 481 /// successor blocks (creating fall throughs), and eliminating branches over 482 /// branches. 483 extern char &BranchFolderPassID; 484 485 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 486 extern char &MachineFunctionPrinterPassID; 487 488 /// TailDuplicate - Duplicate blocks with unconditional branches 489 /// into tails of their predecessors. 490 extern char &TailDuplicateID; 491 492 /// MachineTraceMetrics - This pass computes critical path and CPU resource 493 /// usage in an ensemble of traces. 494 extern char &MachineTraceMetricsID; 495 496 /// EarlyIfConverter - This pass performs if-conversion on SSA form by 497 /// inserting cmov instructions. 498 extern char &EarlyIfConverterID; 499 500 /// This pass performs instruction combining using trace metrics to estimate 501 /// critical-path and resource depth. 502 extern char &MachineCombinerID; 503 504 /// StackSlotColoring - This pass performs stack coloring and merging. 505 /// It merges disjoint allocas to reduce the stack size. 506 extern char &StackColoringID; 507 508 /// IfConverter - This pass performs machine code if conversion. 509 extern char &IfConverterID; 510 511 /// MachineBlockPlacement - This pass places basic blocks based on branch 512 /// probabilities. 513 extern char &MachineBlockPlacementID; 514 515 /// MachineBlockPlacementStats - This pass collects statistics about the 516 /// basic block placement using branch probabilities and block frequency 517 /// information. 518 extern char &MachineBlockPlacementStatsID; 519 520 /// GCLowering Pass - Performs target-independent LLVM IR transformations for 521 /// highly portable strategies. 522 /// 523 FunctionPass *createGCLoweringPass(); 524 525 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 526 /// in machine code. Must be added very late during code generation, just 527 /// prior to output, and importantly after all CFG transformations (such as 528 /// branch folding). 529 extern char &GCMachineCodeAnalysisID; 530 531 /// Creates a pass to print GC metadata. 532 /// 533 FunctionPass *createGCInfoPrinter(raw_ostream &OS); 534 535 /// MachineCSE - This pass performs global CSE on machine instructions. 536 extern char &MachineCSEID; 537 538 /// MachineLICM - This pass performs LICM on machine instructions. 539 extern char &MachineLICMID; 540 541 /// MachineSinking - This pass performs sinking on machine instructions. 542 extern char &MachineSinkingID; 543 544 /// MachineCopyPropagation - This pass performs copy propagation on 545 /// machine instructions. 546 extern char &MachineCopyPropagationID; 547 548 /// PeepholeOptimizer - This pass performs peephole optimizations - 549 /// like extension and comparison eliminations. 550 extern char &PeepholeOptimizerID; 551 552 /// OptimizePHIs - This pass optimizes machine instruction PHIs 553 /// to take advantage of opportunities created during DAG legalization. 554 extern char &OptimizePHIsID; 555 556 /// StackSlotColoring - This pass performs stack slot coloring. 557 extern char &StackSlotColoringID; 558 559 /// createStackProtectorPass - This pass adds stack protectors to functions. 560 /// 561 FunctionPass *createStackProtectorPass(const TargetMachine *TM); 562 563 /// createMachineVerifierPass - This pass verifies cenerated machine code 564 /// instructions for correctness. 565 /// 566 FunctionPass *createMachineVerifierPass(const std::string& Banner); 567 568 /// createDwarfEHPass - This pass mulches exception handling code into a form 569 /// adapted to code generation. Required if using dwarf exception handling. 570 FunctionPass *createDwarfEHPass(const TargetMachine *TM); 571 572 /// createSjLjEHPreparePass - This pass adapts exception handling code to use 573 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 574 /// 575 FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM); 576 577 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 578 /// slots relative to one another and allocates base registers to access them 579 /// when it is estimated by the target to be out of range of normal frame 580 /// pointer or stack pointer index addressing. 581 extern char &LocalStackSlotAllocationID; 582 583 /// ExpandISelPseudos - This pass expands pseudo-instructions. 584 extern char &ExpandISelPseudosID; 585 586 /// createExecutionDependencyFixPass - This pass fixes execution time 587 /// problems with dependent instructions, such as switching execution 588 /// domains to match. 589 /// 590 /// The pass will examine instructions using and defining registers in RC. 591 /// 592 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); 593 594 /// UnpackMachineBundles - This pass unpack machine instruction bundles. 595 extern char &UnpackMachineBundlesID; 596 597 /// FinalizeMachineBundles - This pass finalize machine instruction 598 /// bundles (created earlier, e.g. during pre-RA scheduling). 599 extern char &FinalizeMachineBundlesID; 600 601 /// StackMapLiveness - This pass analyses the register live-out set of 602 /// stackmap/patchpoint intrinsics and attaches the calculated information to 603 /// the intrinsic for later emission to the StackMap. 604 extern char &StackMapLivenessID; 605 606 /// createJumpInstrTables - This pass creates jump-instruction tables. 607 ModulePass *createJumpInstrTablesPass(); 608 609 /// createForwardControlFlowIntegrityPass - This pass adds control-flow 610 /// integrity. 611 ModulePass *createForwardControlFlowIntegrityPass(); 612 } // End llvm namespace 613 614 /// This initializer registers TargetMachine constructor, so the pass being 615 /// initialized can use target dependent interfaces. Please do not move this 616 /// macro to be together with INITIALIZE_PASS, which is a complete target 617 /// independent initializer, and we don't want to make libScalarOpts depend 618 /// on libCodeGen. 619 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \ 620 static void* initialize##passName##PassOnce(PassRegistry &Registry) { \ 621 PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \ 622 PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \ 623 PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \ 624 Registry.registerPass(*PI, true); \ 625 return PI; \ 626 } \ 627 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \ 628 CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \ 629 } 630 631 #endif 632