1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
17 // targets).
18 //
19 //===----------------------------------------------------------------------===//
20
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 using namespace llvm;
26
27 #define DEBUG_TYPE "legalize-types"
28
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
32
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
PromoteIntegerResult(SDNode * N,unsigned ResNo)37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
40
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 return;
44
45 switch (N->getOpcode()) {
46 default:
47 #ifndef NDEBUG
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
50 #endif
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
70 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
74 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
75 case ISD::SIGN_EXTEND_INREG:
76 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
77 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
78 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
79 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
80 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
81 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
82
83 case ISD::EXTRACT_SUBVECTOR:
84 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
85 case ISD::VECTOR_SHUFFLE:
86 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
87 case ISD::INSERT_VECTOR_ELT:
88 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
89 case ISD::BUILD_VECTOR:
90 Res = PromoteIntRes_BUILD_VECTOR(N); break;
91 case ISD::SCALAR_TO_VECTOR:
92 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
93 case ISD::CONCAT_VECTORS:
94 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
95
96 case ISD::SIGN_EXTEND:
97 case ISD::ZERO_EXTEND:
98 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
99
100 case ISD::FP_TO_SINT:
101 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
102
103 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
104
105 case ISD::AND:
106 case ISD::OR:
107 case ISD::XOR:
108 case ISD::ADD:
109 case ISD::SUB:
110 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
111
112 case ISD::SDIV:
113 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
114
115 case ISD::UDIV:
116 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
117
118 case ISD::SADDO:
119 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
120 case ISD::UADDO:
121 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
122 case ISD::SMULO:
123 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
124
125 case ISD::ATOMIC_LOAD:
126 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
127
128 case ISD::ATOMIC_LOAD_ADD:
129 case ISD::ATOMIC_LOAD_SUB:
130 case ISD::ATOMIC_LOAD_AND:
131 case ISD::ATOMIC_LOAD_OR:
132 case ISD::ATOMIC_LOAD_XOR:
133 case ISD::ATOMIC_LOAD_NAND:
134 case ISD::ATOMIC_LOAD_MIN:
135 case ISD::ATOMIC_LOAD_MAX:
136 case ISD::ATOMIC_LOAD_UMIN:
137 case ISD::ATOMIC_LOAD_UMAX:
138 case ISD::ATOMIC_SWAP:
139 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
140
141 case ISD::ATOMIC_CMP_SWAP:
142 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
143 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
144 break;
145 }
146
147 // If the result is null then the sub-method took care of registering it.
148 if (Res.getNode())
149 SetPromotedInteger(SDValue(N, ResNo), Res);
150 }
151
PromoteIntRes_MERGE_VALUES(SDNode * N,unsigned ResNo)152 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
153 unsigned ResNo) {
154 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
155 return GetPromotedInteger(Op);
156 }
157
PromoteIntRes_AssertSext(SDNode * N)158 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
159 // Sign-extend the new bits, and continue the assertion.
160 SDValue Op = SExtPromotedInteger(N->getOperand(0));
161 return DAG.getNode(ISD::AssertSext, SDLoc(N),
162 Op.getValueType(), Op, N->getOperand(1));
163 }
164
PromoteIntRes_AssertZext(SDNode * N)165 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
166 // Zero the new bits, and continue the assertion.
167 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
168 return DAG.getNode(ISD::AssertZext, SDLoc(N),
169 Op.getValueType(), Op, N->getOperand(1));
170 }
171
PromoteIntRes_Atomic0(AtomicSDNode * N)172 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
173 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
174 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
175 N->getMemoryVT(), ResVT,
176 N->getChain(), N->getBasePtr(),
177 N->getMemOperand(), N->getOrdering(),
178 N->getSynchScope());
179 // Legalized the chain result - switch anything that used the old chain to
180 // use the new one.
181 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
182 return Res;
183 }
184
PromoteIntRes_Atomic1(AtomicSDNode * N)185 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
186 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
187 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
188 N->getMemoryVT(),
189 N->getChain(), N->getBasePtr(),
190 Op2, N->getMemOperand(), N->getOrdering(),
191 N->getSynchScope());
192 // Legalized the chain result - switch anything that used the old chain to
193 // use the new one.
194 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
195 return Res;
196 }
197
PromoteIntRes_AtomicCmpSwap(AtomicSDNode * N,unsigned ResNo)198 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
199 unsigned ResNo) {
200 if (ResNo == 1) {
201 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
202 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
203 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
204
205 // Only use the result of getSetCCResultType if it is legal,
206 // otherwise just use the promoted result type (NVT).
207 if (!TLI.isTypeLegal(SVT))
208 SVT = NVT;
209
210 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
211 SDValue Res = DAG.getAtomicCmpSwap(
212 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
213 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
214 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
215 N->getSynchScope());
216 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
217 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
218 return Res.getValue(1);
219 }
220
221 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
222 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
223 SDVTList VTs =
224 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
225 SDValue Res = DAG.getAtomicCmpSwap(
226 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
227 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
228 N->getFailureOrdering(), N->getSynchScope());
229 // Update the use to N with the newly created Res.
230 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
231 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
232 return Res;
233 }
234
PromoteIntRes_BITCAST(SDNode * N)235 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
236 SDValue InOp = N->getOperand(0);
237 EVT InVT = InOp.getValueType();
238 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
239 EVT OutVT = N->getValueType(0);
240 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
241 SDLoc dl(N);
242
243 switch (getTypeAction(InVT)) {
244 case TargetLowering::TypeLegal:
245 break;
246 case TargetLowering::TypePromoteInteger:
247 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
248 // The input promotes to the same size. Convert the promoted value.
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
250 break;
251 case TargetLowering::TypeSoftenFloat:
252 // Promote the integer operand by hand.
253 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
254 case TargetLowering::TypeExpandInteger:
255 case TargetLowering::TypeExpandFloat:
256 break;
257 case TargetLowering::TypeScalarizeVector:
258 // Convert the element to an integer and promote it by hand.
259 if (!NOutVT.isVector())
260 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
261 BitConvertToInteger(GetScalarizedVector(InOp)));
262 break;
263 case TargetLowering::TypeSplitVector: {
264 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
265 // pieces of the input into integers and reassemble in the final type.
266 SDValue Lo, Hi;
267 GetSplitVector(N->getOperand(0), Lo, Hi);
268 Lo = BitConvertToInteger(Lo);
269 Hi = BitConvertToInteger(Hi);
270
271 if (TLI.isBigEndian())
272 std::swap(Lo, Hi);
273
274 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
275 EVT::getIntegerVT(*DAG.getContext(),
276 NOutVT.getSizeInBits()),
277 JoinIntegers(Lo, Hi));
278 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
279 }
280 case TargetLowering::TypeWidenVector:
281 // The input is widened to the same size. Convert to the widened value.
282 // Make sure that the outgoing value is not a vector, because this would
283 // make us bitcast between two vectors which are legalized in different ways.
284 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
285 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
286 }
287
288 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
289 CreateStackStoreLoad(InOp, OutVT));
290 }
291
PromoteIntRes_BSWAP(SDNode * N)292 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
293 SDValue Op = GetPromotedInteger(N->getOperand(0));
294 EVT OVT = N->getValueType(0);
295 EVT NVT = Op.getValueType();
296 SDLoc dl(N);
297
298 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
299 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
300 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
301 }
302
PromoteIntRes_BUILD_PAIR(SDNode * N)303 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
304 // The pair element type may be legal, or may not promote to the same type as
305 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
306 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
307 TLI.getTypeToTransformTo(*DAG.getContext(),
308 N->getValueType(0)), JoinIntegers(N->getOperand(0),
309 N->getOperand(1)));
310 }
311
PromoteIntRes_Constant(SDNode * N)312 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
313 EVT VT = N->getValueType(0);
314 // FIXME there is no actual debug info here
315 SDLoc dl(N);
316 // Zero extend things like i1, sign extend everything else. It shouldn't
317 // matter in theory which one we pick, but this tends to give better code?
318 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
319 SDValue Result = DAG.getNode(Opc, dl,
320 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
321 SDValue(N, 0));
322 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
323 return Result;
324 }
325
PromoteIntRes_CONVERT_RNDSAT(SDNode * N)326 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
327 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
328 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
329 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
330 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
331 "can only promote integers");
332 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
333 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
334 N->getOperand(1), N->getOperand(2),
335 N->getOperand(3), N->getOperand(4), CvtCode);
336 }
337
PromoteIntRes_CTLZ(SDNode * N)338 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
339 // Zero extend to the promoted type and do the count there.
340 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
341 SDLoc dl(N);
342 EVT OVT = N->getValueType(0);
343 EVT NVT = Op.getValueType();
344 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
345 // Subtract off the extra leading bits in the bigger type.
346 return DAG.getNode(
347 ISD::SUB, dl, NVT, Op,
348 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(),
349 NVT));
350 }
351
PromoteIntRes_CTPOP(SDNode * N)352 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
353 // Zero extend to the promoted type and do the count there.
354 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
355 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
356 }
357
PromoteIntRes_CTTZ(SDNode * N)358 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
359 SDValue Op = GetPromotedInteger(N->getOperand(0));
360 EVT OVT = N->getValueType(0);
361 EVT NVT = Op.getValueType();
362 SDLoc dl(N);
363 if (N->getOpcode() == ISD::CTTZ) {
364 // The count is the same in the promoted type except if the original
365 // value was zero. This can be handled by setting the bit just off
366 // the top of the original type.
367 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
368 OVT.getScalarSizeInBits());
369 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
370 }
371 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
372 }
373
PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode * N)374 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
375 SDLoc dl(N);
376 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
377 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
378 N->getOperand(1));
379 }
380
PromoteIntRes_FP_TO_XINT(SDNode * N)381 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
382 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
383 unsigned NewOpc = N->getOpcode();
384 SDLoc dl(N);
385
386 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
387 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
388 // and SINT conversions are Custom, there is no way to tell which is
389 // preferable. We choose SINT because that's the right thing on PPC.)
390 if (N->getOpcode() == ISD::FP_TO_UINT &&
391 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
392 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
393 NewOpc = ISD::FP_TO_SINT;
394
395 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
396
397 // Assert that the converted value fits in the original type. If it doesn't
398 // (eg: because the value being converted is too big), then the result of the
399 // original operation was undefined anyway, so the assert is still correct.
400 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
401 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
402 DAG.getValueType(N->getValueType(0).getScalarType()));
403 }
404
PromoteIntRes_FP_TO_FP16(SDNode * N)405 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
406 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
407 SDLoc dl(N);
408
409 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
410
411 return DAG.getNode(ISD::AssertZext, dl,
412 NVT, Res, DAG.getValueType(N->getValueType(0)));
413 }
414
PromoteIntRes_INT_EXTEND(SDNode * N)415 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
416 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
417 SDLoc dl(N);
418
419 if (getTypeAction(N->getOperand(0).getValueType())
420 == TargetLowering::TypePromoteInteger) {
421 SDValue Res = GetPromotedInteger(N->getOperand(0));
422 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
423
424 // If the result and operand types are the same after promotion, simplify
425 // to an in-register extension.
426 if (NVT == Res.getValueType()) {
427 // The high bits are not guaranteed to be anything. Insert an extend.
428 if (N->getOpcode() == ISD::SIGN_EXTEND)
429 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
430 DAG.getValueType(N->getOperand(0).getValueType()));
431 if (N->getOpcode() == ISD::ZERO_EXTEND)
432 return DAG.getZeroExtendInReg(Res, dl,
433 N->getOperand(0).getValueType().getScalarType());
434 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
435 return Res;
436 }
437 }
438
439 // Otherwise, just extend the original operand all the way to the larger type.
440 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
441 }
442
PromoteIntRes_LOAD(LoadSDNode * N)443 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
444 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
445 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
446 ISD::LoadExtType ExtType =
447 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
448 SDLoc dl(N);
449 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
450 N->getMemoryVT(), N->getMemOperand());
451
452 // Legalized the chain result - switch anything that used the old chain to
453 // use the new one.
454 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
455 return Res;
456 }
457
PromoteIntRes_MLOAD(MaskedLoadSDNode * N)458 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
459 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
460 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
461
462 SDValue Mask = N->getMask();
463 EVT NewMaskVT = getSetCCResultType(NVT);
464 if (NewMaskVT != N->getMask().getValueType())
465 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
466 SDLoc dl(N);
467
468 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
469 Mask, ExtSrc0, N->getMemoryVT(),
470 N->getMemOperand(), ISD::SEXTLOAD);
471 // Legalized the chain result - switch anything that used the old chain to
472 // use the new one.
473 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
474 return Res;
475 }
476 /// Promote the overflow flag of an overflowing arithmetic node.
PromoteIntRes_Overflow(SDNode * N)477 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
478 // Simply change the return type of the boolean result.
479 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
480 EVT ValueVTs[] = { N->getValueType(0), NVT };
481 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
482 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
483 DAG.getVTList(ValueVTs), Ops);
484
485 // Modified the sum result - switch anything that used the old sum to use
486 // the new one.
487 ReplaceValueWith(SDValue(N, 0), Res);
488
489 return SDValue(Res.getNode(), 1);
490 }
491
PromoteIntRes_SADDSUBO(SDNode * N,unsigned ResNo)492 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
493 if (ResNo == 1)
494 return PromoteIntRes_Overflow(N);
495
496 // The operation overflowed iff the result in the larger type is not the
497 // sign extension of its truncation to the original type.
498 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
499 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
500 EVT OVT = N->getOperand(0).getValueType();
501 EVT NVT = LHS.getValueType();
502 SDLoc dl(N);
503
504 // Do the arithmetic in the larger type.
505 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
506 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
507
508 // Calculate the overflow flag: sign extend the arithmetic result from
509 // the original type.
510 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
511 DAG.getValueType(OVT));
512 // Overflowed if and only if this is not equal to Res.
513 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
514
515 // Use the calculated overflow everywhere.
516 ReplaceValueWith(SDValue(N, 1), Ofl);
517
518 return Res;
519 }
520
PromoteIntRes_SDIV(SDNode * N)521 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
522 // Sign extend the input.
523 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
524 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
525 return DAG.getNode(N->getOpcode(), SDLoc(N),
526 LHS.getValueType(), LHS, RHS);
527 }
528
PromoteIntRes_SELECT(SDNode * N)529 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
530 SDValue LHS = GetPromotedInteger(N->getOperand(1));
531 SDValue RHS = GetPromotedInteger(N->getOperand(2));
532 return DAG.getSelect(SDLoc(N),
533 LHS.getValueType(), N->getOperand(0), LHS, RHS);
534 }
535
PromoteIntRes_VSELECT(SDNode * N)536 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
537 SDValue Mask = N->getOperand(0);
538 EVT OpTy = N->getOperand(1).getValueType();
539
540 // Promote all the way up to the canonical SetCC type.
541 Mask = PromoteTargetBoolean(Mask, OpTy);
542 SDValue LHS = GetPromotedInteger(N->getOperand(1));
543 SDValue RHS = GetPromotedInteger(N->getOperand(2));
544 return DAG.getNode(ISD::VSELECT, SDLoc(N),
545 LHS.getValueType(), Mask, LHS, RHS);
546 }
547
PromoteIntRes_SELECT_CC(SDNode * N)548 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
549 SDValue LHS = GetPromotedInteger(N->getOperand(2));
550 SDValue RHS = GetPromotedInteger(N->getOperand(3));
551 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
552 LHS.getValueType(), N->getOperand(0),
553 N->getOperand(1), LHS, RHS, N->getOperand(4));
554 }
555
PromoteIntRes_SETCC(SDNode * N)556 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
557 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
558
559 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
560
561 // Only use the result of getSetCCResultType if it is legal,
562 // otherwise just use the promoted result type (NVT).
563 if (!TLI.isTypeLegal(SVT))
564 SVT = NVT;
565
566 SDLoc dl(N);
567 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
568 "Vector compare must return a vector result!");
569
570 SDValue LHS = N->getOperand(0);
571 SDValue RHS = N->getOperand(1);
572 if (LHS.getValueType() != RHS.getValueType()) {
573 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
574 !LHS.getValueType().isVector())
575 LHS = GetPromotedInteger(LHS);
576 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
577 !RHS.getValueType().isVector())
578 RHS = GetPromotedInteger(RHS);
579 }
580
581 // Get the SETCC result using the canonical SETCC type.
582 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
583 N->getOperand(2));
584
585 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
586 // Convert to the expected type.
587 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
588 }
589
PromoteIntRes_SHL(SDNode * N)590 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
591 SDValue Res = GetPromotedInteger(N->getOperand(0));
592 SDValue Amt = N->getOperand(1);
593 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
594 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
595 }
596
PromoteIntRes_SIGN_EXTEND_INREG(SDNode * N)597 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
598 SDValue Op = GetPromotedInteger(N->getOperand(0));
599 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
600 Op.getValueType(), Op, N->getOperand(1));
601 }
602
PromoteIntRes_SimpleIntBinOp(SDNode * N)603 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
604 // The input may have strange things in the top bits of the registers, but
605 // these operations don't care. They may have weird bits going out, but
606 // that too is okay if they are integer operations.
607 SDValue LHS = GetPromotedInteger(N->getOperand(0));
608 SDValue RHS = GetPromotedInteger(N->getOperand(1));
609 return DAG.getNode(N->getOpcode(), SDLoc(N),
610 LHS.getValueType(), LHS, RHS);
611 }
612
PromoteIntRes_SRA(SDNode * N)613 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
614 // The input value must be properly sign extended.
615 SDValue Res = SExtPromotedInteger(N->getOperand(0));
616 SDValue Amt = N->getOperand(1);
617 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
618 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
619 }
620
PromoteIntRes_SRL(SDNode * N)621 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
622 // The input value must be properly zero extended.
623 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
624 SDValue Amt = N->getOperand(1);
625 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
626 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
627 }
628
PromoteIntRes_TRUNCATE(SDNode * N)629 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
630 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
631 SDValue Res;
632 SDValue InOp = N->getOperand(0);
633 SDLoc dl(N);
634
635 switch (getTypeAction(InOp.getValueType())) {
636 default: llvm_unreachable("Unknown type action!");
637 case TargetLowering::TypeLegal:
638 case TargetLowering::TypeExpandInteger:
639 Res = InOp;
640 break;
641 case TargetLowering::TypePromoteInteger:
642 Res = GetPromotedInteger(InOp);
643 break;
644 case TargetLowering::TypeSplitVector:
645 EVT InVT = InOp.getValueType();
646 assert(InVT.isVector() && "Cannot split scalar types");
647 unsigned NumElts = InVT.getVectorNumElements();
648 assert(NumElts == NVT.getVectorNumElements() &&
649 "Dst and Src must have the same number of elements");
650 assert(isPowerOf2_32(NumElts) &&
651 "Promoted vector type must be a power of two");
652
653 SDValue EOp1, EOp2;
654 GetSplitVector(InOp, EOp1, EOp2);
655
656 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
657 NumElts/2);
658 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
659 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
660
661 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
662 }
663
664 // Truncate to NVT instead of VT
665 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
666 }
667
PromoteIntRes_UADDSUBO(SDNode * N,unsigned ResNo)668 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
669 if (ResNo == 1)
670 return PromoteIntRes_Overflow(N);
671
672 // The operation overflowed iff the result in the larger type is not the
673 // zero extension of its truncation to the original type.
674 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
675 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
676 EVT OVT = N->getOperand(0).getValueType();
677 EVT NVT = LHS.getValueType();
678 SDLoc dl(N);
679
680 // Do the arithmetic in the larger type.
681 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
682 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
683
684 // Calculate the overflow flag: zero extend the arithmetic result from
685 // the original type.
686 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
687 // Overflowed if and only if this is not equal to Res.
688 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
689
690 // Use the calculated overflow everywhere.
691 ReplaceValueWith(SDValue(N, 1), Ofl);
692
693 return Res;
694 }
695
PromoteIntRes_XMULO(SDNode * N,unsigned ResNo)696 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
697 // Promote the overflow bit trivially.
698 if (ResNo == 1)
699 return PromoteIntRes_Overflow(N);
700
701 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
702 SDLoc DL(N);
703 EVT SmallVT = LHS.getValueType();
704
705 // To determine if the result overflowed in a larger type, we extend the
706 // input to the larger type, do the multiply (checking if it overflows),
707 // then also check the high bits of the result to see if overflow happened
708 // there.
709 if (N->getOpcode() == ISD::SMULO) {
710 LHS = SExtPromotedInteger(LHS);
711 RHS = SExtPromotedInteger(RHS);
712 } else {
713 LHS = ZExtPromotedInteger(LHS);
714 RHS = ZExtPromotedInteger(RHS);
715 }
716 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
717 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
718
719 // Overflow occurred if it occurred in the larger type, or if the high part
720 // of the result does not zero/sign-extend the low part. Check this second
721 // possibility first.
722 SDValue Overflow;
723 if (N->getOpcode() == ISD::UMULO) {
724 // Unsigned overflow occurred if the high part is non-zero.
725 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
726 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
727 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
728 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
729 } else {
730 // Signed overflow occurred if the high part does not sign extend the low.
731 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
732 Mul, DAG.getValueType(SmallVT));
733 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
734 }
735
736 // The only other way for overflow to occur is if the multiplication in the
737 // larger type itself overflowed.
738 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
739 SDValue(Mul.getNode(), 1));
740
741 // Use the calculated overflow everywhere.
742 ReplaceValueWith(SDValue(N, 1), Overflow);
743 return Mul;
744 }
745
PromoteIntRes_UDIV(SDNode * N)746 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
747 // Zero extend the input.
748 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
749 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
750 return DAG.getNode(N->getOpcode(), SDLoc(N),
751 LHS.getValueType(), LHS, RHS);
752 }
753
PromoteIntRes_UNDEF(SDNode * N)754 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
755 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
756 N->getValueType(0)));
757 }
758
PromoteIntRes_VAARG(SDNode * N)759 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
760 SDValue Chain = N->getOperand(0); // Get the chain.
761 SDValue Ptr = N->getOperand(1); // Get the pointer.
762 EVT VT = N->getValueType(0);
763 SDLoc dl(N);
764
765 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
766 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
767 // The argument is passed as NumRegs registers of type RegVT.
768
769 SmallVector<SDValue, 8> Parts(NumRegs);
770 for (unsigned i = 0; i < NumRegs; ++i) {
771 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
772 N->getConstantOperandVal(3));
773 Chain = Parts[i].getValue(1);
774 }
775
776 // Handle endianness of the load.
777 if (TLI.isBigEndian())
778 std::reverse(Parts.begin(), Parts.end());
779
780 // Assemble the parts in the promoted type.
781 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
782 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
783 for (unsigned i = 1; i < NumRegs; ++i) {
784 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
785 // Shift it to the right position and "or" it in.
786 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
787 DAG.getConstant(i * RegVT.getSizeInBits(),
788 TLI.getPointerTy()));
789 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
790 }
791
792 // Modified the chain result - switch anything that used the old chain to
793 // use the new one.
794 ReplaceValueWith(SDValue(N, 1), Chain);
795
796 return Res;
797 }
798
799 //===----------------------------------------------------------------------===//
800 // Integer Operand Promotion
801 //===----------------------------------------------------------------------===//
802
803 /// PromoteIntegerOperand - This method is called when the specified operand of
804 /// the specified node is found to need promotion. At this point, all of the
805 /// result types of the node are known to be legal, but other operands of the
806 /// node may need promotion or expansion as well as the specified one.
PromoteIntegerOperand(SDNode * N,unsigned OpNo)807 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
808 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
809 SDValue Res = SDValue();
810
811 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
812 return false;
813
814 switch (N->getOpcode()) {
815 default:
816 #ifndef NDEBUG
817 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
818 N->dump(&DAG); dbgs() << "\n";
819 #endif
820 llvm_unreachable("Do not know how to promote this operator's operand!");
821
822 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
823 case ISD::ATOMIC_STORE:
824 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
825 break;
826 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
827 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
828 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
829 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
830 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
831 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
832 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
833 case ISD::CONVERT_RNDSAT:
834 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
835 case ISD::INSERT_VECTOR_ELT:
836 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
837 case ISD::SCALAR_TO_VECTOR:
838 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
839 case ISD::VSELECT:
840 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
841 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
842 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
843 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
844 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
845 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
846 OpNo); break;
847 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
848 OpNo); break;
849 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
850 OpNo); break;
851 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
852 case ISD::FP16_TO_FP:
853 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
854 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
855
856 case ISD::SHL:
857 case ISD::SRA:
858 case ISD::SRL:
859 case ISD::ROTL:
860 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
861 }
862
863 // If the result is null, the sub-method took care of registering results etc.
864 if (!Res.getNode()) return false;
865
866 // If the result is N, the sub-method updated N in place. Tell the legalizer
867 // core about this.
868 if (Res.getNode() == N)
869 return true;
870
871 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
872 "Invalid operand expansion");
873
874 ReplaceValueWith(SDValue(N, 0), Res);
875 return false;
876 }
877
878 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
879 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
PromoteSetCCOperands(SDValue & NewLHS,SDValue & NewRHS,ISD::CondCode CCCode)880 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
881 ISD::CondCode CCCode) {
882 // We have to insert explicit sign or zero extends. Note that we could
883 // insert sign extends for ALL conditions, but zero extend is cheaper on
884 // many machines (an AND instead of two shifts), so prefer it.
885 switch (CCCode) {
886 default: llvm_unreachable("Unknown integer comparison!");
887 case ISD::SETEQ:
888 case ISD::SETNE: {
889 SDValue OpL = GetPromotedInteger(NewLHS);
890 SDValue OpR = GetPromotedInteger(NewRHS);
891
892 // We would prefer to promote the comparison operand with sign extension,
893 // if we find the operand is actually to truncate an AssertSext. With this
894 // optimization, we can avoid inserting real truncate instruction, which
895 // is redudant eventually.
896 if (OpL->getOpcode() == ISD::AssertSext &&
897 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
898 OpR->getOpcode() == ISD::AssertSext &&
899 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
900 NewLHS = OpL;
901 NewRHS = OpR;
902 } else {
903 NewLHS = ZExtPromotedInteger(NewLHS);
904 NewRHS = ZExtPromotedInteger(NewRHS);
905 }
906 break;
907 }
908 case ISD::SETUGE:
909 case ISD::SETUGT:
910 case ISD::SETULE:
911 case ISD::SETULT:
912 // ALL of these operations will work if we either sign or zero extend
913 // the operands (including the unsigned comparisons!). Zero extend is
914 // usually a simpler/cheaper operation, so prefer it.
915 NewLHS = ZExtPromotedInteger(NewLHS);
916 NewRHS = ZExtPromotedInteger(NewRHS);
917 break;
918 case ISD::SETGE:
919 case ISD::SETGT:
920 case ISD::SETLT:
921 case ISD::SETLE:
922 NewLHS = SExtPromotedInteger(NewLHS);
923 NewRHS = SExtPromotedInteger(NewRHS);
924 break;
925 }
926 }
927
PromoteIntOp_ANY_EXTEND(SDNode * N)928 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
929 SDValue Op = GetPromotedInteger(N->getOperand(0));
930 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
931 }
932
PromoteIntOp_ATOMIC_STORE(AtomicSDNode * N)933 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
934 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
935 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
936 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
937 N->getOrdering(), N->getSynchScope());
938 }
939
PromoteIntOp_BITCAST(SDNode * N)940 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
941 // This should only occur in unusual situations like bitcasting to an
942 // x86_fp80, so just turn it into a store+load
943 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
944 }
945
PromoteIntOp_BR_CC(SDNode * N,unsigned OpNo)946 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
947 assert(OpNo == 2 && "Don't know how to promote this operand!");
948
949 SDValue LHS = N->getOperand(2);
950 SDValue RHS = N->getOperand(3);
951 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
952
953 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
954 // legal types.
955 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
956 N->getOperand(1), LHS, RHS, N->getOperand(4)),
957 0);
958 }
959
PromoteIntOp_BRCOND(SDNode * N,unsigned OpNo)960 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
961 assert(OpNo == 1 && "only know how to promote condition");
962
963 // Promote all the way up to the canonical SetCC type.
964 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
965
966 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
967 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
968 N->getOperand(2)), 0);
969 }
970
PromoteIntOp_BUILD_PAIR(SDNode * N)971 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
972 // Since the result type is legal, the operands must promote to it.
973 EVT OVT = N->getOperand(0).getValueType();
974 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
975 SDValue Hi = GetPromotedInteger(N->getOperand(1));
976 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
977 SDLoc dl(N);
978
979 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
980 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
981 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
982 }
983
PromoteIntOp_BUILD_VECTOR(SDNode * N)984 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
985 // The vector type is legal but the element type is not. This implies
986 // that the vector is a power-of-two in length and that the element
987 // type does not have a strange size (eg: it is not i1).
988 EVT VecVT = N->getValueType(0);
989 unsigned NumElts = VecVT.getVectorNumElements();
990 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
991 "Legal vector of one illegal element?");
992
993 // Promote the inserted value. The type does not need to match the
994 // vector element type. Check that any extra bits introduced will be
995 // truncated away.
996 assert(N->getOperand(0).getValueType().getSizeInBits() >=
997 N->getValueType(0).getVectorElementType().getSizeInBits() &&
998 "Type of inserted value narrower than vector element type!");
999
1000 SmallVector<SDValue, 16> NewOps;
1001 for (unsigned i = 0; i < NumElts; ++i)
1002 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1003
1004 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1005 }
1006
PromoteIntOp_CONVERT_RNDSAT(SDNode * N)1007 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1008 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1009 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1010 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1011 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1012 "can only promote integer arguments");
1013 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1014 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1015 N->getOperand(1), N->getOperand(2),
1016 N->getOperand(3), N->getOperand(4), CvtCode);
1017 }
1018
PromoteIntOp_INSERT_VECTOR_ELT(SDNode * N,unsigned OpNo)1019 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1020 unsigned OpNo) {
1021 if (OpNo == 1) {
1022 // Promote the inserted value. This is valid because the type does not
1023 // have to match the vector element type.
1024
1025 // Check that any extra bits introduced will be truncated away.
1026 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1027 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1028 "Type of inserted value narrower than vector element type!");
1029 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1030 GetPromotedInteger(N->getOperand(1)),
1031 N->getOperand(2)),
1032 0);
1033 }
1034
1035 assert(OpNo == 2 && "Different operand and result vector types?");
1036
1037 // Promote the index.
1038 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1039 TLI.getVectorIdxTy());
1040 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1041 N->getOperand(1), Idx), 0);
1042 }
1043
PromoteIntOp_SCALAR_TO_VECTOR(SDNode * N)1044 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1045 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1046 // the operand in place.
1047 return SDValue(DAG.UpdateNodeOperands(N,
1048 GetPromotedInteger(N->getOperand(0))), 0);
1049 }
1050
PromoteIntOp_SELECT(SDNode * N,unsigned OpNo)1051 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1052 assert(OpNo == 0 && "Only know how to promote the condition!");
1053 SDValue Cond = N->getOperand(0);
1054 EVT OpTy = N->getOperand(1).getValueType();
1055
1056 // Promote all the way up to the canonical SetCC type.
1057 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1058 Cond = PromoteTargetBoolean(Cond, OpVT);
1059
1060 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1061 N->getOperand(2)), 0);
1062 }
1063
PromoteIntOp_SELECT_CC(SDNode * N,unsigned OpNo)1064 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1065 assert(OpNo == 0 && "Don't know how to promote this operand!");
1066
1067 SDValue LHS = N->getOperand(0);
1068 SDValue RHS = N->getOperand(1);
1069 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1070
1071 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1072 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1073 N->getOperand(3), N->getOperand(4)), 0);
1074 }
1075
PromoteIntOp_SETCC(SDNode * N,unsigned OpNo)1076 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1077 assert(OpNo == 0 && "Don't know how to promote this operand!");
1078
1079 SDValue LHS = N->getOperand(0);
1080 SDValue RHS = N->getOperand(1);
1081 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1082
1083 // The CC (#2) is always legal.
1084 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1085 }
1086
PromoteIntOp_Shift(SDNode * N)1087 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1088 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1089 ZExtPromotedInteger(N->getOperand(1))), 0);
1090 }
1091
PromoteIntOp_SIGN_EXTEND(SDNode * N)1092 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1093 SDValue Op = GetPromotedInteger(N->getOperand(0));
1094 SDLoc dl(N);
1095 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1096 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1097 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1098 }
1099
PromoteIntOp_SINT_TO_FP(SDNode * N)1100 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1101 return SDValue(DAG.UpdateNodeOperands(N,
1102 SExtPromotedInteger(N->getOperand(0))), 0);
1103 }
1104
PromoteIntOp_STORE(StoreSDNode * N,unsigned OpNo)1105 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1106 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1107 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1108 SDLoc dl(N);
1109
1110 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1111
1112 // Truncate the value and store the result.
1113 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1114 N->getMemoryVT(), N->getMemOperand());
1115 }
1116
PromoteIntOp_MSTORE(MaskedStoreSDNode * N,unsigned OpNo)1117 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1118
1119 assert(OpNo == 2 && "Only know how to promote the mask!");
1120 SDValue DataOp = N->getValue();
1121 EVT DataVT = DataOp.getValueType();
1122 SDValue Mask = N->getMask();
1123 EVT MaskVT = Mask.getValueType();
1124 SDLoc dl(N);
1125
1126 bool TruncateStore = false;
1127 if (!TLI.isTypeLegal(DataVT)) {
1128 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) {
1129 DataOp = GetPromotedInteger(DataOp);
1130 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1131 TruncateStore = true;
1132 }
1133 else {
1134 assert(getTypeAction(DataVT) == TargetLowering::TypeWidenVector &&
1135 "Unexpected data legalization in MSTORE");
1136 DataOp = GetWidenedVector(DataOp);
1137
1138 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
1139 Mask = GetWidenedVector(Mask);
1140 else {
1141 EVT BoolVT = getSetCCResultType(DataOp.getValueType());
1142
1143 // We can't use ModifyToType() because we should fill the mask with
1144 // zeroes
1145 unsigned WidenNumElts = BoolVT.getVectorNumElements();
1146 unsigned MaskNumElts = MaskVT.getVectorNumElements();
1147
1148 unsigned NumConcat = WidenNumElts / MaskNumElts;
1149 SmallVector<SDValue, 16> Ops(NumConcat);
1150 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
1151 Ops[0] = Mask;
1152 for (unsigned i = 1; i != NumConcat; ++i)
1153 Ops[i] = ZeroVal;
1154
1155 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1156 }
1157 }
1158 }
1159 else
1160 Mask = PromoteTargetBoolean(N->getMask(), DataOp.getValueType());
1161 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1162 N->getMemoryVT(), N->getMemOperand(),
1163 TruncateStore);
1164 }
1165
PromoteIntOp_MLOAD(MaskedLoadSDNode * N,unsigned OpNo)1166 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1167 assert(OpNo == 2 && "Only know how to promote the mask!");
1168 EVT DataVT = N->getValueType(0);
1169 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1170 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1171 NewOps[OpNo] = Mask;
1172 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1173 }
1174
PromoteIntOp_TRUNCATE(SDNode * N)1175 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1176 SDValue Op = GetPromotedInteger(N->getOperand(0));
1177 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1178 }
1179
PromoteIntOp_UINT_TO_FP(SDNode * N)1180 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1181 return SDValue(DAG.UpdateNodeOperands(N,
1182 ZExtPromotedInteger(N->getOperand(0))), 0);
1183 }
1184
PromoteIntOp_ZERO_EXTEND(SDNode * N)1185 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1186 SDLoc dl(N);
1187 SDValue Op = GetPromotedInteger(N->getOperand(0));
1188 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1189 return DAG.getZeroExtendInReg(Op, dl,
1190 N->getOperand(0).getValueType().getScalarType());
1191 }
1192
1193
1194 //===----------------------------------------------------------------------===//
1195 // Integer Result Expansion
1196 //===----------------------------------------------------------------------===//
1197
1198 /// ExpandIntegerResult - This method is called when the specified result of the
1199 /// specified node is found to need expansion. At this point, the node may also
1200 /// have invalid operands or may have other results that need promotion, we just
1201 /// know that (at least) one result needs expansion.
ExpandIntegerResult(SDNode * N,unsigned ResNo)1202 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1203 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1204 SDValue Lo, Hi;
1205 Lo = Hi = SDValue();
1206
1207 // See if the target wants to custom expand this node.
1208 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1209 return;
1210
1211 switch (N->getOpcode()) {
1212 default:
1213 #ifndef NDEBUG
1214 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1215 N->dump(&DAG); dbgs() << "\n";
1216 #endif
1217 llvm_unreachable("Do not know how to expand the result of this operator!");
1218
1219 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1220 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1221 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1222 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1223
1224 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1225 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1226 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1227 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1228 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1229
1230 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1231 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1232 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1233 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1234 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1235 case ISD::CTLZ_ZERO_UNDEF:
1236 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1237 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1238 case ISD::CTTZ_ZERO_UNDEF:
1239 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1240 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1241 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1242 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1243 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1244 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1245 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1246 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1247 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1248 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1249 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1250 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1251 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1252 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1253
1254 case ISD::ATOMIC_LOAD_ADD:
1255 case ISD::ATOMIC_LOAD_SUB:
1256 case ISD::ATOMIC_LOAD_AND:
1257 case ISD::ATOMIC_LOAD_OR:
1258 case ISD::ATOMIC_LOAD_XOR:
1259 case ISD::ATOMIC_LOAD_NAND:
1260 case ISD::ATOMIC_LOAD_MIN:
1261 case ISD::ATOMIC_LOAD_MAX:
1262 case ISD::ATOMIC_LOAD_UMIN:
1263 case ISD::ATOMIC_LOAD_UMAX:
1264 case ISD::ATOMIC_SWAP:
1265 case ISD::ATOMIC_CMP_SWAP: {
1266 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1267 SplitInteger(Tmp.first, Lo, Hi);
1268 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1269 break;
1270 }
1271 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1272 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1273 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1274 SDValue Tmp = DAG.getAtomicCmpSwap(
1275 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1276 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1277 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1278 AN->getSynchScope());
1279
1280 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1281 // success simply by comparing the loaded value against the ingoing
1282 // comparison.
1283 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1284 N->getOperand(2), ISD::SETEQ);
1285
1286 SplitInteger(Tmp, Lo, Hi);
1287 ReplaceValueWith(SDValue(N, 1), Success);
1288 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1289 break;
1290 }
1291
1292 case ISD::AND:
1293 case ISD::OR:
1294 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1295
1296 case ISD::ADD:
1297 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1298
1299 case ISD::ADDC:
1300 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1301
1302 case ISD::ADDE:
1303 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1304
1305 case ISD::SHL:
1306 case ISD::SRA:
1307 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1308
1309 case ISD::SADDO:
1310 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1311 case ISD::UADDO:
1312 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1313 case ISD::UMULO:
1314 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1315 }
1316
1317 // If Lo/Hi is null, the sub-method took care of registering results etc.
1318 if (Lo.getNode())
1319 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1320 }
1321
1322 /// Lower an atomic node to the appropriate builtin call.
ExpandAtomic(SDNode * Node)1323 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1324 unsigned Opc = Node->getOpcode();
1325 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1326 RTLIB::Libcall LC;
1327
1328 switch (Opc) {
1329 default:
1330 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1331 case ISD::ATOMIC_SWAP:
1332 switch (VT.SimpleTy) {
1333 default: llvm_unreachable("Unexpected value type for atomic!");
1334 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1335 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1336 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1337 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1338 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
1339 }
1340 break;
1341 case ISD::ATOMIC_CMP_SWAP:
1342 switch (VT.SimpleTy) {
1343 default: llvm_unreachable("Unexpected value type for atomic!");
1344 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1345 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1346 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1347 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1348 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
1349 }
1350 break;
1351 case ISD::ATOMIC_LOAD_ADD:
1352 switch (VT.SimpleTy) {
1353 default: llvm_unreachable("Unexpected value type for atomic!");
1354 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1355 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1356 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1357 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1358 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
1359 }
1360 break;
1361 case ISD::ATOMIC_LOAD_SUB:
1362 switch (VT.SimpleTy) {
1363 default: llvm_unreachable("Unexpected value type for atomic!");
1364 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1365 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1366 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1367 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1368 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
1369 }
1370 break;
1371 case ISD::ATOMIC_LOAD_AND:
1372 switch (VT.SimpleTy) {
1373 default: llvm_unreachable("Unexpected value type for atomic!");
1374 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1375 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1376 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1377 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1378 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
1379 }
1380 break;
1381 case ISD::ATOMIC_LOAD_OR:
1382 switch (VT.SimpleTy) {
1383 default: llvm_unreachable("Unexpected value type for atomic!");
1384 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1385 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1386 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1387 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1388 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
1389 }
1390 break;
1391 case ISD::ATOMIC_LOAD_XOR:
1392 switch (VT.SimpleTy) {
1393 default: llvm_unreachable("Unexpected value type for atomic!");
1394 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1395 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1396 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1397 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1398 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
1399 }
1400 break;
1401 case ISD::ATOMIC_LOAD_NAND:
1402 switch (VT.SimpleTy) {
1403 default: llvm_unreachable("Unexpected value type for atomic!");
1404 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1405 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1406 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1407 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1408 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
1409 }
1410 break;
1411 }
1412
1413 return ExpandChainLibCall(LC, Node, false);
1414 }
1415
1416 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1417 /// and the shift amount is a constant 'Amt'. Expand the operation.
ExpandShiftByConstant(SDNode * N,unsigned Amt,SDValue & Lo,SDValue & Hi)1418 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1419 SDValue &Lo, SDValue &Hi) {
1420 assert(Amt && "Expected zero shifts to be already optimized away.");
1421 SDLoc DL(N);
1422 // Expand the incoming operand to be shifted, so that we have its parts
1423 SDValue InL, InH;
1424 GetExpandedInteger(N->getOperand(0), InL, InH);
1425
1426 EVT NVT = InL.getValueType();
1427 unsigned VTBits = N->getValueType(0).getSizeInBits();
1428 unsigned NVTBits = NVT.getSizeInBits();
1429 EVT ShTy = N->getOperand(1).getValueType();
1430
1431 if (N->getOpcode() == ISD::SHL) {
1432 if (Amt > VTBits) {
1433 Lo = Hi = DAG.getConstant(0, NVT);
1434 } else if (Amt > NVTBits) {
1435 Lo = DAG.getConstant(0, NVT);
1436 Hi = DAG.getNode(ISD::SHL, DL,
1437 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1438 } else if (Amt == NVTBits) {
1439 Lo = DAG.getConstant(0, NVT);
1440 Hi = InL;
1441 } else if (Amt == 1 &&
1442 TLI.isOperationLegalOrCustom(ISD::ADDC,
1443 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1444 // Emit this X << 1 as X+X.
1445 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1446 SDValue LoOps[2] = { InL, InL };
1447 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1448 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1449 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1450 } else {
1451 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1452 Hi = DAG.getNode(ISD::OR, DL, NVT,
1453 DAG.getNode(ISD::SHL, DL, NVT, InH,
1454 DAG.getConstant(Amt, ShTy)),
1455 DAG.getNode(ISD::SRL, DL, NVT, InL,
1456 DAG.getConstant(NVTBits-Amt, ShTy)));
1457 }
1458 return;
1459 }
1460
1461 if (N->getOpcode() == ISD::SRL) {
1462 if (Amt > VTBits) {
1463 Lo = DAG.getConstant(0, NVT);
1464 Hi = DAG.getConstant(0, NVT);
1465 } else if (Amt > NVTBits) {
1466 Lo = DAG.getNode(ISD::SRL, DL,
1467 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1468 Hi = DAG.getConstant(0, NVT);
1469 } else if (Amt == NVTBits) {
1470 Lo = InH;
1471 Hi = DAG.getConstant(0, NVT);
1472 } else {
1473 Lo = DAG.getNode(ISD::OR, DL, NVT,
1474 DAG.getNode(ISD::SRL, DL, NVT, InL,
1475 DAG.getConstant(Amt, ShTy)),
1476 DAG.getNode(ISD::SHL, DL, NVT, InH,
1477 DAG.getConstant(NVTBits-Amt, ShTy)));
1478 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1479 }
1480 return;
1481 }
1482
1483 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1484 if (Amt > VTBits) {
1485 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1486 DAG.getConstant(NVTBits-1, ShTy));
1487 } else if (Amt > NVTBits) {
1488 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1489 DAG.getConstant(Amt-NVTBits, ShTy));
1490 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1491 DAG.getConstant(NVTBits-1, ShTy));
1492 } else if (Amt == NVTBits) {
1493 Lo = InH;
1494 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1495 DAG.getConstant(NVTBits-1, ShTy));
1496 } else {
1497 Lo = DAG.getNode(ISD::OR, DL, NVT,
1498 DAG.getNode(ISD::SRL, DL, NVT, InL,
1499 DAG.getConstant(Amt, ShTy)),
1500 DAG.getNode(ISD::SHL, DL, NVT, InH,
1501 DAG.getConstant(NVTBits-Amt, ShTy)));
1502 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1503 }
1504 }
1505
1506 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1507 /// this shift based on knowledge of the high bit of the shift amount. If we
1508 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1509 /// shift amount.
1510 bool DAGTypeLegalizer::
ExpandShiftWithKnownAmountBit(SDNode * N,SDValue & Lo,SDValue & Hi)1511 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1512 SDValue Amt = N->getOperand(1);
1513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1514 EVT ShTy = Amt.getValueType();
1515 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1516 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1517 assert(isPowerOf2_32(NVTBits) &&
1518 "Expanded integer type size not a power of two!");
1519 SDLoc dl(N);
1520
1521 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1522 APInt KnownZero, KnownOne;
1523 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1524
1525 // If we don't know anything about the high bits, exit.
1526 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1527 return false;
1528
1529 // Get the incoming operand to be shifted.
1530 SDValue InL, InH;
1531 GetExpandedInteger(N->getOperand(0), InL, InH);
1532
1533 // If we know that any of the high bits of the shift amount are one, then we
1534 // can do this as a couple of simple shifts.
1535 if (KnownOne.intersects(HighBitMask)) {
1536 // Mask out the high bit, which we know is set.
1537 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1538 DAG.getConstant(~HighBitMask, ShTy));
1539
1540 switch (N->getOpcode()) {
1541 default: llvm_unreachable("Unknown shift");
1542 case ISD::SHL:
1543 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1544 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1545 return true;
1546 case ISD::SRL:
1547 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1548 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1549 return true;
1550 case ISD::SRA:
1551 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1552 DAG.getConstant(NVTBits-1, ShTy));
1553 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1554 return true;
1555 }
1556 }
1557
1558 // If we know that all of the high bits of the shift amount are zero, then we
1559 // can do this as a couple of simple shifts.
1560 if ((KnownZero & HighBitMask) == HighBitMask) {
1561 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1562 // shift if x is zero. We can use XOR here because x is known to be smaller
1563 // than 32.
1564 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1565 DAG.getConstant(NVTBits-1, ShTy));
1566
1567 unsigned Op1, Op2;
1568 switch (N->getOpcode()) {
1569 default: llvm_unreachable("Unknown shift");
1570 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1571 case ISD::SRL:
1572 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1573 }
1574
1575 // When shifting right the arithmetic for Lo and Hi is swapped.
1576 if (N->getOpcode() != ISD::SHL)
1577 std::swap(InL, InH);
1578
1579 // Use a little trick to get the bits that move from Lo to Hi. First
1580 // shift by one bit.
1581 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1582 // Then compute the remaining shift with amount-1.
1583 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1584
1585 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1586 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1587
1588 if (N->getOpcode() != ISD::SHL)
1589 std::swap(Hi, Lo);
1590 return true;
1591 }
1592
1593 return false;
1594 }
1595
1596 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1597 /// of any size.
1598 bool DAGTypeLegalizer::
ExpandShiftWithUnknownAmountBit(SDNode * N,SDValue & Lo,SDValue & Hi)1599 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1600 SDValue Amt = N->getOperand(1);
1601 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1602 EVT ShTy = Amt.getValueType();
1603 unsigned NVTBits = NVT.getSizeInBits();
1604 assert(isPowerOf2_32(NVTBits) &&
1605 "Expanded integer type size not a power of two!");
1606 SDLoc dl(N);
1607
1608 // Get the incoming operand to be shifted.
1609 SDValue InL, InH;
1610 GetExpandedInteger(N->getOperand(0), InL, InH);
1611
1612 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1613 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1614 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1615 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1616 Amt, NVBitsNode, ISD::SETULT);
1617
1618 SDValue LoS, HiS, LoL, HiL;
1619 switch (N->getOpcode()) {
1620 default: llvm_unreachable("Unknown shift");
1621 case ISD::SHL:
1622 // Short: ShAmt < NVTBits
1623 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1624 HiS = DAG.getNode(ISD::OR, dl, NVT,
1625 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1626 // FIXME: If Amt is zero, the following shift generates an undefined result
1627 // on some architectures.
1628 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1629
1630 // Long: ShAmt >= NVTBits
1631 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1632 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1633
1634 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1635 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1636 return true;
1637 case ISD::SRL:
1638 // Short: ShAmt < NVTBits
1639 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1640 LoS = DAG.getNode(ISD::OR, dl, NVT,
1641 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1642 // FIXME: If Amt is zero, the following shift generates an undefined result
1643 // on some architectures.
1644 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1645
1646 // Long: ShAmt >= NVTBits
1647 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1648 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1649
1650 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1651 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1652 return true;
1653 case ISD::SRA:
1654 // Short: ShAmt < NVTBits
1655 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1656 LoS = DAG.getNode(ISD::OR, dl, NVT,
1657 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1658 // FIXME: If Amt is zero, the following shift generates an undefined result
1659 // on some architectures.
1660 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1661
1662 // Long: ShAmt >= NVTBits
1663 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1664 DAG.getConstant(NVTBits-1, ShTy));
1665 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1666
1667 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1668 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1669 return true;
1670 }
1671 }
1672
ExpandIntRes_ADDSUB(SDNode * N,SDValue & Lo,SDValue & Hi)1673 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1674 SDValue &Lo, SDValue &Hi) {
1675 SDLoc dl(N);
1676 // Expand the subcomponents.
1677 SDValue LHSL, LHSH, RHSL, RHSH;
1678 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1679 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1680
1681 EVT NVT = LHSL.getValueType();
1682 SDValue LoOps[2] = { LHSL, RHSL };
1683 SDValue HiOps[3] = { LHSH, RHSH };
1684
1685 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1686 // them. TODO: Teach operation legalization how to expand unsupported
1687 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1688 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1689 // generate a value of this type in the expanded code sequence.
1690 bool hasCarry =
1691 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1692 ISD::ADDC : ISD::SUBC,
1693 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1694
1695 if (hasCarry) {
1696 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1697 if (N->getOpcode() == ISD::ADD) {
1698 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1699 HiOps[2] = Lo.getValue(1);
1700 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1701 } else {
1702 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1703 HiOps[2] = Lo.getValue(1);
1704 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1705 }
1706 return;
1707 }
1708
1709 if (N->getOpcode() == ISD::ADD) {
1710 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1711 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1712 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1713 ISD::SETULT);
1714 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1715 DAG.getConstant(1, NVT),
1716 DAG.getConstant(0, NVT));
1717 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1718 ISD::SETULT);
1719 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1720 DAG.getConstant(1, NVT), Carry1);
1721 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1722 } else {
1723 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1724 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1725 SDValue Cmp =
1726 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1727 LoOps[0], LoOps[1], ISD::SETULT);
1728 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1729 DAG.getConstant(1, NVT),
1730 DAG.getConstant(0, NVT));
1731 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1732 }
1733 }
1734
ExpandIntRes_ADDSUBC(SDNode * N,SDValue & Lo,SDValue & Hi)1735 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1736 SDValue &Lo, SDValue &Hi) {
1737 // Expand the subcomponents.
1738 SDValue LHSL, LHSH, RHSL, RHSH;
1739 SDLoc dl(N);
1740 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1741 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1742 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1743 SDValue LoOps[2] = { LHSL, RHSL };
1744 SDValue HiOps[3] = { LHSH, RHSH };
1745
1746 if (N->getOpcode() == ISD::ADDC) {
1747 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1748 HiOps[2] = Lo.getValue(1);
1749 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1750 } else {
1751 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1752 HiOps[2] = Lo.getValue(1);
1753 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1754 }
1755
1756 // Legalized the flag result - switch anything that used the old flag to
1757 // use the new one.
1758 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1759 }
1760
ExpandIntRes_ADDSUBE(SDNode * N,SDValue & Lo,SDValue & Hi)1761 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1762 SDValue &Lo, SDValue &Hi) {
1763 // Expand the subcomponents.
1764 SDValue LHSL, LHSH, RHSL, RHSH;
1765 SDLoc dl(N);
1766 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1767 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1768 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1769 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1770 SDValue HiOps[3] = { LHSH, RHSH };
1771
1772 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1773 HiOps[2] = Lo.getValue(1);
1774 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1775
1776 // Legalized the flag result - switch anything that used the old flag to
1777 // use the new one.
1778 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1779 }
1780
ExpandIntRes_MERGE_VALUES(SDNode * N,unsigned ResNo,SDValue & Lo,SDValue & Hi)1781 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1782 SDValue &Lo, SDValue &Hi) {
1783 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1784 SplitInteger(Res, Lo, Hi);
1785 }
1786
ExpandIntRes_ANY_EXTEND(SDNode * N,SDValue & Lo,SDValue & Hi)1787 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1788 SDValue &Lo, SDValue &Hi) {
1789 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1790 SDLoc dl(N);
1791 SDValue Op = N->getOperand(0);
1792 if (Op.getValueType().bitsLE(NVT)) {
1793 // The low part is any extension of the input (which degenerates to a copy).
1794 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1795 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1796 } else {
1797 // For example, extension of an i48 to an i64. The operand type necessarily
1798 // promotes to the result type, so will end up being expanded too.
1799 assert(getTypeAction(Op.getValueType()) ==
1800 TargetLowering::TypePromoteInteger &&
1801 "Only know how to promote this result!");
1802 SDValue Res = GetPromotedInteger(Op);
1803 assert(Res.getValueType() == N->getValueType(0) &&
1804 "Operand over promoted?");
1805 // Split the promoted operand. This will simplify when it is expanded.
1806 SplitInteger(Res, Lo, Hi);
1807 }
1808 }
1809
ExpandIntRes_AssertSext(SDNode * N,SDValue & Lo,SDValue & Hi)1810 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1811 SDValue &Lo, SDValue &Hi) {
1812 SDLoc dl(N);
1813 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1814 EVT NVT = Lo.getValueType();
1815 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1816 unsigned NVTBits = NVT.getSizeInBits();
1817 unsigned EVTBits = EVT.getSizeInBits();
1818
1819 if (NVTBits < EVTBits) {
1820 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1821 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1822 EVTBits - NVTBits)));
1823 } else {
1824 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1825 // The high part replicates the sign bit of Lo, make it explicit.
1826 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1827 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1828 }
1829 }
1830
ExpandIntRes_AssertZext(SDNode * N,SDValue & Lo,SDValue & Hi)1831 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1832 SDValue &Lo, SDValue &Hi) {
1833 SDLoc dl(N);
1834 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1835 EVT NVT = Lo.getValueType();
1836 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1837 unsigned NVTBits = NVT.getSizeInBits();
1838 unsigned EVTBits = EVT.getSizeInBits();
1839
1840 if (NVTBits < EVTBits) {
1841 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1842 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1843 EVTBits - NVTBits)));
1844 } else {
1845 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1846 // The high part must be zero, make it explicit.
1847 Hi = DAG.getConstant(0, NVT);
1848 }
1849 }
1850
ExpandIntRes_BSWAP(SDNode * N,SDValue & Lo,SDValue & Hi)1851 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1852 SDValue &Lo, SDValue &Hi) {
1853 SDLoc dl(N);
1854 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1855 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1856 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1857 }
1858
ExpandIntRes_Constant(SDNode * N,SDValue & Lo,SDValue & Hi)1859 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1860 SDValue &Lo, SDValue &Hi) {
1861 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1862 unsigned NBitWidth = NVT.getSizeInBits();
1863 auto Constant = cast<ConstantSDNode>(N);
1864 const APInt &Cst = Constant->getAPIntValue();
1865 bool IsTarget = Constant->isTargetOpcode();
1866 bool IsOpaque = Constant->isOpaque();
1867 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT, IsTarget, IsOpaque);
1868 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT, IsTarget,
1869 IsOpaque);
1870 }
1871
ExpandIntRes_CTLZ(SDNode * N,SDValue & Lo,SDValue & Hi)1872 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1873 SDValue &Lo, SDValue &Hi) {
1874 SDLoc dl(N);
1875 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1876 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1877 EVT NVT = Lo.getValueType();
1878
1879 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1880 DAG.getConstant(0, NVT), ISD::SETNE);
1881
1882 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1883 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1884
1885 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1886 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1887 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1888 Hi = DAG.getConstant(0, NVT);
1889 }
1890
ExpandIntRes_CTPOP(SDNode * N,SDValue & Lo,SDValue & Hi)1891 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1892 SDValue &Lo, SDValue &Hi) {
1893 SDLoc dl(N);
1894 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1895 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1896 EVT NVT = Lo.getValueType();
1897 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1898 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1899 Hi = DAG.getConstant(0, NVT);
1900 }
1901
ExpandIntRes_CTTZ(SDNode * N,SDValue & Lo,SDValue & Hi)1902 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1903 SDValue &Lo, SDValue &Hi) {
1904 SDLoc dl(N);
1905 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1906 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1907 EVT NVT = Lo.getValueType();
1908
1909 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1910 DAG.getConstant(0, NVT), ISD::SETNE);
1911
1912 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1913 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1914
1915 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1916 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1917 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1918 Hi = DAG.getConstant(0, NVT);
1919 }
1920
ExpandIntRes_FP_TO_SINT(SDNode * N,SDValue & Lo,SDValue & Hi)1921 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1922 SDValue &Hi) {
1923 SDLoc dl(N);
1924 EVT VT = N->getValueType(0);
1925 SDValue Op = N->getOperand(0);
1926 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1927 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1928 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1929 dl).first,
1930 Lo, Hi);
1931 }
1932
ExpandIntRes_FP_TO_UINT(SDNode * N,SDValue & Lo,SDValue & Hi)1933 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1934 SDValue &Hi) {
1935 SDLoc dl(N);
1936 EVT VT = N->getValueType(0);
1937 SDValue Op = N->getOperand(0);
1938 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1939 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1940 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1941 dl).first,
1942 Lo, Hi);
1943 }
1944
ExpandIntRes_LOAD(LoadSDNode * N,SDValue & Lo,SDValue & Hi)1945 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1946 SDValue &Lo, SDValue &Hi) {
1947 if (ISD::isNormalLoad(N)) {
1948 ExpandRes_NormalLoad(N, Lo, Hi);
1949 return;
1950 }
1951
1952 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1953
1954 EVT VT = N->getValueType(0);
1955 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1956 SDValue Ch = N->getChain();
1957 SDValue Ptr = N->getBasePtr();
1958 ISD::LoadExtType ExtType = N->getExtensionType();
1959 unsigned Alignment = N->getAlignment();
1960 bool isVolatile = N->isVolatile();
1961 bool isNonTemporal = N->isNonTemporal();
1962 bool isInvariant = N->isInvariant();
1963 AAMDNodes AAInfo = N->getAAInfo();
1964 SDLoc dl(N);
1965
1966 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1967
1968 if (N->getMemoryVT().bitsLE(NVT)) {
1969 EVT MemVT = N->getMemoryVT();
1970
1971 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1972 MemVT, isVolatile, isNonTemporal, isInvariant,
1973 Alignment, AAInfo);
1974
1975 // Remember the chain.
1976 Ch = Lo.getValue(1);
1977
1978 if (ExtType == ISD::SEXTLOAD) {
1979 // The high part is obtained by SRA'ing all but one of the bits of the
1980 // lo part.
1981 unsigned LoSize = Lo.getValueType().getSizeInBits();
1982 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1983 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1984 } else if (ExtType == ISD::ZEXTLOAD) {
1985 // The high part is just a zero.
1986 Hi = DAG.getConstant(0, NVT);
1987 } else {
1988 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1989 // The high part is undefined.
1990 Hi = DAG.getUNDEF(NVT);
1991 }
1992 } else if (TLI.isLittleEndian()) {
1993 // Little-endian - low bits are at low addresses.
1994 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1995 isVolatile, isNonTemporal, isInvariant, Alignment,
1996 AAInfo);
1997
1998 unsigned ExcessBits =
1999 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2000 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2001
2002 // Increment the pointer to the other half.
2003 unsigned IncrementSize = NVT.getSizeInBits()/8;
2004 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2005 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2006 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2007 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2008 isVolatile, isNonTemporal, isInvariant,
2009 MinAlign(Alignment, IncrementSize), AAInfo);
2010
2011 // Build a factor node to remember that this load is independent of the
2012 // other one.
2013 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2014 Hi.getValue(1));
2015 } else {
2016 // Big-endian - high bits are at low addresses. Favor aligned loads at
2017 // the cost of some bit-fiddling.
2018 EVT MemVT = N->getMemoryVT();
2019 unsigned EBytes = MemVT.getStoreSize();
2020 unsigned IncrementSize = NVT.getSizeInBits()/8;
2021 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2022
2023 // Load both the high bits and maybe some of the low bits.
2024 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2025 EVT::getIntegerVT(*DAG.getContext(),
2026 MemVT.getSizeInBits() - ExcessBits),
2027 isVolatile, isNonTemporal, isInvariant, Alignment,
2028 AAInfo);
2029
2030 // Increment the pointer to the other half.
2031 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2032 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2033 // Load the rest of the low bits.
2034 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2035 N->getPointerInfo().getWithOffset(IncrementSize),
2036 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2037 isVolatile, isNonTemporal, isInvariant,
2038 MinAlign(Alignment, IncrementSize), AAInfo);
2039
2040 // Build a factor node to remember that this load is independent of the
2041 // other one.
2042 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2043 Hi.getValue(1));
2044
2045 if (ExcessBits < NVT.getSizeInBits()) {
2046 // Transfer low bits from the bottom of Hi to the top of Lo.
2047 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
2048 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2049 DAG.getConstant(ExcessBits,
2050 TLI.getPointerTy())));
2051 // Move high bits to the right position in Hi.
2052 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
2053 NVT, Hi,
2054 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2055 TLI.getPointerTy()));
2056 }
2057 }
2058
2059 // Legalized the chain result - switch anything that used the old chain to
2060 // use the new one.
2061 ReplaceValueWith(SDValue(N, 1), Ch);
2062 }
2063
ExpandIntRes_Logical(SDNode * N,SDValue & Lo,SDValue & Hi)2064 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2065 SDValue &Lo, SDValue &Hi) {
2066 SDLoc dl(N);
2067 SDValue LL, LH, RL, RH;
2068 GetExpandedInteger(N->getOperand(0), LL, LH);
2069 GetExpandedInteger(N->getOperand(1), RL, RH);
2070 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2071 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2072 }
2073
ExpandIntRes_MUL(SDNode * N,SDValue & Lo,SDValue & Hi)2074 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2075 SDValue &Lo, SDValue &Hi) {
2076 EVT VT = N->getValueType(0);
2077 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2078 SDLoc dl(N);
2079
2080 SDValue LL, LH, RL, RH;
2081 GetExpandedInteger(N->getOperand(0), LL, LH);
2082 GetExpandedInteger(N->getOperand(1), RL, RH);
2083
2084 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2085 return;
2086
2087 // If nothing else, we can make a libcall.
2088 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2089 if (VT == MVT::i16)
2090 LC = RTLIB::MUL_I16;
2091 else if (VT == MVT::i32)
2092 LC = RTLIB::MUL_I32;
2093 else if (VT == MVT::i64)
2094 LC = RTLIB::MUL_I64;
2095 else if (VT == MVT::i128)
2096 LC = RTLIB::MUL_I128;
2097 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2098
2099 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2100 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2101 dl).first,
2102 Lo, Hi);
2103 }
2104
ExpandIntRes_SADDSUBO(SDNode * Node,SDValue & Lo,SDValue & Hi)2105 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2106 SDValue &Lo, SDValue &Hi) {
2107 SDValue LHS = Node->getOperand(0);
2108 SDValue RHS = Node->getOperand(1);
2109 SDLoc dl(Node);
2110
2111 // Expand the result by simply replacing it with the equivalent
2112 // non-overflow-checking operation.
2113 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2114 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2115 LHS, RHS);
2116 SplitInteger(Sum, Lo, Hi);
2117
2118 // Compute the overflow.
2119 //
2120 // LHSSign -> LHS >= 0
2121 // RHSSign -> RHS >= 0
2122 // SumSign -> Sum >= 0
2123 //
2124 // Add:
2125 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2126 // Sub:
2127 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2128 //
2129 EVT OType = Node->getValueType(1);
2130 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2131
2132 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2133 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2134 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2135 Node->getOpcode() == ISD::SADDO ?
2136 ISD::SETEQ : ISD::SETNE);
2137
2138 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2139 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2140
2141 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2142
2143 // Use the calculated overflow everywhere.
2144 ReplaceValueWith(SDValue(Node, 1), Cmp);
2145 }
2146
ExpandIntRes_SDIV(SDNode * N,SDValue & Lo,SDValue & Hi)2147 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2148 SDValue &Lo, SDValue &Hi) {
2149 EVT VT = N->getValueType(0);
2150 SDLoc dl(N);
2151
2152 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2153 if (VT == MVT::i16)
2154 LC = RTLIB::SDIV_I16;
2155 else if (VT == MVT::i32)
2156 LC = RTLIB::SDIV_I32;
2157 else if (VT == MVT::i64)
2158 LC = RTLIB::SDIV_I64;
2159 else if (VT == MVT::i128)
2160 LC = RTLIB::SDIV_I128;
2161 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2162
2163 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2164 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2165 }
2166
ExpandIntRes_Shift(SDNode * N,SDValue & Lo,SDValue & Hi)2167 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2168 SDValue &Lo, SDValue &Hi) {
2169 EVT VT = N->getValueType(0);
2170 SDLoc dl(N);
2171
2172 // If we can emit an efficient shift operation, do so now. Check to see if
2173 // the RHS is a constant.
2174 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2175 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2176
2177 // If we can determine that the high bit of the shift is zero or one, even if
2178 // the low bits are variable, emit this shift in an optimized form.
2179 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2180 return;
2181
2182 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2183 unsigned PartsOpc;
2184 if (N->getOpcode() == ISD::SHL) {
2185 PartsOpc = ISD::SHL_PARTS;
2186 } else if (N->getOpcode() == ISD::SRL) {
2187 PartsOpc = ISD::SRL_PARTS;
2188 } else {
2189 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2190 PartsOpc = ISD::SRA_PARTS;
2191 }
2192
2193 // Next check to see if the target supports this SHL_PARTS operation or if it
2194 // will custom expand it.
2195 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2196 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2197 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2198 Action == TargetLowering::Custom) {
2199 // Expand the subcomponents.
2200 SDValue LHSL, LHSH;
2201 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2202 EVT VT = LHSL.getValueType();
2203
2204 // If the shift amount operand is coming from a vector legalization it may
2205 // have an illegal type. Fix that first by casting the operand, otherwise
2206 // the new SHL_PARTS operation would need further legalization.
2207 SDValue ShiftOp = N->getOperand(1);
2208 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2209 assert(ShiftTy.getScalarType().getSizeInBits() >=
2210 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2211 "ShiftAmountTy is too small to cover the range of this type!");
2212 if (ShiftOp.getValueType() != ShiftTy)
2213 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2214
2215 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2216 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2217 Hi = Lo.getValue(1);
2218 return;
2219 }
2220
2221 // Otherwise, emit a libcall.
2222 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2223 bool isSigned;
2224 if (N->getOpcode() == ISD::SHL) {
2225 isSigned = false; /*sign irrelevant*/
2226 if (VT == MVT::i16)
2227 LC = RTLIB::SHL_I16;
2228 else if (VT == MVT::i32)
2229 LC = RTLIB::SHL_I32;
2230 else if (VT == MVT::i64)
2231 LC = RTLIB::SHL_I64;
2232 else if (VT == MVT::i128)
2233 LC = RTLIB::SHL_I128;
2234 } else if (N->getOpcode() == ISD::SRL) {
2235 isSigned = false;
2236 if (VT == MVT::i16)
2237 LC = RTLIB::SRL_I16;
2238 else if (VT == MVT::i32)
2239 LC = RTLIB::SRL_I32;
2240 else if (VT == MVT::i64)
2241 LC = RTLIB::SRL_I64;
2242 else if (VT == MVT::i128)
2243 LC = RTLIB::SRL_I128;
2244 } else {
2245 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2246 isSigned = true;
2247 if (VT == MVT::i16)
2248 LC = RTLIB::SRA_I16;
2249 else if (VT == MVT::i32)
2250 LC = RTLIB::SRA_I32;
2251 else if (VT == MVT::i64)
2252 LC = RTLIB::SRA_I64;
2253 else if (VT == MVT::i128)
2254 LC = RTLIB::SRA_I128;
2255 }
2256
2257 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2258 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2259 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2260 Hi);
2261 return;
2262 }
2263
2264 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2265 llvm_unreachable("Unsupported shift!");
2266 }
2267
ExpandIntRes_SIGN_EXTEND(SDNode * N,SDValue & Lo,SDValue & Hi)2268 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2269 SDValue &Lo, SDValue &Hi) {
2270 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2271 SDLoc dl(N);
2272 SDValue Op = N->getOperand(0);
2273 if (Op.getValueType().bitsLE(NVT)) {
2274 // The low part is sign extension of the input (degenerates to a copy).
2275 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2276 // The high part is obtained by SRA'ing all but one of the bits of low part.
2277 unsigned LoSize = NVT.getSizeInBits();
2278 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2279 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2280 } else {
2281 // For example, extension of an i48 to an i64. The operand type necessarily
2282 // promotes to the result type, so will end up being expanded too.
2283 assert(getTypeAction(Op.getValueType()) ==
2284 TargetLowering::TypePromoteInteger &&
2285 "Only know how to promote this result!");
2286 SDValue Res = GetPromotedInteger(Op);
2287 assert(Res.getValueType() == N->getValueType(0) &&
2288 "Operand over promoted?");
2289 // Split the promoted operand. This will simplify when it is expanded.
2290 SplitInteger(Res, Lo, Hi);
2291 unsigned ExcessBits =
2292 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2293 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2294 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2295 ExcessBits)));
2296 }
2297 }
2298
2299 void DAGTypeLegalizer::
ExpandIntRes_SIGN_EXTEND_INREG(SDNode * N,SDValue & Lo,SDValue & Hi)2300 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2301 SDLoc dl(N);
2302 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2303 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2304
2305 if (EVT.bitsLE(Lo.getValueType())) {
2306 // sext_inreg the low part if needed.
2307 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2308 N->getOperand(1));
2309
2310 // The high part gets the sign extension from the lo-part. This handles
2311 // things like sextinreg V:i64 from i8.
2312 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2313 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2314 TLI.getPointerTy()));
2315 } else {
2316 // For example, extension of an i48 to an i64. Leave the low part alone,
2317 // sext_inreg the high part.
2318 unsigned ExcessBits =
2319 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2320 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2321 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2322 ExcessBits)));
2323 }
2324 }
2325
ExpandIntRes_SREM(SDNode * N,SDValue & Lo,SDValue & Hi)2326 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2327 SDValue &Lo, SDValue &Hi) {
2328 EVT VT = N->getValueType(0);
2329 SDLoc dl(N);
2330
2331 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2332 if (VT == MVT::i16)
2333 LC = RTLIB::SREM_I16;
2334 else if (VT == MVT::i32)
2335 LC = RTLIB::SREM_I32;
2336 else if (VT == MVT::i64)
2337 LC = RTLIB::SREM_I64;
2338 else if (VT == MVT::i128)
2339 LC = RTLIB::SREM_I128;
2340 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2341
2342 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2343 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2344 }
2345
ExpandIntRes_TRUNCATE(SDNode * N,SDValue & Lo,SDValue & Hi)2346 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2347 SDValue &Lo, SDValue &Hi) {
2348 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2349 SDLoc dl(N);
2350 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2351 Hi = DAG.getNode(ISD::SRL, dl,
2352 N->getOperand(0).getValueType(), N->getOperand(0),
2353 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2354 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2355 }
2356
ExpandIntRes_UADDSUBO(SDNode * N,SDValue & Lo,SDValue & Hi)2357 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2358 SDValue &Lo, SDValue &Hi) {
2359 SDValue LHS = N->getOperand(0);
2360 SDValue RHS = N->getOperand(1);
2361 SDLoc dl(N);
2362
2363 // Expand the result by simply replacing it with the equivalent
2364 // non-overflow-checking operation.
2365 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2366 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2367 LHS, RHS);
2368 SplitInteger(Sum, Lo, Hi);
2369
2370 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2371 // overflows iff a - b > a.
2372 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2373 N->getOpcode () == ISD::UADDO ?
2374 ISD::SETULT : ISD::SETUGT);
2375
2376 // Use the calculated overflow everywhere.
2377 ReplaceValueWith(SDValue(N, 1), Ofl);
2378 }
2379
ExpandIntRes_XMULO(SDNode * N,SDValue & Lo,SDValue & Hi)2380 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2381 SDValue &Lo, SDValue &Hi) {
2382 EVT VT = N->getValueType(0);
2383 SDLoc dl(N);
2384
2385 // A divide for UMULO should be faster than a function call.
2386 if (N->getOpcode() == ISD::UMULO) {
2387 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2388
2389 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2390 SplitInteger(MUL, Lo, Hi);
2391
2392 // A divide for UMULO will be faster than a function call. Select to
2393 // make sure we aren't using 0.
2394 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2395 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2396 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2397 DAG.getConstant(1, VT), RHS);
2398 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2399 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2400 ISD::SETNE);
2401 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2402 DAG.getConstant(0, N->getValueType(1)),
2403 Overflow);
2404 ReplaceValueWith(SDValue(N, 1), Overflow);
2405 return;
2406 }
2407
2408 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2409 EVT PtrVT = TLI.getPointerTy();
2410 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2411
2412 // Replace this with a libcall that will check overflow.
2413 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2414 if (VT == MVT::i32)
2415 LC = RTLIB::MULO_I32;
2416 else if (VT == MVT::i64)
2417 LC = RTLIB::MULO_I64;
2418 else if (VT == MVT::i128)
2419 LC = RTLIB::MULO_I128;
2420 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2421
2422 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2423 // Temporary for the overflow value, default it to zero.
2424 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2425 DAG.getConstant(0, PtrVT), Temp,
2426 MachinePointerInfo(), false, false, 0);
2427
2428 TargetLowering::ArgListTy Args;
2429 TargetLowering::ArgListEntry Entry;
2430 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2431 EVT ArgVT = N->getOperand(i).getValueType();
2432 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2433 Entry.Node = N->getOperand(i);
2434 Entry.Ty = ArgTy;
2435 Entry.isSExt = true;
2436 Entry.isZExt = false;
2437 Args.push_back(Entry);
2438 }
2439
2440 // Also pass the address of the overflow check.
2441 Entry.Node = Temp;
2442 Entry.Ty = PtrTy->getPointerTo();
2443 Entry.isSExt = true;
2444 Entry.isZExt = false;
2445 Args.push_back(Entry);
2446
2447 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2448
2449 TargetLowering::CallLoweringInfo CLI(DAG);
2450 CLI.setDebugLoc(dl).setChain(Chain)
2451 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2452 .setSExtResult();
2453
2454 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2455
2456 SplitInteger(CallInfo.first, Lo, Hi);
2457 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2458 MachinePointerInfo(), false, false, false, 0);
2459 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2460 DAG.getConstant(0, PtrVT),
2461 ISD::SETNE);
2462 // Use the overflow from the libcall everywhere.
2463 ReplaceValueWith(SDValue(N, 1), Ofl);
2464 }
2465
ExpandIntRes_UDIV(SDNode * N,SDValue & Lo,SDValue & Hi)2466 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2467 SDValue &Lo, SDValue &Hi) {
2468 EVT VT = N->getValueType(0);
2469 SDLoc dl(N);
2470
2471 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2472 if (VT == MVT::i16)
2473 LC = RTLIB::UDIV_I16;
2474 else if (VT == MVT::i32)
2475 LC = RTLIB::UDIV_I32;
2476 else if (VT == MVT::i64)
2477 LC = RTLIB::UDIV_I64;
2478 else if (VT == MVT::i128)
2479 LC = RTLIB::UDIV_I128;
2480 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2481
2482 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2483 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2484 }
2485
ExpandIntRes_UREM(SDNode * N,SDValue & Lo,SDValue & Hi)2486 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2487 SDValue &Lo, SDValue &Hi) {
2488 EVT VT = N->getValueType(0);
2489 SDLoc dl(N);
2490
2491 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2492 if (VT == MVT::i16)
2493 LC = RTLIB::UREM_I16;
2494 else if (VT == MVT::i32)
2495 LC = RTLIB::UREM_I32;
2496 else if (VT == MVT::i64)
2497 LC = RTLIB::UREM_I64;
2498 else if (VT == MVT::i128)
2499 LC = RTLIB::UREM_I128;
2500 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2501
2502 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2503 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2504 }
2505
ExpandIntRes_ZERO_EXTEND(SDNode * N,SDValue & Lo,SDValue & Hi)2506 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2507 SDValue &Lo, SDValue &Hi) {
2508 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2509 SDLoc dl(N);
2510 SDValue Op = N->getOperand(0);
2511 if (Op.getValueType().bitsLE(NVT)) {
2512 // The low part is zero extension of the input (degenerates to a copy).
2513 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2514 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2515 } else {
2516 // For example, extension of an i48 to an i64. The operand type necessarily
2517 // promotes to the result type, so will end up being expanded too.
2518 assert(getTypeAction(Op.getValueType()) ==
2519 TargetLowering::TypePromoteInteger &&
2520 "Only know how to promote this result!");
2521 SDValue Res = GetPromotedInteger(Op);
2522 assert(Res.getValueType() == N->getValueType(0) &&
2523 "Operand over promoted?");
2524 // Split the promoted operand. This will simplify when it is expanded.
2525 SplitInteger(Res, Lo, Hi);
2526 unsigned ExcessBits =
2527 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2528 Hi = DAG.getZeroExtendInReg(Hi, dl,
2529 EVT::getIntegerVT(*DAG.getContext(),
2530 ExcessBits));
2531 }
2532 }
2533
ExpandIntRes_ATOMIC_LOAD(SDNode * N,SDValue & Lo,SDValue & Hi)2534 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2535 SDValue &Lo, SDValue &Hi) {
2536 SDLoc dl(N);
2537 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2538 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2539 SDValue Zero = DAG.getConstant(0, VT);
2540 SDValue Swap = DAG.getAtomicCmpSwap(
2541 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2542 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2543 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2544 cast<AtomicSDNode>(N)->getOrdering(),
2545 cast<AtomicSDNode>(N)->getOrdering(),
2546 cast<AtomicSDNode>(N)->getSynchScope());
2547
2548 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2549 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2550 }
2551
2552 //===----------------------------------------------------------------------===//
2553 // Integer Operand Expansion
2554 //===----------------------------------------------------------------------===//
2555
2556 /// ExpandIntegerOperand - This method is called when the specified operand of
2557 /// the specified node is found to need expansion. At this point, all of the
2558 /// result types of the node are known to be legal, but other operands of the
2559 /// node may need promotion or expansion as well as the specified one.
ExpandIntegerOperand(SDNode * N,unsigned OpNo)2560 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2561 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2562 SDValue Res = SDValue();
2563
2564 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2565 return false;
2566
2567 switch (N->getOpcode()) {
2568 default:
2569 #ifndef NDEBUG
2570 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2571 N->dump(&DAG); dbgs() << "\n";
2572 #endif
2573 llvm_unreachable("Do not know how to expand this operator's operand!");
2574
2575 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2576 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2577 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2578 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2579 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2580 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2581 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2582 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2583 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2584 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2585 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2586 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2587
2588 case ISD::SHL:
2589 case ISD::SRA:
2590 case ISD::SRL:
2591 case ISD::ROTL:
2592 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2593 case ISD::RETURNADDR:
2594 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2595
2596 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2597 }
2598
2599 // If the result is null, the sub-method took care of registering results etc.
2600 if (!Res.getNode()) return false;
2601
2602 // If the result is N, the sub-method updated N in place. Tell the legalizer
2603 // core about this.
2604 if (Res.getNode() == N)
2605 return true;
2606
2607 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2608 "Invalid operand expansion");
2609
2610 ReplaceValueWith(SDValue(N, 0), Res);
2611 return false;
2612 }
2613
2614 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2615 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
IntegerExpandSetCCOperands(SDValue & NewLHS,SDValue & NewRHS,ISD::CondCode & CCCode,SDLoc dl)2616 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2617 SDValue &NewRHS,
2618 ISD::CondCode &CCCode,
2619 SDLoc dl) {
2620 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2621 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2622 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2623
2624 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2625 if (RHSLo == RHSHi) {
2626 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2627 if (RHSCST->isAllOnesValue()) {
2628 // Equality comparison to -1.
2629 NewLHS = DAG.getNode(ISD::AND, dl,
2630 LHSLo.getValueType(), LHSLo, LHSHi);
2631 NewRHS = RHSLo;
2632 return;
2633 }
2634 }
2635 }
2636
2637 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2638 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2639 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2640 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2641 return;
2642 }
2643
2644 // If this is a comparison of the sign bit, just look at the top part.
2645 // X > -1, x < 0
2646 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2647 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2648 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2649 NewLHS = LHSHi;
2650 NewRHS = RHSHi;
2651 return;
2652 }
2653
2654 // FIXME: This generated code sucks.
2655 ISD::CondCode LowCC;
2656 switch (CCCode) {
2657 default: llvm_unreachable("Unknown integer setcc!");
2658 case ISD::SETLT:
2659 case ISD::SETULT: LowCC = ISD::SETULT; break;
2660 case ISD::SETGT:
2661 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2662 case ISD::SETLE:
2663 case ISD::SETULE: LowCC = ISD::SETULE; break;
2664 case ISD::SETGE:
2665 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2666 }
2667
2668 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2669 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2670 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2671
2672 // NOTE: on targets without efficient SELECT of bools, we can always use
2673 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2674 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2675 nullptr);
2676 SDValue Tmp1, Tmp2;
2677 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2678 TLI.isTypeLegal(RHSLo.getValueType()))
2679 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2680 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2681 if (!Tmp1.getNode())
2682 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2683 LHSLo, RHSLo, LowCC);
2684 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2685 TLI.isTypeLegal(RHSHi.getValueType()))
2686 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2687 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2688 if (!Tmp2.getNode())
2689 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2690 getSetCCResultType(LHSHi.getValueType()),
2691 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2692
2693 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2694 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2695 if ((Tmp1C && Tmp1C->isNullValue()) ||
2696 (Tmp2C && Tmp2C->isNullValue() &&
2697 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2698 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2699 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2700 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2701 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2702 // low part is known false, returns high part.
2703 // For LE / GE, if high part is known false, ignore the low part.
2704 // For LT / GT, if high part is known true, ignore the low part.
2705 NewLHS = Tmp2;
2706 NewRHS = SDValue();
2707 return;
2708 }
2709
2710 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2711 LHSHi, RHSHi, ISD::SETEQ, false,
2712 DagCombineInfo, dl);
2713 if (!NewLHS.getNode())
2714 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2715 LHSHi, RHSHi, ISD::SETEQ);
2716 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2717 NewLHS, Tmp1, Tmp2);
2718 NewRHS = SDValue();
2719 }
2720
ExpandIntOp_BR_CC(SDNode * N)2721 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2722 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2723 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2724 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2725
2726 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2727 // against zero to select between true and false values.
2728 if (!NewRHS.getNode()) {
2729 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2730 CCCode = ISD::SETNE;
2731 }
2732
2733 // Update N to have the operands specified.
2734 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2735 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2736 N->getOperand(4)), 0);
2737 }
2738
ExpandIntOp_SELECT_CC(SDNode * N)2739 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2740 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2741 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2742 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2743
2744 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2745 // against zero to select between true and false values.
2746 if (!NewRHS.getNode()) {
2747 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2748 CCCode = ISD::SETNE;
2749 }
2750
2751 // Update N to have the operands specified.
2752 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2753 N->getOperand(2), N->getOperand(3),
2754 DAG.getCondCode(CCCode)), 0);
2755 }
2756
ExpandIntOp_SETCC(SDNode * N)2757 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2758 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2759 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2760 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2761
2762 // If ExpandSetCCOperands returned a scalar, use it.
2763 if (!NewRHS.getNode()) {
2764 assert(NewLHS.getValueType() == N->getValueType(0) &&
2765 "Unexpected setcc expansion!");
2766 return NewLHS;
2767 }
2768
2769 // Otherwise, update N to have the operands specified.
2770 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2771 DAG.getCondCode(CCCode)), 0);
2772 }
2773
ExpandIntOp_Shift(SDNode * N)2774 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2775 // The value being shifted is legal, but the shift amount is too big.
2776 // It follows that either the result of the shift is undefined, or the
2777 // upper half of the shift amount is zero. Just use the lower half.
2778 SDValue Lo, Hi;
2779 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2780 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2781 }
2782
ExpandIntOp_RETURNADDR(SDNode * N)2783 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2784 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2785 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2786 // constant to valid type.
2787 SDValue Lo, Hi;
2788 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2789 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2790 }
2791
ExpandIntOp_SINT_TO_FP(SDNode * N)2792 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2793 SDValue Op = N->getOperand(0);
2794 EVT DstVT = N->getValueType(0);
2795 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2796 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2797 "Don't know how to expand this SINT_TO_FP!");
2798 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2799 }
2800
ExpandIntOp_STORE(StoreSDNode * N,unsigned OpNo)2801 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2802 if (ISD::isNormalStore(N))
2803 return ExpandOp_NormalStore(N, OpNo);
2804
2805 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2806 assert(OpNo == 1 && "Can only expand the stored value so far");
2807
2808 EVT VT = N->getOperand(1).getValueType();
2809 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2810 SDValue Ch = N->getChain();
2811 SDValue Ptr = N->getBasePtr();
2812 unsigned Alignment = N->getAlignment();
2813 bool isVolatile = N->isVolatile();
2814 bool isNonTemporal = N->isNonTemporal();
2815 AAMDNodes AAInfo = N->getAAInfo();
2816 SDLoc dl(N);
2817 SDValue Lo, Hi;
2818
2819 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2820
2821 if (N->getMemoryVT().bitsLE(NVT)) {
2822 GetExpandedInteger(N->getValue(), Lo, Hi);
2823 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2824 N->getMemoryVT(), isVolatile, isNonTemporal,
2825 Alignment, AAInfo);
2826 }
2827
2828 if (TLI.isLittleEndian()) {
2829 // Little-endian - low bits are at low addresses.
2830 GetExpandedInteger(N->getValue(), Lo, Hi);
2831
2832 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2833 isVolatile, isNonTemporal, Alignment, AAInfo);
2834
2835 unsigned ExcessBits =
2836 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2837 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2838
2839 // Increment the pointer to the other half.
2840 unsigned IncrementSize = NVT.getSizeInBits()/8;
2841 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2842 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2843 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2844 N->getPointerInfo().getWithOffset(IncrementSize),
2845 NEVT, isVolatile, isNonTemporal,
2846 MinAlign(Alignment, IncrementSize), AAInfo);
2847 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2848 }
2849
2850 // Big-endian - high bits are at low addresses. Favor aligned stores at
2851 // the cost of some bit-fiddling.
2852 GetExpandedInteger(N->getValue(), Lo, Hi);
2853
2854 EVT ExtVT = N->getMemoryVT();
2855 unsigned EBytes = ExtVT.getStoreSize();
2856 unsigned IncrementSize = NVT.getSizeInBits()/8;
2857 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2858 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2859 ExtVT.getSizeInBits() - ExcessBits);
2860
2861 if (ExcessBits < NVT.getSizeInBits()) {
2862 // Transfer high bits from the top of Lo to the bottom of Hi.
2863 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2864 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2865 TLI.getPointerTy()));
2866 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2867 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2868 DAG.getConstant(ExcessBits,
2869 TLI.getPointerTy())));
2870 }
2871
2872 // Store both the high bits and maybe some of the low bits.
2873 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2874 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2875
2876 // Increment the pointer to the other half.
2877 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2878 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2879 // Store the lowest ExcessBits bits in the second half.
2880 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2881 N->getPointerInfo().getWithOffset(IncrementSize),
2882 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2883 isVolatile, isNonTemporal,
2884 MinAlign(Alignment, IncrementSize), AAInfo);
2885 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2886 }
2887
ExpandIntOp_TRUNCATE(SDNode * N)2888 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2889 SDValue InL, InH;
2890 GetExpandedInteger(N->getOperand(0), InL, InH);
2891 // Just truncate the low part of the source.
2892 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2893 }
2894
ExpandIntOp_UINT_TO_FP(SDNode * N)2895 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2896 SDValue Op = N->getOperand(0);
2897 EVT SrcVT = Op.getValueType();
2898 EVT DstVT = N->getValueType(0);
2899 SDLoc dl(N);
2900
2901 // The following optimization is valid only if every value in SrcVT (when
2902 // treated as signed) is representable in DstVT. Check that the mantissa
2903 // size of DstVT is >= than the number of bits in SrcVT -1.
2904 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2905 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2906 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2907 // Do a signed conversion then adjust the result.
2908 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2909 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2910
2911 // The result of the signed conversion needs adjusting if the 'sign bit' of
2912 // the incoming integer was set. To handle this, we dynamically test to see
2913 // if it is set, and, if so, add a fudge factor.
2914
2915 const uint64_t F32TwoE32 = 0x4F800000ULL;
2916 const uint64_t F32TwoE64 = 0x5F800000ULL;
2917 const uint64_t F32TwoE128 = 0x7F800000ULL;
2918
2919 APInt FF(32, 0);
2920 if (SrcVT == MVT::i32)
2921 FF = APInt(32, F32TwoE32);
2922 else if (SrcVT == MVT::i64)
2923 FF = APInt(32, F32TwoE64);
2924 else if (SrcVT == MVT::i128)
2925 FF = APInt(32, F32TwoE128);
2926 else
2927 llvm_unreachable("Unsupported UINT_TO_FP!");
2928
2929 // Check whether the sign bit is set.
2930 SDValue Lo, Hi;
2931 GetExpandedInteger(Op, Lo, Hi);
2932 SDValue SignSet = DAG.getSetCC(dl,
2933 getSetCCResultType(Hi.getValueType()),
2934 Hi, DAG.getConstant(0, Hi.getValueType()),
2935 ISD::SETLT);
2936
2937 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2938 SDValue FudgePtr = DAG.getConstantPool(
2939 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2940 TLI.getPointerTy());
2941
2942 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2943 SDValue Zero = DAG.getIntPtrConstant(0);
2944 SDValue Four = DAG.getIntPtrConstant(4);
2945 if (TLI.isBigEndian()) std::swap(Zero, Four);
2946 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2947 Zero, Four);
2948 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2949 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2950 FudgePtr, Offset);
2951 Alignment = std::min(Alignment, 4u);
2952
2953 // Load the value out, extending it from f32 to the destination float type.
2954 // FIXME: Avoid the extend by constructing the right constant pool?
2955 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2956 FudgePtr,
2957 MachinePointerInfo::getConstantPool(),
2958 MVT::f32,
2959 false, false, false, Alignment);
2960 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2961 }
2962
2963 // Otherwise, use a libcall.
2964 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2965 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2966 "Don't know how to expand this UINT_TO_FP!");
2967 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2968 }
2969
ExpandIntOp_ATOMIC_STORE(SDNode * N)2970 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2971 SDLoc dl(N);
2972 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2973 cast<AtomicSDNode>(N)->getMemoryVT(),
2974 N->getOperand(0),
2975 N->getOperand(1), N->getOperand(2),
2976 cast<AtomicSDNode>(N)->getMemOperand(),
2977 cast<AtomicSDNode>(N)->getOrdering(),
2978 cast<AtomicSDNode>(N)->getSynchScope());
2979 return Swap.getValue(1);
2980 }
2981
2982
PromoteIntRes_EXTRACT_SUBVECTOR(SDNode * N)2983 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2984 SDValue InOp0 = N->getOperand(0);
2985 EVT InVT = InOp0.getValueType();
2986
2987 EVT OutVT = N->getValueType(0);
2988 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2989 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2990 unsigned OutNumElems = OutVT.getVectorNumElements();
2991 EVT NOutVTElem = NOutVT.getVectorElementType();
2992
2993 SDLoc dl(N);
2994 SDValue BaseIdx = N->getOperand(1);
2995
2996 SmallVector<SDValue, 8> Ops;
2997 Ops.reserve(OutNumElems);
2998 for (unsigned i = 0; i != OutNumElems; ++i) {
2999
3000 // Extract the element from the original vector.
3001 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3002 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
3003 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3004 InVT.getVectorElementType(), N->getOperand(0), Index);
3005
3006 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3007 // Insert the converted element to the new vector.
3008 Ops.push_back(Op);
3009 }
3010
3011 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3012 }
3013
3014
PromoteIntRes_VECTOR_SHUFFLE(SDNode * N)3015 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3016 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3017 EVT VT = N->getValueType(0);
3018 SDLoc dl(N);
3019
3020 unsigned NumElts = VT.getVectorNumElements();
3021 SmallVector<int, 8> NewMask;
3022 for (unsigned i = 0; i != NumElts; ++i) {
3023 NewMask.push_back(SV->getMaskElt(i));
3024 }
3025
3026 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3027 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3028 EVT OutVT = V0.getValueType();
3029
3030 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
3031 }
3032
3033
PromoteIntRes_BUILD_VECTOR(SDNode * N)3034 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3035 EVT OutVT = N->getValueType(0);
3036 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3037 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3038 unsigned NumElems = N->getNumOperands();
3039 EVT NOutVTElem = NOutVT.getVectorElementType();
3040
3041 SDLoc dl(N);
3042
3043 SmallVector<SDValue, 8> Ops;
3044 Ops.reserve(NumElems);
3045 for (unsigned i = 0; i != NumElems; ++i) {
3046 SDValue Op;
3047 // BUILD_VECTOR integer operand types are allowed to be larger than the
3048 // result's element type. This may still be true after the promotion. For
3049 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3050 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3051 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3052 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3053 else
3054 Op = N->getOperand(i);
3055 Ops.push_back(Op);
3056 }
3057
3058 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3059 }
3060
PromoteIntRes_SCALAR_TO_VECTOR(SDNode * N)3061 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3062
3063 SDLoc dl(N);
3064
3065 assert(!N->getOperand(0).getValueType().isVector() &&
3066 "Input must be a scalar");
3067
3068 EVT OutVT = N->getValueType(0);
3069 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3070 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3071 EVT NOutVTElem = NOutVT.getVectorElementType();
3072
3073 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3074
3075 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3076 }
3077
PromoteIntRes_CONCAT_VECTORS(SDNode * N)3078 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3079 SDLoc dl(N);
3080
3081 EVT OutVT = N->getValueType(0);
3082 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3083 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3084
3085 EVT InElemTy = OutVT.getVectorElementType();
3086 EVT OutElemTy = NOutVT.getVectorElementType();
3087
3088 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3089 unsigned NumOutElem = NOutVT.getVectorNumElements();
3090 unsigned NumOperands = N->getNumOperands();
3091 assert(NumElem * NumOperands == NumOutElem &&
3092 "Unexpected number of elements");
3093
3094 // Take the elements from the first vector.
3095 SmallVector<SDValue, 8> Ops(NumOutElem);
3096 for (unsigned i = 0; i < NumOperands; ++i) {
3097 SDValue Op = N->getOperand(i);
3098 for (unsigned j = 0; j < NumElem; ++j) {
3099 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3100 InElemTy, Op, DAG.getConstant(j,
3101 TLI.getVectorIdxTy()));
3102 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3103 }
3104 }
3105
3106 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3107 }
3108
PromoteIntRes_INSERT_VECTOR_ELT(SDNode * N)3109 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3110 EVT OutVT = N->getValueType(0);
3111 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3112 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3113
3114 EVT NOutVTElem = NOutVT.getVectorElementType();
3115
3116 SDLoc dl(N);
3117 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3118
3119 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3120 NOutVTElem, N->getOperand(1));
3121 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3122 V0, ConvElem, N->getOperand(2));
3123 }
3124
PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode * N)3125 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3126 SDLoc dl(N);
3127 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3128 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3129 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3130 V0->getValueType(0).getScalarType(), V0, V1);
3131
3132 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3133 // element types. If this is the case then we need to expand the outgoing
3134 // value and not truncate it.
3135 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3136 }
3137
PromoteIntOp_CONCAT_VECTORS(SDNode * N)3138 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3139 SDLoc dl(N);
3140 unsigned NumElems = N->getNumOperands();
3141
3142 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3143
3144 SmallVector<SDValue, 8> NewOps;
3145 NewOps.reserve(NumElems);
3146
3147 // For each incoming vector
3148 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3149 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3150 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3151 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3152
3153 for (unsigned i=0; i<NumElem; ++i) {
3154 // Extract element from incoming vector
3155 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3156 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3157 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3158 NewOps.push_back(Tr);
3159 }
3160 }
3161
3162 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);
3163 }
3164