1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAG::LegalizeVectors method.
11 //
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
21 //
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
27 //
28 //===----------------------------------------------------------------------===//
29
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
32 using namespace llvm;
33
34 namespace {
35 class VectorLegalizer {
36 SelectionDAG& DAG;
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
39
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
44
45 /// \brief Adds a node to the translation cache.
AddLegalizedOperand(SDValue From,SDValue To)46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
49 if (From != To)
50 LegalizedNodes.insert(std::make_pair(To, To));
51 }
52
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
55
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
61
62 /// \brief Implement expand-based legalization of vector operations.
63 ///
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
67
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
69 /// FSUB isn't legal.
70 ///
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
74
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
77
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
79 ///
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
82 /// undef.
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
84
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
86 ///
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
89 /// extension.
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
91
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
93 ///
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
97
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
100
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
108
109 /// \brief Implements vector promotion.
110 ///
111 /// This is essentially just bitcasting the operands to a different type and
112 /// bitcasting the result back to the original type.
113 SDValue Promote(SDValue Op);
114
115 /// \brief Implements [SU]INT_TO_FP vector promotion.
116 ///
117 /// This is a [zs]ext of the input operand to the next size up.
118 SDValue PromoteINT_TO_FP(SDValue Op);
119
120 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
121 ///
122 /// It is promoted to the next size up integer type. The result is then
123 /// truncated back to the original type.
124 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
125
126 public:
127 /// \brief Begin legalizer the vector operations in the DAG.
128 bool Run();
VectorLegalizer(SelectionDAG & dag)129 VectorLegalizer(SelectionDAG& dag) :
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
131 };
132
Run()133 bool VectorLegalizer::Run() {
134 // Before we start legalizing vector nodes, check if there are any vectors.
135 bool HasVectors = false;
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
138 // Check if the values of the nodes contain vectors. We don't need to check
139 // the operands because we are going to check their values at some point.
140 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
141 J != E; ++J)
142 HasVectors |= J->isVector();
143
144 // If we found a vector node we can start the legalization.
145 if (HasVectors)
146 break;
147 }
148
149 // If this basic block has no vectors then no need to legalize vectors.
150 if (!HasVectors)
151 return false;
152
153 // The legalize process is inherently a bottom-up recursive process (users
154 // legalize their uses before themselves). Given infinite stack space, we
155 // could just start legalizing on the root and traverse the whole graph. In
156 // practice however, this causes us to run out of stack space on large basic
157 // blocks. To avoid this problem, compute an ordering of the nodes where each
158 // node is only legalized after all of its operands are legalized.
159 DAG.AssignTopologicalOrder();
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
162 LegalizeOp(SDValue(I, 0));
163
164 // Finally, it's possible the root changed. Get the new root.
165 SDValue OldRoot = DAG.getRoot();
166 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
167 DAG.setRoot(LegalizedNodes[OldRoot]);
168
169 LegalizedNodes.clear();
170
171 // Remove dead nodes now.
172 DAG.RemoveDeadNodes();
173
174 return Changed;
175 }
176
TranslateLegalizeResults(SDValue Op,SDValue Result)177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
178 // Generic legalization: just pass the operand through.
179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
180 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
181 return Result.getValue(Op.getResNo());
182 }
183
LegalizeOp(SDValue Op)184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
185 // Note that LegalizeOp may be reentered even from single-use nodes, which
186 // means that we always must cache transformed nodes.
187 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
188 if (I != LegalizedNodes.end()) return I->second;
189
190 SDNode* Node = Op.getNode();
191
192 // Legalize the operands
193 SmallVector<SDValue, 8> Ops;
194 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
195 Ops.push_back(LegalizeOp(Node->getOperand(i)));
196
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
198
199 if (Op.getOpcode() == ISD::LOAD) {
200 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
201 ISD::LoadExtType ExtType = LD->getExtensionType();
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
203 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
204 LD->getMemoryVT())) {
205 default: llvm_unreachable("This action is not supported yet!");
206 case TargetLowering::Legal:
207 return TranslateLegalizeResults(Op, Result);
208 case TargetLowering::Custom:
209 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
210 Changed = true;
211 if (Lowered->getNumValues() != Op->getNumValues()) {
212 // This expanded to something other than the load. Assume the
213 // lowering code took care of any chain values, and just handle the
214 // returned value.
215 assert(Result.getValue(1).use_empty() &&
216 "There are still live users of the old chain!");
217 return LegalizeOp(Lowered);
218 } else {
219 return TranslateLegalizeResults(Op, Lowered);
220 }
221 }
222 case TargetLowering::Expand:
223 Changed = true;
224 return LegalizeOp(ExpandLoad(Op));
225 }
226 } else if (Op.getOpcode() == ISD::STORE) {
227 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
228 EVT StVT = ST->getMemoryVT();
229 MVT ValVT = ST->getValue().getSimpleValueType();
230 if (StVT.isVector() && ST->isTruncatingStore())
231 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
232 default: llvm_unreachable("This action is not supported yet!");
233 case TargetLowering::Legal:
234 return TranslateLegalizeResults(Op, Result);
235 case TargetLowering::Custom:
236 Changed = true;
237 return TranslateLegalizeResults(Op, TLI.LowerOperation(Result, DAG));
238 case TargetLowering::Expand:
239 Changed = true;
240 return LegalizeOp(ExpandStore(Op));
241 }
242 }
243
244 bool HasVectorValue = false;
245 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
246 J != E;
247 ++J)
248 HasVectorValue |= J->isVector();
249 if (!HasVectorValue)
250 return TranslateLegalizeResults(Op, Result);
251
252 EVT QueryType;
253 switch (Op.getOpcode()) {
254 default:
255 return TranslateLegalizeResults(Op, Result);
256 case ISD::ADD:
257 case ISD::SUB:
258 case ISD::MUL:
259 case ISD::SDIV:
260 case ISD::UDIV:
261 case ISD::SREM:
262 case ISD::UREM:
263 case ISD::FADD:
264 case ISD::FSUB:
265 case ISD::FMUL:
266 case ISD::FDIV:
267 case ISD::FREM:
268 case ISD::AND:
269 case ISD::OR:
270 case ISD::XOR:
271 case ISD::SHL:
272 case ISD::SRA:
273 case ISD::SRL:
274 case ISD::ROTL:
275 case ISD::ROTR:
276 case ISD::BSWAP:
277 case ISD::CTLZ:
278 case ISD::CTTZ:
279 case ISD::CTLZ_ZERO_UNDEF:
280 case ISD::CTTZ_ZERO_UNDEF:
281 case ISD::CTPOP:
282 case ISD::SELECT:
283 case ISD::VSELECT:
284 case ISD::SELECT_CC:
285 case ISD::SETCC:
286 case ISD::ZERO_EXTEND:
287 case ISD::ANY_EXTEND:
288 case ISD::TRUNCATE:
289 case ISD::SIGN_EXTEND:
290 case ISD::FP_TO_SINT:
291 case ISD::FP_TO_UINT:
292 case ISD::FNEG:
293 case ISD::FABS:
294 case ISD::FMINNUM:
295 case ISD::FMAXNUM:
296 case ISD::FCOPYSIGN:
297 case ISD::FSQRT:
298 case ISD::FSIN:
299 case ISD::FCOS:
300 case ISD::FPOWI:
301 case ISD::FPOW:
302 case ISD::FLOG:
303 case ISD::FLOG2:
304 case ISD::FLOG10:
305 case ISD::FEXP:
306 case ISD::FEXP2:
307 case ISD::FCEIL:
308 case ISD::FTRUNC:
309 case ISD::FRINT:
310 case ISD::FNEARBYINT:
311 case ISD::FROUND:
312 case ISD::FFLOOR:
313 case ISD::FP_ROUND:
314 case ISD::FP_EXTEND:
315 case ISD::FMA:
316 case ISD::SIGN_EXTEND_INREG:
317 case ISD::ANY_EXTEND_VECTOR_INREG:
318 case ISD::SIGN_EXTEND_VECTOR_INREG:
319 case ISD::ZERO_EXTEND_VECTOR_INREG:
320 QueryType = Node->getValueType(0);
321 break;
322 case ISD::FP_ROUND_INREG:
323 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
324 break;
325 case ISD::SINT_TO_FP:
326 case ISD::UINT_TO_FP:
327 QueryType = Node->getOperand(0).getValueType();
328 break;
329 }
330
331 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
332 case TargetLowering::Promote:
333 Result = Promote(Op);
334 Changed = true;
335 break;
336 case TargetLowering::Legal:
337 break;
338 case TargetLowering::Custom: {
339 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
340 if (Tmp1.getNode()) {
341 Result = Tmp1;
342 break;
343 }
344 // FALL THROUGH
345 }
346 case TargetLowering::Expand:
347 Result = Expand(Op);
348 }
349
350 // Make sure that the generated code is itself legal.
351 if (Result != Op) {
352 Result = LegalizeOp(Result);
353 Changed = true;
354 }
355
356 // Note that LegalizeOp may be reentered even from single-use nodes, which
357 // means that we always must cache transformed nodes.
358 AddLegalizedOperand(Op, Result);
359 return Result;
360 }
361
Promote(SDValue Op)362 SDValue VectorLegalizer::Promote(SDValue Op) {
363 // For a few operations there is a specific concept for promotion based on
364 // the operand's type.
365 switch (Op.getOpcode()) {
366 case ISD::SINT_TO_FP:
367 case ISD::UINT_TO_FP:
368 // "Promote" the operation by extending the operand.
369 return PromoteINT_TO_FP(Op);
370 case ISD::FP_TO_UINT:
371 case ISD::FP_TO_SINT:
372 // Promote the operation by extending the operand.
373 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
374 }
375
376 // There are currently two cases of vector promotion:
377 // 1) Bitcasting a vector of integers to a different type to a vector of the
378 // same overall length. For example, x86 promotes ISD::AND on v2i32 to v1i64.
379 // 2) Extending a vector of floats to a vector of the same number oflarger
380 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
381 MVT VT = Op.getSimpleValueType();
382 assert(Op.getNode()->getNumValues() == 1 &&
383 "Can't promote a vector with multiple results!");
384 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
385 SDLoc dl(Op);
386 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
387
388 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
389 if (Op.getOperand(j).getValueType().isVector())
390 if (Op.getOperand(j)
391 .getValueType()
392 .getVectorElementType()
393 .isFloatingPoint() &&
394 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
395 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
396 else
397 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
398 else
399 Operands[j] = Op.getOperand(j);
400 }
401
402 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
403 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
404 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
405 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
406 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0));
407 else
408 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
409 }
410
PromoteINT_TO_FP(SDValue Op)411 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
412 // INT_TO_FP operations may require the input operand be promoted even
413 // when the type is otherwise legal.
414 EVT VT = Op.getOperand(0).getValueType();
415 assert(Op.getNode()->getNumValues() == 1 &&
416 "Can't promote a vector with multiple results!");
417
418 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
419 // by widening the vector w/ the same element width and twice the number
420 // of elements. We want the other way around, the same number of elements,
421 // each twice the width.
422 //
423 // Increase the bitwidth of the element to the next pow-of-two
424 // (which is greater than 8 bits).
425
426 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
427 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
428 SDLoc dl(Op);
429 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
430
431 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
432 ISD::SIGN_EXTEND;
433 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
434 if (Op.getOperand(j).getValueType().isVector())
435 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
436 else
437 Operands[j] = Op.getOperand(j);
438 }
439
440 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
441 }
442
443 // For FP_TO_INT we promote the result type to a vector type with wider
444 // elements and then truncate the result. This is different from the default
445 // PromoteVector which uses bitcast to promote thus assumning that the
446 // promoted vector type has the same overall size.
PromoteFP_TO_INT(SDValue Op,bool isSigned)447 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
448 assert(Op.getNode()->getNumValues() == 1 &&
449 "Can't promote a vector with multiple results!");
450 EVT VT = Op.getValueType();
451
452 EVT NewVT;
453 unsigned NewOpc;
454 while (1) {
455 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
456 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
457 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
458 NewOpc = ISD::FP_TO_SINT;
459 break;
460 }
461 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
462 NewOpc = ISD::FP_TO_UINT;
463 break;
464 }
465 }
466
467 SDLoc loc(Op);
468 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
469 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
470 }
471
472
ExpandLoad(SDValue Op)473 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
474 SDLoc dl(Op);
475 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
476 SDValue Chain = LD->getChain();
477 SDValue BasePTR = LD->getBasePtr();
478 EVT SrcVT = LD->getMemoryVT();
479 ISD::LoadExtType ExtType = LD->getExtensionType();
480
481 SmallVector<SDValue, 8> Vals;
482 SmallVector<SDValue, 8> LoadChains;
483 unsigned NumElem = SrcVT.getVectorNumElements();
484
485 EVT SrcEltVT = SrcVT.getScalarType();
486 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
487
488 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
489 // When elements in a vector is not byte-addressable, we cannot directly
490 // load each element by advancing pointer, which could only address bytes.
491 // Instead, we load all significant words, mask bits off, and concatenate
492 // them to form each element. Finally, they are extended to destination
493 // scalar type to build the destination vector.
494 EVT WideVT = TLI.getPointerTy();
495
496 assert(WideVT.isRound() &&
497 "Could not handle the sophisticated case when the widest integer is"
498 " not power of 2.");
499 assert(WideVT.bitsGE(SrcEltVT) &&
500 "Type is not legalized?");
501
502 unsigned WideBytes = WideVT.getStoreSize();
503 unsigned Offset = 0;
504 unsigned RemainingBytes = SrcVT.getStoreSize();
505 SmallVector<SDValue, 8> LoadVals;
506
507 while (RemainingBytes > 0) {
508 SDValue ScalarLoad;
509 unsigned LoadBytes = WideBytes;
510
511 if (RemainingBytes >= LoadBytes) {
512 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
513 LD->getPointerInfo().getWithOffset(Offset),
514 LD->isVolatile(), LD->isNonTemporal(),
515 LD->isInvariant(), LD->getAlignment(),
516 LD->getAAInfo());
517 } else {
518 EVT LoadVT = WideVT;
519 while (RemainingBytes < LoadBytes) {
520 LoadBytes >>= 1; // Reduce the load size by half.
521 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
522 }
523 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
524 LD->getPointerInfo().getWithOffset(Offset),
525 LoadVT, LD->isVolatile(),
526 LD->isNonTemporal(), LD->isInvariant(),
527 LD->getAlignment(), LD->getAAInfo());
528 }
529
530 RemainingBytes -= LoadBytes;
531 Offset += LoadBytes;
532 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
533 DAG.getConstant(LoadBytes, BasePTR.getValueType()));
534
535 LoadVals.push_back(ScalarLoad.getValue(0));
536 LoadChains.push_back(ScalarLoad.getValue(1));
537 }
538
539 // Extract bits, pack and extend/trunc them into destination type.
540 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
541 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
542
543 unsigned BitOffset = 0;
544 unsigned WideIdx = 0;
545 unsigned WideBits = WideVT.getSizeInBits();
546
547 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
548 SDValue Lo, Hi, ShAmt;
549
550 if (BitOffset < WideBits) {
551 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
552 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
553 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
554 }
555
556 BitOffset += SrcEltBits;
557 if (BitOffset >= WideBits) {
558 WideIdx++;
559 BitOffset -= WideBits;
560 if (BitOffset > 0) {
561 ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
562 TLI.getShiftAmountTy(WideVT));
563 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
564 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
565 }
566 }
567
568 if (Hi.getNode())
569 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
570
571 switch (ExtType) {
572 default: llvm_unreachable("Unknown extended-load op!");
573 case ISD::EXTLOAD:
574 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
575 break;
576 case ISD::ZEXTLOAD:
577 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
578 break;
579 case ISD::SEXTLOAD:
580 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
581 TLI.getShiftAmountTy(WideVT));
582 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
583 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
584 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
585 break;
586 }
587 Vals.push_back(Lo);
588 }
589 } else {
590 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
591
592 for (unsigned Idx=0; Idx<NumElem; Idx++) {
593 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
594 Op.getNode()->getValueType(0).getScalarType(),
595 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
596 SrcVT.getScalarType(),
597 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
598 LD->getAlignment(), LD->getAAInfo());
599
600 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
601 DAG.getConstant(Stride, BasePTR.getValueType()));
602
603 Vals.push_back(ScalarLoad.getValue(0));
604 LoadChains.push_back(ScalarLoad.getValue(1));
605 }
606 }
607
608 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
609 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
610 Op.getNode()->getValueType(0), Vals);
611
612 AddLegalizedOperand(Op.getValue(0), Value);
613 AddLegalizedOperand(Op.getValue(1), NewChain);
614
615 return (Op.getResNo() ? NewChain : Value);
616 }
617
ExpandStore(SDValue Op)618 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
619 SDLoc dl(Op);
620 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
621 SDValue Chain = ST->getChain();
622 SDValue BasePTR = ST->getBasePtr();
623 SDValue Value = ST->getValue();
624 EVT StVT = ST->getMemoryVT();
625
626 unsigned Alignment = ST->getAlignment();
627 bool isVolatile = ST->isVolatile();
628 bool isNonTemporal = ST->isNonTemporal();
629 AAMDNodes AAInfo = ST->getAAInfo();
630
631 unsigned NumElem = StVT.getVectorNumElements();
632 // The type of the data we want to save
633 EVT RegVT = Value.getValueType();
634 EVT RegSclVT = RegVT.getScalarType();
635 // The type of data as saved in memory.
636 EVT MemSclVT = StVT.getScalarType();
637
638 // Cast floats into integers
639 unsigned ScalarSize = MemSclVT.getSizeInBits();
640
641 // Round odd types to the next pow of two.
642 if (!isPowerOf2_32(ScalarSize))
643 ScalarSize = NextPowerOf2(ScalarSize);
644
645 // Store Stride in bytes
646 unsigned Stride = ScalarSize/8;
647 // Extract each of the elements from the original vector
648 // and save them into memory individually.
649 SmallVector<SDValue, 8> Stores;
650 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
651 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
652 RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
653
654 // This scalar TruncStore may be illegal, but we legalize it later.
655 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
656 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
657 isVolatile, isNonTemporal, Alignment, AAInfo);
658
659 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
660 DAG.getConstant(Stride, BasePTR.getValueType()));
661
662 Stores.push_back(Store);
663 }
664 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
665 AddLegalizedOperand(Op, TF);
666 return TF;
667 }
668
Expand(SDValue Op)669 SDValue VectorLegalizer::Expand(SDValue Op) {
670 switch (Op->getOpcode()) {
671 case ISD::SIGN_EXTEND_INREG:
672 return ExpandSEXTINREG(Op);
673 case ISD::ANY_EXTEND_VECTOR_INREG:
674 return ExpandANY_EXTEND_VECTOR_INREG(Op);
675 case ISD::SIGN_EXTEND_VECTOR_INREG:
676 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
677 case ISD::ZERO_EXTEND_VECTOR_INREG:
678 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
679 case ISD::BSWAP:
680 return ExpandBSWAP(Op);
681 case ISD::VSELECT:
682 return ExpandVSELECT(Op);
683 case ISD::SELECT:
684 return ExpandSELECT(Op);
685 case ISD::UINT_TO_FP:
686 return ExpandUINT_TO_FLOAT(Op);
687 case ISD::FNEG:
688 return ExpandFNEG(Op);
689 case ISD::SETCC:
690 return UnrollVSETCC(Op);
691 default:
692 return DAG.UnrollVectorOp(Op.getNode());
693 }
694 }
695
ExpandSELECT(SDValue Op)696 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
697 // Lower a select instruction where the condition is a scalar and the
698 // operands are vectors. Lower this select to VSELECT and implement it
699 // using XOR AND OR. The selector bit is broadcasted.
700 EVT VT = Op.getValueType();
701 SDLoc DL(Op);
702
703 SDValue Mask = Op.getOperand(0);
704 SDValue Op1 = Op.getOperand(1);
705 SDValue Op2 = Op.getOperand(2);
706
707 assert(VT.isVector() && !Mask.getValueType().isVector()
708 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
709
710 unsigned NumElem = VT.getVectorNumElements();
711
712 // If we can't even use the basic vector operations of
713 // AND,OR,XOR, we will have to scalarize the op.
714 // Notice that the operation may be 'promoted' which means that it is
715 // 'bitcasted' to another type which is handled.
716 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
717 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
718 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
719 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
720 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
721 return DAG.UnrollVectorOp(Op.getNode());
722
723 // Generate a mask operand.
724 EVT MaskTy = VT.changeVectorElementTypeToInteger();
725
726 // What is the size of each element in the vector mask.
727 EVT BitTy = MaskTy.getScalarType();
728
729 Mask = DAG.getSelect(DL, BitTy, Mask,
730 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
731 DAG.getConstant(0, BitTy));
732
733 // Broadcast the mask so that the entire vector is all-one or all zero.
734 SmallVector<SDValue, 8> Ops(NumElem, Mask);
735 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
736
737 // Bitcast the operands to be the same type as the mask.
738 // This is needed when we select between FP types because
739 // the mask is a vector of integers.
740 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
741 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
742
743 SDValue AllOnes = DAG.getConstant(
744 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
745 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
746
747 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
748 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
749 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
750 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
751 }
752
ExpandSEXTINREG(SDValue Op)753 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
754 EVT VT = Op.getValueType();
755
756 // Make sure that the SRA and SHL instructions are available.
757 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
758 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
759 return DAG.UnrollVectorOp(Op.getNode());
760
761 SDLoc DL(Op);
762 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
763
764 unsigned BW = VT.getScalarType().getSizeInBits();
765 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
766 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
767
768 Op = Op.getOperand(0);
769 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
770 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
771 }
772
773 // Generically expand a vector anyext in register to a shuffle of the relevant
774 // lanes into the appropriate locations, with other lanes left undef.
ExpandANY_EXTEND_VECTOR_INREG(SDValue Op)775 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
776 SDLoc DL(Op);
777 EVT VT = Op.getValueType();
778 int NumElements = VT.getVectorNumElements();
779 SDValue Src = Op.getOperand(0);
780 EVT SrcVT = Src.getValueType();
781 int NumSrcElements = SrcVT.getVectorNumElements();
782
783 // Build a base mask of undef shuffles.
784 SmallVector<int, 16> ShuffleMask;
785 ShuffleMask.resize(NumSrcElements, -1);
786
787 // Place the extended lanes into the correct locations.
788 int ExtLaneScale = NumSrcElements / NumElements;
789 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
790 for (int i = 0; i < NumElements; ++i)
791 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
792
793 return DAG.getNode(
794 ISD::BITCAST, DL, VT,
795 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
796 }
797
ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op)798 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
799 SDLoc DL(Op);
800 EVT VT = Op.getValueType();
801 SDValue Src = Op.getOperand(0);
802 EVT SrcVT = Src.getValueType();
803
804 // First build an any-extend node which can be legalized above when we
805 // recurse through it.
806 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
807
808 // Now we need sign extend. Do this by shifting the elements. Even if these
809 // aren't legal operations, they have a better chance of being legalized
810 // without full scalarization than the sign extension does.
811 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
812 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
813 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
814 return DAG.getNode(ISD::SRA, DL, VT,
815 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
816 ShiftAmount);
817 }
818
819 // Generically expand a vector zext in register to a shuffle of the relevant
820 // lanes into the appropriate locations, a blend of zero into the high bits,
821 // and a bitcast to the wider element type.
ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op)822 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
823 SDLoc DL(Op);
824 EVT VT = Op.getValueType();
825 int NumElements = VT.getVectorNumElements();
826 SDValue Src = Op.getOperand(0);
827 EVT SrcVT = Src.getValueType();
828 int NumSrcElements = SrcVT.getVectorNumElements();
829
830 // Build up a zero vector to blend into this one.
831 EVT SrcScalarVT = SrcVT.getScalarType();
832 SDValue ScalarZero = DAG.getTargetConstant(0, SrcScalarVT);
833 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
834 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
835
836 // Shuffle the incoming lanes into the correct position, and pull all other
837 // lanes from the zero vector.
838 SmallVector<int, 16> ShuffleMask;
839 ShuffleMask.reserve(NumSrcElements);
840 for (int i = 0; i < NumSrcElements; ++i)
841 ShuffleMask.push_back(i);
842
843 int ExtLaneScale = NumSrcElements / NumElements;
844 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
845 for (int i = 0; i < NumElements; ++i)
846 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
847
848 return DAG.getNode(ISD::BITCAST, DL, VT,
849 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
850 }
851
ExpandBSWAP(SDValue Op)852 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
853 EVT VT = Op.getValueType();
854
855 // Generate a byte wise shuffle mask for the BSWAP.
856 SmallVector<int, 16> ShuffleMask;
857 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
858 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
859 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
860 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
861
862 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
863
864 // Only emit a shuffle if the mask is legal.
865 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
866 return DAG.UnrollVectorOp(Op.getNode());
867
868 SDLoc DL(Op);
869 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
870 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
871 ShuffleMask.data());
872 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
873 }
874
ExpandVSELECT(SDValue Op)875 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
876 // Implement VSELECT in terms of XOR, AND, OR
877 // on platforms which do not support blend natively.
878 SDLoc DL(Op);
879
880 SDValue Mask = Op.getOperand(0);
881 SDValue Op1 = Op.getOperand(1);
882 SDValue Op2 = Op.getOperand(2);
883
884 EVT VT = Mask.getValueType();
885
886 // If we can't even use the basic vector operations of
887 // AND,OR,XOR, we will have to scalarize the op.
888 // Notice that the operation may be 'promoted' which means that it is
889 // 'bitcasted' to another type which is handled.
890 // This operation also isn't safe with AND, OR, XOR when the boolean
891 // type is 0/1 as we need an all ones vector constant to mask with.
892 // FIXME: Sign extend 1 to all ones if thats legal on the target.
893 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
894 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
895 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
896 TLI.getBooleanContents(Op1.getValueType()) !=
897 TargetLowering::ZeroOrNegativeOneBooleanContent)
898 return DAG.UnrollVectorOp(Op.getNode());
899
900 // If the mask and the type are different sizes, unroll the vector op. This
901 // can occur when getSetCCResultType returns something that is different in
902 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
903 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
904 return DAG.UnrollVectorOp(Op.getNode());
905
906 // Bitcast the operands to be the same type as the mask.
907 // This is needed when we select between FP types because
908 // the mask is a vector of integers.
909 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
910 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
911
912 SDValue AllOnes = DAG.getConstant(
913 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
914 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
915
916 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
917 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
918 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
919 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
920 }
921
ExpandUINT_TO_FLOAT(SDValue Op)922 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
923 EVT VT = Op.getOperand(0).getValueType();
924 SDLoc DL(Op);
925
926 // Make sure that the SINT_TO_FP and SRL instructions are available.
927 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
928 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
929 return DAG.UnrollVectorOp(Op.getNode());
930
931 EVT SVT = VT.getScalarType();
932 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
933 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
934
935 unsigned BW = SVT.getSizeInBits();
936 SDValue HalfWord = DAG.getConstant(BW/2, VT);
937
938 // Constants to clear the upper part of the word.
939 // Notice that we can also use SHL+SHR, but using a constant is slightly
940 // faster on x86.
941 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
942 SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
943
944 // Two to the power of half-word-size.
945 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
946
947 // Clear upper part of LO, lower HI
948 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
949 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
950
951 // Convert hi and lo to floats
952 // Convert the hi part back to the upper values
953 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
954 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
955 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
956
957 // Add the two halves
958 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
959 }
960
961
ExpandFNEG(SDValue Op)962 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
963 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
964 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
965 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
966 Zero, Op.getOperand(0));
967 }
968 return DAG.UnrollVectorOp(Op.getNode());
969 }
970
UnrollVSETCC(SDValue Op)971 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
972 EVT VT = Op.getValueType();
973 unsigned NumElems = VT.getVectorNumElements();
974 EVT EltVT = VT.getVectorElementType();
975 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
976 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
977 SDLoc dl(Op);
978 SmallVector<SDValue, 8> Ops(NumElems);
979 for (unsigned i = 0; i < NumElems; ++i) {
980 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
981 DAG.getConstant(i, TLI.getVectorIdxTy()));
982 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
983 DAG.getConstant(i, TLI.getVectorIdxTy()));
984 Ops[i] = DAG.getNode(ISD::SETCC, dl,
985 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
986 LHSElem, RHSElem, CC);
987 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
988 DAG.getConstant(APInt::getAllOnesValue
989 (EltVT.getSizeInBits()), EltVT),
990 DAG.getConstant(0, EltVT));
991 }
992 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
993 }
994
995 }
996
LegalizeVectors()997 bool SelectionDAG::LegalizeVectors() {
998 return VectorLegalizer(*this).Run();
999 }
1000