1f4a2713aSLionel Sambuc //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2f4a2713aSLionel Sambuc //
3f4a2713aSLionel Sambuc // The LLVM Compiler Infrastructure
4f4a2713aSLionel Sambuc //
5f4a2713aSLionel Sambuc // This file is distributed under the University of Illinois Open Source
6f4a2713aSLionel Sambuc // License. See LICENSE.TXT for details.
7f4a2713aSLionel Sambuc //
8f4a2713aSLionel Sambuc //===----------------------------------------------------------------------===//
9f4a2713aSLionel Sambuc //
10f4a2713aSLionel Sambuc // This implements the ScheduleDAG class, which is a base class used by
11f4a2713aSLionel Sambuc // scheduling implementation classes.
12f4a2713aSLionel Sambuc //
13f4a2713aSLionel Sambuc //===----------------------------------------------------------------------===//
14f4a2713aSLionel Sambuc
15f4a2713aSLionel Sambuc #include "ScheduleDAGSDNodes.h"
16f4a2713aSLionel Sambuc #include "InstrEmitter.h"
17f4a2713aSLionel Sambuc #include "SDNodeDbgValue.h"
18f4a2713aSLionel Sambuc #include "llvm/ADT/DenseMap.h"
19f4a2713aSLionel Sambuc #include "llvm/ADT/SmallPtrSet.h"
20f4a2713aSLionel Sambuc #include "llvm/ADT/SmallSet.h"
21f4a2713aSLionel Sambuc #include "llvm/ADT/SmallVector.h"
22f4a2713aSLionel Sambuc #include "llvm/ADT/Statistic.h"
23f4a2713aSLionel Sambuc #include "llvm/CodeGen/MachineInstrBuilder.h"
24f4a2713aSLionel Sambuc #include "llvm/CodeGen/MachineRegisterInfo.h"
25f4a2713aSLionel Sambuc #include "llvm/CodeGen/SelectionDAG.h"
26f4a2713aSLionel Sambuc #include "llvm/MC/MCInstrItineraries.h"
27f4a2713aSLionel Sambuc #include "llvm/Support/CommandLine.h"
28f4a2713aSLionel Sambuc #include "llvm/Support/Debug.h"
29f4a2713aSLionel Sambuc #include "llvm/Support/raw_ostream.h"
30f4a2713aSLionel Sambuc #include "llvm/Target/TargetInstrInfo.h"
31f4a2713aSLionel Sambuc #include "llvm/Target/TargetLowering.h"
32f4a2713aSLionel Sambuc #include "llvm/Target/TargetRegisterInfo.h"
33f4a2713aSLionel Sambuc #include "llvm/Target/TargetSubtargetInfo.h"
34f4a2713aSLionel Sambuc using namespace llvm;
35f4a2713aSLionel Sambuc
36*0a6a1f1dSLionel Sambuc #define DEBUG_TYPE "pre-RA-sched"
37*0a6a1f1dSLionel Sambuc
38f4a2713aSLionel Sambuc STATISTIC(LoadsClustered, "Number of loads clustered together");
39f4a2713aSLionel Sambuc
40*0a6a1f1dSLionel Sambuc // This allows the latency-based scheduler to notice high latency instructions
41*0a6a1f1dSLionel Sambuc // without a target itinerary. The choice of number here has more to do with
42*0a6a1f1dSLionel Sambuc // balancing scheduler heuristics than with the actual machine latency.
43f4a2713aSLionel Sambuc static cl::opt<int> HighLatencyCycles(
44f4a2713aSLionel Sambuc "sched-high-latency-cycles", cl::Hidden, cl::init(10),
45f4a2713aSLionel Sambuc cl::desc("Roughly estimate the number of cycles that 'long latency'"
46f4a2713aSLionel Sambuc "instructions take for targets with no itinerary"));
47f4a2713aSLionel Sambuc
ScheduleDAGSDNodes(MachineFunction & mf)48f4a2713aSLionel Sambuc ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
49*0a6a1f1dSLionel Sambuc : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
50*0a6a1f1dSLionel Sambuc InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
51f4a2713aSLionel Sambuc
52f4a2713aSLionel Sambuc /// Run - perform scheduling.
53f4a2713aSLionel Sambuc ///
Run(SelectionDAG * dag,MachineBasicBlock * bb)54f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
55f4a2713aSLionel Sambuc BB = bb;
56f4a2713aSLionel Sambuc DAG = dag;
57f4a2713aSLionel Sambuc
58f4a2713aSLionel Sambuc // Clear the scheduler's SUnit DAG.
59f4a2713aSLionel Sambuc ScheduleDAG::clearDAG();
60f4a2713aSLionel Sambuc Sequence.clear();
61f4a2713aSLionel Sambuc
62f4a2713aSLionel Sambuc // Invoke the target's selection of scheduler.
63f4a2713aSLionel Sambuc Schedule();
64f4a2713aSLionel Sambuc }
65f4a2713aSLionel Sambuc
66f4a2713aSLionel Sambuc /// NewSUnit - Creates a new SUnit and return a ptr to it.
67f4a2713aSLionel Sambuc ///
newSUnit(SDNode * N)68f4a2713aSLionel Sambuc SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
69f4a2713aSLionel Sambuc #ifndef NDEBUG
70*0a6a1f1dSLionel Sambuc const SUnit *Addr = nullptr;
71f4a2713aSLionel Sambuc if (!SUnits.empty())
72f4a2713aSLionel Sambuc Addr = &SUnits[0];
73f4a2713aSLionel Sambuc #endif
74f4a2713aSLionel Sambuc SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
75*0a6a1f1dSLionel Sambuc assert((Addr == nullptr || Addr == &SUnits[0]) &&
76f4a2713aSLionel Sambuc "SUnits std::vector reallocated on the fly!");
77f4a2713aSLionel Sambuc SUnits.back().OrigNode = &SUnits.back();
78f4a2713aSLionel Sambuc SUnit *SU = &SUnits.back();
79f4a2713aSLionel Sambuc const TargetLowering &TLI = DAG->getTargetLoweringInfo();
80f4a2713aSLionel Sambuc if (!N ||
81f4a2713aSLionel Sambuc (N->isMachineOpcode() &&
82f4a2713aSLionel Sambuc N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
83f4a2713aSLionel Sambuc SU->SchedulingPref = Sched::None;
84f4a2713aSLionel Sambuc else
85f4a2713aSLionel Sambuc SU->SchedulingPref = TLI.getSchedulingPreference(N);
86f4a2713aSLionel Sambuc return SU;
87f4a2713aSLionel Sambuc }
88f4a2713aSLionel Sambuc
Clone(SUnit * Old)89f4a2713aSLionel Sambuc SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
90f4a2713aSLionel Sambuc SUnit *SU = newSUnit(Old->getNode());
91f4a2713aSLionel Sambuc SU->OrigNode = Old->OrigNode;
92f4a2713aSLionel Sambuc SU->Latency = Old->Latency;
93f4a2713aSLionel Sambuc SU->isVRegCycle = Old->isVRegCycle;
94f4a2713aSLionel Sambuc SU->isCall = Old->isCall;
95f4a2713aSLionel Sambuc SU->isCallOp = Old->isCallOp;
96f4a2713aSLionel Sambuc SU->isTwoAddress = Old->isTwoAddress;
97f4a2713aSLionel Sambuc SU->isCommutable = Old->isCommutable;
98f4a2713aSLionel Sambuc SU->hasPhysRegDefs = Old->hasPhysRegDefs;
99f4a2713aSLionel Sambuc SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
100f4a2713aSLionel Sambuc SU->isScheduleHigh = Old->isScheduleHigh;
101f4a2713aSLionel Sambuc SU->isScheduleLow = Old->isScheduleLow;
102f4a2713aSLionel Sambuc SU->SchedulingPref = Old->SchedulingPref;
103f4a2713aSLionel Sambuc Old->isCloned = true;
104f4a2713aSLionel Sambuc return SU;
105f4a2713aSLionel Sambuc }
106f4a2713aSLionel Sambuc
107f4a2713aSLionel Sambuc /// CheckForPhysRegDependency - Check if the dependency between def and use of
108f4a2713aSLionel Sambuc /// a specified operand is a physical register dependency. If so, returns the
109f4a2713aSLionel Sambuc /// register and the cost of copying the register.
CheckForPhysRegDependency(SDNode * Def,SDNode * User,unsigned Op,const TargetRegisterInfo * TRI,const TargetInstrInfo * TII,unsigned & PhysReg,int & Cost)110f4a2713aSLionel Sambuc static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
111f4a2713aSLionel Sambuc const TargetRegisterInfo *TRI,
112f4a2713aSLionel Sambuc const TargetInstrInfo *TII,
113f4a2713aSLionel Sambuc unsigned &PhysReg, int &Cost) {
114f4a2713aSLionel Sambuc if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
115f4a2713aSLionel Sambuc return;
116f4a2713aSLionel Sambuc
117f4a2713aSLionel Sambuc unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118f4a2713aSLionel Sambuc if (TargetRegisterInfo::isVirtualRegister(Reg))
119f4a2713aSLionel Sambuc return;
120f4a2713aSLionel Sambuc
121f4a2713aSLionel Sambuc unsigned ResNo = User->getOperand(2).getResNo();
122*0a6a1f1dSLionel Sambuc if (Def->getOpcode() == ISD::CopyFromReg &&
123*0a6a1f1dSLionel Sambuc cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
124*0a6a1f1dSLionel Sambuc PhysReg = Reg;
125*0a6a1f1dSLionel Sambuc } else if (Def->isMachineOpcode()) {
126f4a2713aSLionel Sambuc const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
127f4a2713aSLionel Sambuc if (ResNo >= II.getNumDefs() &&
128*0a6a1f1dSLionel Sambuc II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
129f4a2713aSLionel Sambuc PhysReg = Reg;
130f4a2713aSLionel Sambuc }
131*0a6a1f1dSLionel Sambuc
132*0a6a1f1dSLionel Sambuc if (PhysReg != 0) {
133*0a6a1f1dSLionel Sambuc const TargetRegisterClass *RC =
134*0a6a1f1dSLionel Sambuc TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
135*0a6a1f1dSLionel Sambuc Cost = RC->getCopyCost();
136f4a2713aSLionel Sambuc }
137f4a2713aSLionel Sambuc }
138f4a2713aSLionel Sambuc
139f4a2713aSLionel Sambuc // Helper for AddGlue to clone node operands.
CloneNodeWithValues(SDNode * N,SelectionDAG * DAG,SmallVectorImpl<EVT> & VTs,SDValue ExtraOper=SDValue ())140f4a2713aSLionel Sambuc static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG,
141f4a2713aSLionel Sambuc SmallVectorImpl<EVT> &VTs,
142f4a2713aSLionel Sambuc SDValue ExtraOper = SDValue()) {
143*0a6a1f1dSLionel Sambuc SmallVector<SDValue, 8> Ops;
144f4a2713aSLionel Sambuc for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
145f4a2713aSLionel Sambuc Ops.push_back(N->getOperand(I));
146f4a2713aSLionel Sambuc
147f4a2713aSLionel Sambuc if (ExtraOper.getNode())
148f4a2713aSLionel Sambuc Ops.push_back(ExtraOper);
149f4a2713aSLionel Sambuc
150*0a6a1f1dSLionel Sambuc SDVTList VTList = DAG->getVTList(VTs);
151*0a6a1f1dSLionel Sambuc MachineSDNode::mmo_iterator Begin = nullptr, End = nullptr;
152f4a2713aSLionel Sambuc MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
153f4a2713aSLionel Sambuc
154f4a2713aSLionel Sambuc // Store memory references.
155f4a2713aSLionel Sambuc if (MN) {
156f4a2713aSLionel Sambuc Begin = MN->memoperands_begin();
157f4a2713aSLionel Sambuc End = MN->memoperands_end();
158f4a2713aSLionel Sambuc }
159f4a2713aSLionel Sambuc
160*0a6a1f1dSLionel Sambuc DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
161f4a2713aSLionel Sambuc
162f4a2713aSLionel Sambuc // Reset the memory references
163f4a2713aSLionel Sambuc if (MN)
164f4a2713aSLionel Sambuc MN->setMemRefs(Begin, End);
165f4a2713aSLionel Sambuc }
166f4a2713aSLionel Sambuc
AddGlue(SDNode * N,SDValue Glue,bool AddGlue,SelectionDAG * DAG)167f4a2713aSLionel Sambuc static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
168f4a2713aSLionel Sambuc SmallVector<EVT, 4> VTs;
169f4a2713aSLionel Sambuc SDNode *GlueDestNode = Glue.getNode();
170f4a2713aSLionel Sambuc
171f4a2713aSLionel Sambuc // Don't add glue from a node to itself.
172f4a2713aSLionel Sambuc if (GlueDestNode == N) return false;
173f4a2713aSLionel Sambuc
174f4a2713aSLionel Sambuc // Don't add a glue operand to something that already uses glue.
175f4a2713aSLionel Sambuc if (GlueDestNode &&
176f4a2713aSLionel Sambuc N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
177f4a2713aSLionel Sambuc return false;
178f4a2713aSLionel Sambuc }
179f4a2713aSLionel Sambuc // Don't add glue to something that already has a glue value.
180f4a2713aSLionel Sambuc if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
181f4a2713aSLionel Sambuc
182f4a2713aSLionel Sambuc for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
183f4a2713aSLionel Sambuc VTs.push_back(N->getValueType(I));
184f4a2713aSLionel Sambuc
185f4a2713aSLionel Sambuc if (AddGlue)
186f4a2713aSLionel Sambuc VTs.push_back(MVT::Glue);
187f4a2713aSLionel Sambuc
188f4a2713aSLionel Sambuc CloneNodeWithValues(N, DAG, VTs, Glue);
189f4a2713aSLionel Sambuc
190f4a2713aSLionel Sambuc return true;
191f4a2713aSLionel Sambuc }
192f4a2713aSLionel Sambuc
193f4a2713aSLionel Sambuc // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
194f4a2713aSLionel Sambuc // node even though simply shrinking the value list is sufficient.
RemoveUnusedGlue(SDNode * N,SelectionDAG * DAG)195f4a2713aSLionel Sambuc static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
196f4a2713aSLionel Sambuc assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
197f4a2713aSLionel Sambuc !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
198f4a2713aSLionel Sambuc "expected an unused glue value");
199f4a2713aSLionel Sambuc
200f4a2713aSLionel Sambuc SmallVector<EVT, 4> VTs;
201f4a2713aSLionel Sambuc for (unsigned I = 0, E = N->getNumValues()-1; I != E; ++I)
202f4a2713aSLionel Sambuc VTs.push_back(N->getValueType(I));
203f4a2713aSLionel Sambuc
204f4a2713aSLionel Sambuc CloneNodeWithValues(N, DAG, VTs);
205f4a2713aSLionel Sambuc }
206f4a2713aSLionel Sambuc
207f4a2713aSLionel Sambuc /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
208f4a2713aSLionel Sambuc /// This function finds loads of the same base and different offsets. If the
209f4a2713aSLionel Sambuc /// offsets are not far apart (target specific), it add MVT::Glue inputs and
210f4a2713aSLionel Sambuc /// outputs to ensure they are scheduled together and in order. This
211f4a2713aSLionel Sambuc /// optimization may benefit some targets by improving cache locality.
ClusterNeighboringLoads(SDNode * Node)212f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
213*0a6a1f1dSLionel Sambuc SDNode *Chain = nullptr;
214f4a2713aSLionel Sambuc unsigned NumOps = Node->getNumOperands();
215f4a2713aSLionel Sambuc if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
216f4a2713aSLionel Sambuc Chain = Node->getOperand(NumOps-1).getNode();
217f4a2713aSLionel Sambuc if (!Chain)
218f4a2713aSLionel Sambuc return;
219f4a2713aSLionel Sambuc
220f4a2713aSLionel Sambuc // Look for other loads of the same chain. Find loads that are loading from
221f4a2713aSLionel Sambuc // the same base pointer and different offsets.
222f4a2713aSLionel Sambuc SmallPtrSet<SDNode*, 16> Visited;
223f4a2713aSLionel Sambuc SmallVector<int64_t, 4> Offsets;
224f4a2713aSLionel Sambuc DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
225f4a2713aSLionel Sambuc bool Cluster = false;
226f4a2713aSLionel Sambuc SDNode *Base = Node;
227*0a6a1f1dSLionel Sambuc // This algorithm requires a reasonably low use count before finding a match
228*0a6a1f1dSLionel Sambuc // to avoid uselessly blowing up compile time in large blocks.
229*0a6a1f1dSLionel Sambuc unsigned UseCount = 0;
230f4a2713aSLionel Sambuc for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
231*0a6a1f1dSLionel Sambuc I != E && UseCount < 100; ++I, ++UseCount) {
232f4a2713aSLionel Sambuc SDNode *User = *I;
233*0a6a1f1dSLionel Sambuc if (User == Node || !Visited.insert(User).second)
234f4a2713aSLionel Sambuc continue;
235f4a2713aSLionel Sambuc int64_t Offset1, Offset2;
236f4a2713aSLionel Sambuc if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
237f4a2713aSLionel Sambuc Offset1 == Offset2)
238f4a2713aSLionel Sambuc // FIXME: Should be ok if they addresses are identical. But earlier
239f4a2713aSLionel Sambuc // optimizations really should have eliminated one of the loads.
240f4a2713aSLionel Sambuc continue;
241f4a2713aSLionel Sambuc if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
242f4a2713aSLionel Sambuc Offsets.push_back(Offset1);
243f4a2713aSLionel Sambuc O2SMap.insert(std::make_pair(Offset2, User));
244f4a2713aSLionel Sambuc Offsets.push_back(Offset2);
245f4a2713aSLionel Sambuc if (Offset2 < Offset1)
246f4a2713aSLionel Sambuc Base = User;
247f4a2713aSLionel Sambuc Cluster = true;
248*0a6a1f1dSLionel Sambuc // Reset UseCount to allow more matches.
249*0a6a1f1dSLionel Sambuc UseCount = 0;
250f4a2713aSLionel Sambuc }
251f4a2713aSLionel Sambuc
252f4a2713aSLionel Sambuc if (!Cluster)
253f4a2713aSLionel Sambuc return;
254f4a2713aSLionel Sambuc
255f4a2713aSLionel Sambuc // Sort them in increasing order.
256f4a2713aSLionel Sambuc std::sort(Offsets.begin(), Offsets.end());
257f4a2713aSLionel Sambuc
258f4a2713aSLionel Sambuc // Check if the loads are close enough.
259f4a2713aSLionel Sambuc SmallVector<SDNode*, 4> Loads;
260f4a2713aSLionel Sambuc unsigned NumLoads = 0;
261f4a2713aSLionel Sambuc int64_t BaseOff = Offsets[0];
262f4a2713aSLionel Sambuc SDNode *BaseLoad = O2SMap[BaseOff];
263f4a2713aSLionel Sambuc Loads.push_back(BaseLoad);
264f4a2713aSLionel Sambuc for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
265f4a2713aSLionel Sambuc int64_t Offset = Offsets[i];
266f4a2713aSLionel Sambuc SDNode *Load = O2SMap[Offset];
267f4a2713aSLionel Sambuc if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
268f4a2713aSLionel Sambuc break; // Stop right here. Ignore loads that are further away.
269f4a2713aSLionel Sambuc Loads.push_back(Load);
270f4a2713aSLionel Sambuc ++NumLoads;
271f4a2713aSLionel Sambuc }
272f4a2713aSLionel Sambuc
273f4a2713aSLionel Sambuc if (NumLoads == 0)
274f4a2713aSLionel Sambuc return;
275f4a2713aSLionel Sambuc
276f4a2713aSLionel Sambuc // Cluster loads by adding MVT::Glue outputs and inputs. This also
277f4a2713aSLionel Sambuc // ensure they are scheduled in order of increasing addresses.
278f4a2713aSLionel Sambuc SDNode *Lead = Loads[0];
279*0a6a1f1dSLionel Sambuc SDValue InGlue = SDValue(nullptr, 0);
280f4a2713aSLionel Sambuc if (AddGlue(Lead, InGlue, true, DAG))
281f4a2713aSLionel Sambuc InGlue = SDValue(Lead, Lead->getNumValues() - 1);
282f4a2713aSLionel Sambuc for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
283f4a2713aSLionel Sambuc bool OutGlue = I < E - 1;
284f4a2713aSLionel Sambuc SDNode *Load = Loads[I];
285f4a2713aSLionel Sambuc
286f4a2713aSLionel Sambuc // If AddGlue fails, we could leave an unsused glue value. This should not
287f4a2713aSLionel Sambuc // cause any
288f4a2713aSLionel Sambuc if (AddGlue(Load, InGlue, OutGlue, DAG)) {
289f4a2713aSLionel Sambuc if (OutGlue)
290f4a2713aSLionel Sambuc InGlue = SDValue(Load, Load->getNumValues() - 1);
291f4a2713aSLionel Sambuc
292f4a2713aSLionel Sambuc ++LoadsClustered;
293f4a2713aSLionel Sambuc }
294f4a2713aSLionel Sambuc else if (!OutGlue && InGlue.getNode())
295f4a2713aSLionel Sambuc RemoveUnusedGlue(InGlue.getNode(), DAG);
296f4a2713aSLionel Sambuc }
297f4a2713aSLionel Sambuc }
298f4a2713aSLionel Sambuc
299f4a2713aSLionel Sambuc /// ClusterNodes - Cluster certain nodes which should be scheduled together.
300f4a2713aSLionel Sambuc ///
ClusterNodes()301f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::ClusterNodes() {
302f4a2713aSLionel Sambuc for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
303f4a2713aSLionel Sambuc E = DAG->allnodes_end(); NI != E; ++NI) {
304f4a2713aSLionel Sambuc SDNode *Node = &*NI;
305f4a2713aSLionel Sambuc if (!Node || !Node->isMachineOpcode())
306f4a2713aSLionel Sambuc continue;
307f4a2713aSLionel Sambuc
308f4a2713aSLionel Sambuc unsigned Opc = Node->getMachineOpcode();
309f4a2713aSLionel Sambuc const MCInstrDesc &MCID = TII->get(Opc);
310f4a2713aSLionel Sambuc if (MCID.mayLoad())
311f4a2713aSLionel Sambuc // Cluster loads from "near" addresses into combined SUnits.
312f4a2713aSLionel Sambuc ClusterNeighboringLoads(Node);
313f4a2713aSLionel Sambuc }
314f4a2713aSLionel Sambuc }
315f4a2713aSLionel Sambuc
BuildSchedUnits()316f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::BuildSchedUnits() {
317f4a2713aSLionel Sambuc // During scheduling, the NodeId field of SDNode is used to map SDNodes
318f4a2713aSLionel Sambuc // to their associated SUnits by holding SUnits table indices. A value
319f4a2713aSLionel Sambuc // of -1 means the SDNode does not yet have an associated SUnit.
320f4a2713aSLionel Sambuc unsigned NumNodes = 0;
321f4a2713aSLionel Sambuc for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
322f4a2713aSLionel Sambuc E = DAG->allnodes_end(); NI != E; ++NI) {
323f4a2713aSLionel Sambuc NI->setNodeId(-1);
324f4a2713aSLionel Sambuc ++NumNodes;
325f4a2713aSLionel Sambuc }
326f4a2713aSLionel Sambuc
327f4a2713aSLionel Sambuc // Reserve entries in the vector for each of the SUnits we are creating. This
328f4a2713aSLionel Sambuc // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
329f4a2713aSLionel Sambuc // invalidated.
330f4a2713aSLionel Sambuc // FIXME: Multiply by 2 because we may clone nodes during scheduling.
331f4a2713aSLionel Sambuc // This is a temporary workaround.
332f4a2713aSLionel Sambuc SUnits.reserve(NumNodes * 2);
333f4a2713aSLionel Sambuc
334f4a2713aSLionel Sambuc // Add all nodes in depth first order.
335f4a2713aSLionel Sambuc SmallVector<SDNode*, 64> Worklist;
336f4a2713aSLionel Sambuc SmallPtrSet<SDNode*, 64> Visited;
337f4a2713aSLionel Sambuc Worklist.push_back(DAG->getRoot().getNode());
338f4a2713aSLionel Sambuc Visited.insert(DAG->getRoot().getNode());
339f4a2713aSLionel Sambuc
340f4a2713aSLionel Sambuc SmallVector<SUnit*, 8> CallSUnits;
341f4a2713aSLionel Sambuc while (!Worklist.empty()) {
342f4a2713aSLionel Sambuc SDNode *NI = Worklist.pop_back_val();
343f4a2713aSLionel Sambuc
344f4a2713aSLionel Sambuc // Add all operands to the worklist unless they've already been added.
345f4a2713aSLionel Sambuc for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
346*0a6a1f1dSLionel Sambuc if (Visited.insert(NI->getOperand(i).getNode()).second)
347f4a2713aSLionel Sambuc Worklist.push_back(NI->getOperand(i).getNode());
348f4a2713aSLionel Sambuc
349f4a2713aSLionel Sambuc if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
350f4a2713aSLionel Sambuc continue;
351f4a2713aSLionel Sambuc
352f4a2713aSLionel Sambuc // If this node has already been processed, stop now.
353f4a2713aSLionel Sambuc if (NI->getNodeId() != -1) continue;
354f4a2713aSLionel Sambuc
355f4a2713aSLionel Sambuc SUnit *NodeSUnit = newSUnit(NI);
356f4a2713aSLionel Sambuc
357f4a2713aSLionel Sambuc // See if anything is glued to this node, if so, add them to glued
358f4a2713aSLionel Sambuc // nodes. Nodes can have at most one glue input and one glue output. Glue
359f4a2713aSLionel Sambuc // is required to be the last operand and result of a node.
360f4a2713aSLionel Sambuc
361f4a2713aSLionel Sambuc // Scan up to find glued preds.
362f4a2713aSLionel Sambuc SDNode *N = NI;
363f4a2713aSLionel Sambuc while (N->getNumOperands() &&
364f4a2713aSLionel Sambuc N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
365f4a2713aSLionel Sambuc N = N->getOperand(N->getNumOperands()-1).getNode();
366f4a2713aSLionel Sambuc assert(N->getNodeId() == -1 && "Node already inserted!");
367f4a2713aSLionel Sambuc N->setNodeId(NodeSUnit->NodeNum);
368f4a2713aSLionel Sambuc if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
369f4a2713aSLionel Sambuc NodeSUnit->isCall = true;
370f4a2713aSLionel Sambuc }
371f4a2713aSLionel Sambuc
372f4a2713aSLionel Sambuc // Scan down to find any glued succs.
373f4a2713aSLionel Sambuc N = NI;
374f4a2713aSLionel Sambuc while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
375f4a2713aSLionel Sambuc SDValue GlueVal(N, N->getNumValues()-1);
376f4a2713aSLionel Sambuc
377f4a2713aSLionel Sambuc // There are either zero or one users of the Glue result.
378f4a2713aSLionel Sambuc bool HasGlueUse = false;
379f4a2713aSLionel Sambuc for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
380f4a2713aSLionel Sambuc UI != E; ++UI)
381f4a2713aSLionel Sambuc if (GlueVal.isOperandOf(*UI)) {
382f4a2713aSLionel Sambuc HasGlueUse = true;
383f4a2713aSLionel Sambuc assert(N->getNodeId() == -1 && "Node already inserted!");
384f4a2713aSLionel Sambuc N->setNodeId(NodeSUnit->NodeNum);
385f4a2713aSLionel Sambuc N = *UI;
386f4a2713aSLionel Sambuc if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
387f4a2713aSLionel Sambuc NodeSUnit->isCall = true;
388f4a2713aSLionel Sambuc break;
389f4a2713aSLionel Sambuc }
390f4a2713aSLionel Sambuc if (!HasGlueUse) break;
391f4a2713aSLionel Sambuc }
392f4a2713aSLionel Sambuc
393f4a2713aSLionel Sambuc if (NodeSUnit->isCall)
394f4a2713aSLionel Sambuc CallSUnits.push_back(NodeSUnit);
395f4a2713aSLionel Sambuc
396f4a2713aSLionel Sambuc // Schedule zero-latency TokenFactor below any nodes that may increase the
397f4a2713aSLionel Sambuc // schedule height. Otherwise, ancestors of the TokenFactor may appear to
398f4a2713aSLionel Sambuc // have false stalls.
399f4a2713aSLionel Sambuc if (NI->getOpcode() == ISD::TokenFactor)
400f4a2713aSLionel Sambuc NodeSUnit->isScheduleLow = true;
401f4a2713aSLionel Sambuc
402f4a2713aSLionel Sambuc // If there are glue operands involved, N is now the bottom-most node
403f4a2713aSLionel Sambuc // of the sequence of nodes that are glued together.
404f4a2713aSLionel Sambuc // Update the SUnit.
405f4a2713aSLionel Sambuc NodeSUnit->setNode(N);
406f4a2713aSLionel Sambuc assert(N->getNodeId() == -1 && "Node already inserted!");
407f4a2713aSLionel Sambuc N->setNodeId(NodeSUnit->NodeNum);
408f4a2713aSLionel Sambuc
409f4a2713aSLionel Sambuc // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
410f4a2713aSLionel Sambuc InitNumRegDefsLeft(NodeSUnit);
411f4a2713aSLionel Sambuc
412f4a2713aSLionel Sambuc // Assign the Latency field of NodeSUnit using target-provided information.
413f4a2713aSLionel Sambuc computeLatency(NodeSUnit);
414f4a2713aSLionel Sambuc }
415f4a2713aSLionel Sambuc
416f4a2713aSLionel Sambuc // Find all call operands.
417f4a2713aSLionel Sambuc while (!CallSUnits.empty()) {
418f4a2713aSLionel Sambuc SUnit *SU = CallSUnits.pop_back_val();
419f4a2713aSLionel Sambuc for (const SDNode *SUNode = SU->getNode(); SUNode;
420f4a2713aSLionel Sambuc SUNode = SUNode->getGluedNode()) {
421f4a2713aSLionel Sambuc if (SUNode->getOpcode() != ISD::CopyToReg)
422f4a2713aSLionel Sambuc continue;
423f4a2713aSLionel Sambuc SDNode *SrcN = SUNode->getOperand(2).getNode();
424f4a2713aSLionel Sambuc if (isPassiveNode(SrcN)) continue; // Not scheduled.
425f4a2713aSLionel Sambuc SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
426f4a2713aSLionel Sambuc SrcSU->isCallOp = true;
427f4a2713aSLionel Sambuc }
428f4a2713aSLionel Sambuc }
429f4a2713aSLionel Sambuc }
430f4a2713aSLionel Sambuc
AddSchedEdges()431f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::AddSchedEdges() {
432*0a6a1f1dSLionel Sambuc const TargetSubtargetInfo &ST = MF.getSubtarget();
433f4a2713aSLionel Sambuc
434f4a2713aSLionel Sambuc // Check to see if the scheduler cares about latencies.
435f4a2713aSLionel Sambuc bool UnitLatencies = forceUnitLatencies();
436f4a2713aSLionel Sambuc
437f4a2713aSLionel Sambuc // Pass 2: add the preds, succs, etc.
438f4a2713aSLionel Sambuc for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
439f4a2713aSLionel Sambuc SUnit *SU = &SUnits[su];
440f4a2713aSLionel Sambuc SDNode *MainNode = SU->getNode();
441f4a2713aSLionel Sambuc
442f4a2713aSLionel Sambuc if (MainNode->isMachineOpcode()) {
443f4a2713aSLionel Sambuc unsigned Opc = MainNode->getMachineOpcode();
444f4a2713aSLionel Sambuc const MCInstrDesc &MCID = TII->get(Opc);
445f4a2713aSLionel Sambuc for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
446f4a2713aSLionel Sambuc if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
447f4a2713aSLionel Sambuc SU->isTwoAddress = true;
448f4a2713aSLionel Sambuc break;
449f4a2713aSLionel Sambuc }
450f4a2713aSLionel Sambuc }
451f4a2713aSLionel Sambuc if (MCID.isCommutable())
452f4a2713aSLionel Sambuc SU->isCommutable = true;
453f4a2713aSLionel Sambuc }
454f4a2713aSLionel Sambuc
455f4a2713aSLionel Sambuc // Find all predecessors and successors of the group.
456f4a2713aSLionel Sambuc for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
457f4a2713aSLionel Sambuc if (N->isMachineOpcode() &&
458f4a2713aSLionel Sambuc TII->get(N->getMachineOpcode()).getImplicitDefs()) {
459f4a2713aSLionel Sambuc SU->hasPhysRegClobbers = true;
460f4a2713aSLionel Sambuc unsigned NumUsed = InstrEmitter::CountResults(N);
461f4a2713aSLionel Sambuc while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
462f4a2713aSLionel Sambuc --NumUsed; // Skip over unused values at the end.
463f4a2713aSLionel Sambuc if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
464f4a2713aSLionel Sambuc SU->hasPhysRegDefs = true;
465f4a2713aSLionel Sambuc }
466f4a2713aSLionel Sambuc
467f4a2713aSLionel Sambuc for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
468f4a2713aSLionel Sambuc SDNode *OpN = N->getOperand(i).getNode();
469f4a2713aSLionel Sambuc if (isPassiveNode(OpN)) continue; // Not scheduled.
470f4a2713aSLionel Sambuc SUnit *OpSU = &SUnits[OpN->getNodeId()];
471f4a2713aSLionel Sambuc assert(OpSU && "Node has no SUnit!");
472f4a2713aSLionel Sambuc if (OpSU == SU) continue; // In the same group.
473f4a2713aSLionel Sambuc
474f4a2713aSLionel Sambuc EVT OpVT = N->getOperand(i).getValueType();
475f4a2713aSLionel Sambuc assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
476f4a2713aSLionel Sambuc bool isChain = OpVT == MVT::Other;
477f4a2713aSLionel Sambuc
478f4a2713aSLionel Sambuc unsigned PhysReg = 0;
479f4a2713aSLionel Sambuc int Cost = 1;
480f4a2713aSLionel Sambuc // Determine if this is a physical register dependency.
481f4a2713aSLionel Sambuc CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
482f4a2713aSLionel Sambuc assert((PhysReg == 0 || !isChain) &&
483f4a2713aSLionel Sambuc "Chain dependence via physreg data?");
484f4a2713aSLionel Sambuc // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
485f4a2713aSLionel Sambuc // emits a copy from the physical register to a virtual register unless
486f4a2713aSLionel Sambuc // it requires a cross class copy (cost < 0). That means we are only
487f4a2713aSLionel Sambuc // treating "expensive to copy" register dependency as physical register
488f4a2713aSLionel Sambuc // dependency. This may change in the future though.
489f4a2713aSLionel Sambuc if (Cost >= 0 && !StressSched)
490f4a2713aSLionel Sambuc PhysReg = 0;
491f4a2713aSLionel Sambuc
492f4a2713aSLionel Sambuc // If this is a ctrl dep, latency is 1.
493f4a2713aSLionel Sambuc unsigned OpLatency = isChain ? 1 : OpSU->Latency;
494f4a2713aSLionel Sambuc // Special-case TokenFactor chains as zero-latency.
495f4a2713aSLionel Sambuc if(isChain && OpN->getOpcode() == ISD::TokenFactor)
496f4a2713aSLionel Sambuc OpLatency = 0;
497f4a2713aSLionel Sambuc
498f4a2713aSLionel Sambuc SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
499f4a2713aSLionel Sambuc : SDep(OpSU, SDep::Data, PhysReg);
500f4a2713aSLionel Sambuc Dep.setLatency(OpLatency);
501f4a2713aSLionel Sambuc if (!isChain && !UnitLatencies) {
502f4a2713aSLionel Sambuc computeOperandLatency(OpN, N, i, Dep);
503f4a2713aSLionel Sambuc ST.adjustSchedDependency(OpSU, SU, Dep);
504f4a2713aSLionel Sambuc }
505f4a2713aSLionel Sambuc
506f4a2713aSLionel Sambuc if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
507f4a2713aSLionel Sambuc // Multiple register uses are combined in the same SUnit. For example,
508f4a2713aSLionel Sambuc // we could have a set of glued nodes with all their defs consumed by
509f4a2713aSLionel Sambuc // another set of glued nodes. Register pressure tracking sees this as
510f4a2713aSLionel Sambuc // a single use, so to keep pressure balanced we reduce the defs.
511f4a2713aSLionel Sambuc //
512f4a2713aSLionel Sambuc // We can't tell (without more book-keeping) if this results from
513f4a2713aSLionel Sambuc // glued nodes or duplicate operands. As long as we don't reduce
514f4a2713aSLionel Sambuc // NumRegDefsLeft to zero, we handle the common cases well.
515f4a2713aSLionel Sambuc --OpSU->NumRegDefsLeft;
516f4a2713aSLionel Sambuc }
517f4a2713aSLionel Sambuc }
518f4a2713aSLionel Sambuc }
519f4a2713aSLionel Sambuc }
520f4a2713aSLionel Sambuc }
521f4a2713aSLionel Sambuc
522f4a2713aSLionel Sambuc /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
523f4a2713aSLionel Sambuc /// are input. This SUnit graph is similar to the SelectionDAG, but
524f4a2713aSLionel Sambuc /// excludes nodes that aren't interesting to scheduling, and represents
525f4a2713aSLionel Sambuc /// glued together nodes with a single SUnit.
BuildSchedGraph(AliasAnalysis * AA)526f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
527f4a2713aSLionel Sambuc // Cluster certain nodes which should be scheduled together.
528f4a2713aSLionel Sambuc ClusterNodes();
529f4a2713aSLionel Sambuc // Populate the SUnits array.
530f4a2713aSLionel Sambuc BuildSchedUnits();
531f4a2713aSLionel Sambuc // Compute all the scheduling dependencies between nodes.
532f4a2713aSLionel Sambuc AddSchedEdges();
533f4a2713aSLionel Sambuc }
534f4a2713aSLionel Sambuc
535f4a2713aSLionel Sambuc // Initialize NumNodeDefs for the current Node's opcode.
InitNodeNumDefs()536f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
537f4a2713aSLionel Sambuc // Check for phys reg copy.
538f4a2713aSLionel Sambuc if (!Node)
539f4a2713aSLionel Sambuc return;
540f4a2713aSLionel Sambuc
541f4a2713aSLionel Sambuc if (!Node->isMachineOpcode()) {
542f4a2713aSLionel Sambuc if (Node->getOpcode() == ISD::CopyFromReg)
543f4a2713aSLionel Sambuc NodeNumDefs = 1;
544f4a2713aSLionel Sambuc else
545f4a2713aSLionel Sambuc NodeNumDefs = 0;
546f4a2713aSLionel Sambuc return;
547f4a2713aSLionel Sambuc }
548f4a2713aSLionel Sambuc unsigned POpc = Node->getMachineOpcode();
549f4a2713aSLionel Sambuc if (POpc == TargetOpcode::IMPLICIT_DEF) {
550f4a2713aSLionel Sambuc // No register need be allocated for this.
551f4a2713aSLionel Sambuc NodeNumDefs = 0;
552f4a2713aSLionel Sambuc return;
553f4a2713aSLionel Sambuc }
554*0a6a1f1dSLionel Sambuc if (POpc == TargetOpcode::PATCHPOINT &&
555*0a6a1f1dSLionel Sambuc Node->getValueType(0) == MVT::Other) {
556*0a6a1f1dSLionel Sambuc // PATCHPOINT is defined to have one result, but it might really have none
557*0a6a1f1dSLionel Sambuc // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
558*0a6a1f1dSLionel Sambuc // real definition.
559*0a6a1f1dSLionel Sambuc NodeNumDefs = 0;
560*0a6a1f1dSLionel Sambuc return;
561*0a6a1f1dSLionel Sambuc }
562f4a2713aSLionel Sambuc unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
563f4a2713aSLionel Sambuc // Some instructions define regs that are not represented in the selection DAG
564f4a2713aSLionel Sambuc // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
565f4a2713aSLionel Sambuc NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
566f4a2713aSLionel Sambuc DefIdx = 0;
567f4a2713aSLionel Sambuc }
568f4a2713aSLionel Sambuc
569f4a2713aSLionel Sambuc // Construct a RegDefIter for this SUnit and find the first valid value.
RegDefIter(const SUnit * SU,const ScheduleDAGSDNodes * SD)570f4a2713aSLionel Sambuc ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
571f4a2713aSLionel Sambuc const ScheduleDAGSDNodes *SD)
572f4a2713aSLionel Sambuc : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
573f4a2713aSLionel Sambuc InitNodeNumDefs();
574f4a2713aSLionel Sambuc Advance();
575f4a2713aSLionel Sambuc }
576f4a2713aSLionel Sambuc
577f4a2713aSLionel Sambuc // Advance to the next valid value defined by the SUnit.
Advance()578f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::RegDefIter::Advance() {
579f4a2713aSLionel Sambuc for (;Node;) { // Visit all glued nodes.
580f4a2713aSLionel Sambuc for (;DefIdx < NodeNumDefs; ++DefIdx) {
581f4a2713aSLionel Sambuc if (!Node->hasAnyUseOfValue(DefIdx))
582f4a2713aSLionel Sambuc continue;
583f4a2713aSLionel Sambuc ValueType = Node->getSimpleValueType(DefIdx);
584f4a2713aSLionel Sambuc ++DefIdx;
585f4a2713aSLionel Sambuc return; // Found a normal regdef.
586f4a2713aSLionel Sambuc }
587f4a2713aSLionel Sambuc Node = Node->getGluedNode();
588*0a6a1f1dSLionel Sambuc if (!Node) {
589f4a2713aSLionel Sambuc return; // No values left to visit.
590f4a2713aSLionel Sambuc }
591f4a2713aSLionel Sambuc InitNodeNumDefs();
592f4a2713aSLionel Sambuc }
593f4a2713aSLionel Sambuc }
594f4a2713aSLionel Sambuc
InitNumRegDefsLeft(SUnit * SU)595f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
596f4a2713aSLionel Sambuc assert(SU->NumRegDefsLeft == 0 && "expect a new node");
597f4a2713aSLionel Sambuc for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
598f4a2713aSLionel Sambuc assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
599f4a2713aSLionel Sambuc ++SU->NumRegDefsLeft;
600f4a2713aSLionel Sambuc }
601f4a2713aSLionel Sambuc }
602f4a2713aSLionel Sambuc
computeLatency(SUnit * SU)603f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
604f4a2713aSLionel Sambuc SDNode *N = SU->getNode();
605f4a2713aSLionel Sambuc
606f4a2713aSLionel Sambuc // TokenFactor operands are considered zero latency, and some schedulers
607f4a2713aSLionel Sambuc // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
608f4a2713aSLionel Sambuc // whenever node latency is nonzero.
609f4a2713aSLionel Sambuc if (N && N->getOpcode() == ISD::TokenFactor) {
610f4a2713aSLionel Sambuc SU->Latency = 0;
611f4a2713aSLionel Sambuc return;
612f4a2713aSLionel Sambuc }
613f4a2713aSLionel Sambuc
614f4a2713aSLionel Sambuc // Check to see if the scheduler cares about latencies.
615f4a2713aSLionel Sambuc if (forceUnitLatencies()) {
616f4a2713aSLionel Sambuc SU->Latency = 1;
617f4a2713aSLionel Sambuc return;
618f4a2713aSLionel Sambuc }
619f4a2713aSLionel Sambuc
620f4a2713aSLionel Sambuc if (!InstrItins || InstrItins->isEmpty()) {
621f4a2713aSLionel Sambuc if (N && N->isMachineOpcode() &&
622f4a2713aSLionel Sambuc TII->isHighLatencyDef(N->getMachineOpcode()))
623f4a2713aSLionel Sambuc SU->Latency = HighLatencyCycles;
624f4a2713aSLionel Sambuc else
625f4a2713aSLionel Sambuc SU->Latency = 1;
626f4a2713aSLionel Sambuc return;
627f4a2713aSLionel Sambuc }
628f4a2713aSLionel Sambuc
629f4a2713aSLionel Sambuc // Compute the latency for the node. We use the sum of the latencies for
630f4a2713aSLionel Sambuc // all nodes glued together into this SUnit.
631f4a2713aSLionel Sambuc SU->Latency = 0;
632f4a2713aSLionel Sambuc for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
633f4a2713aSLionel Sambuc if (N->isMachineOpcode())
634f4a2713aSLionel Sambuc SU->Latency += TII->getInstrLatency(InstrItins, N);
635f4a2713aSLionel Sambuc }
636f4a2713aSLionel Sambuc
computeOperandLatency(SDNode * Def,SDNode * Use,unsigned OpIdx,SDep & dep) const637f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
638f4a2713aSLionel Sambuc unsigned OpIdx, SDep& dep) const{
639f4a2713aSLionel Sambuc // Check to see if the scheduler cares about latencies.
640f4a2713aSLionel Sambuc if (forceUnitLatencies())
641f4a2713aSLionel Sambuc return;
642f4a2713aSLionel Sambuc
643f4a2713aSLionel Sambuc if (dep.getKind() != SDep::Data)
644f4a2713aSLionel Sambuc return;
645f4a2713aSLionel Sambuc
646f4a2713aSLionel Sambuc unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
647f4a2713aSLionel Sambuc if (Use->isMachineOpcode())
648f4a2713aSLionel Sambuc // Adjust the use operand index by num of defs.
649f4a2713aSLionel Sambuc OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
650f4a2713aSLionel Sambuc int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
651f4a2713aSLionel Sambuc if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
652f4a2713aSLionel Sambuc !BB->succ_empty()) {
653f4a2713aSLionel Sambuc unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
654f4a2713aSLionel Sambuc if (TargetRegisterInfo::isVirtualRegister(Reg))
655f4a2713aSLionel Sambuc // This copy is a liveout value. It is likely coalesced, so reduce the
656f4a2713aSLionel Sambuc // latency so not to penalize the def.
657f4a2713aSLionel Sambuc // FIXME: need target specific adjustment here?
658f4a2713aSLionel Sambuc Latency = (Latency > 1) ? Latency - 1 : 1;
659f4a2713aSLionel Sambuc }
660f4a2713aSLionel Sambuc if (Latency >= 0)
661f4a2713aSLionel Sambuc dep.setLatency(Latency);
662f4a2713aSLionel Sambuc }
663f4a2713aSLionel Sambuc
dumpNode(const SUnit * SU) const664f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
665f4a2713aSLionel Sambuc #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
666f4a2713aSLionel Sambuc if (!SU->getNode()) {
667f4a2713aSLionel Sambuc dbgs() << "PHYS REG COPY\n";
668f4a2713aSLionel Sambuc return;
669f4a2713aSLionel Sambuc }
670f4a2713aSLionel Sambuc
671f4a2713aSLionel Sambuc SU->getNode()->dump(DAG);
672f4a2713aSLionel Sambuc dbgs() << "\n";
673f4a2713aSLionel Sambuc SmallVector<SDNode *, 4> GluedNodes;
674f4a2713aSLionel Sambuc for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
675f4a2713aSLionel Sambuc GluedNodes.push_back(N);
676f4a2713aSLionel Sambuc while (!GluedNodes.empty()) {
677f4a2713aSLionel Sambuc dbgs() << " ";
678f4a2713aSLionel Sambuc GluedNodes.back()->dump(DAG);
679f4a2713aSLionel Sambuc dbgs() << "\n";
680f4a2713aSLionel Sambuc GluedNodes.pop_back();
681f4a2713aSLionel Sambuc }
682f4a2713aSLionel Sambuc #endif
683f4a2713aSLionel Sambuc }
684f4a2713aSLionel Sambuc
685f4a2713aSLionel Sambuc #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dumpSchedule() const686f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::dumpSchedule() const {
687f4a2713aSLionel Sambuc for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
688f4a2713aSLionel Sambuc if (SUnit *SU = Sequence[i])
689f4a2713aSLionel Sambuc SU->dump(this);
690f4a2713aSLionel Sambuc else
691f4a2713aSLionel Sambuc dbgs() << "**** NOOP ****\n";
692f4a2713aSLionel Sambuc }
693f4a2713aSLionel Sambuc }
694f4a2713aSLionel Sambuc #endif
695f4a2713aSLionel Sambuc
696f4a2713aSLionel Sambuc #ifndef NDEBUG
697f4a2713aSLionel Sambuc /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
698f4a2713aSLionel Sambuc /// their state is consistent with the nodes listed in Sequence.
699f4a2713aSLionel Sambuc ///
VerifyScheduledSequence(bool isBottomUp)700f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
701f4a2713aSLionel Sambuc unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
702f4a2713aSLionel Sambuc unsigned Noops = 0;
703f4a2713aSLionel Sambuc for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
704f4a2713aSLionel Sambuc if (!Sequence[i])
705f4a2713aSLionel Sambuc ++Noops;
706f4a2713aSLionel Sambuc assert(Sequence.size() - Noops == ScheduledNodes &&
707f4a2713aSLionel Sambuc "The number of nodes scheduled doesn't match the expected number!");
708f4a2713aSLionel Sambuc }
709f4a2713aSLionel Sambuc #endif // NDEBUG
710f4a2713aSLionel Sambuc
711f4a2713aSLionel Sambuc /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
712f4a2713aSLionel Sambuc static void
ProcessSDDbgValues(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,DenseMap<SDValue,unsigned> & VRBaseMap,unsigned Order)713f4a2713aSLionel Sambuc ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
714f4a2713aSLionel Sambuc SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
715f4a2713aSLionel Sambuc DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
716f4a2713aSLionel Sambuc if (!N->getHasDebugValue())
717f4a2713aSLionel Sambuc return;
718f4a2713aSLionel Sambuc
719f4a2713aSLionel Sambuc // Opportunistically insert immediate dbg_value uses, i.e. those with source
720f4a2713aSLionel Sambuc // order number right after the N.
721f4a2713aSLionel Sambuc MachineBasicBlock *BB = Emitter.getBlock();
722f4a2713aSLionel Sambuc MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
723f4a2713aSLionel Sambuc ArrayRef<SDDbgValue*> DVs = DAG->GetDbgValues(N);
724f4a2713aSLionel Sambuc for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
725f4a2713aSLionel Sambuc if (DVs[i]->isInvalidated())
726f4a2713aSLionel Sambuc continue;
727f4a2713aSLionel Sambuc unsigned DVOrder = DVs[i]->getOrder();
728f4a2713aSLionel Sambuc if (!Order || DVOrder == ++Order) {
729f4a2713aSLionel Sambuc MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
730f4a2713aSLionel Sambuc if (DbgMI) {
731f4a2713aSLionel Sambuc Orders.push_back(std::make_pair(DVOrder, DbgMI));
732f4a2713aSLionel Sambuc BB->insert(InsertPos, DbgMI);
733f4a2713aSLionel Sambuc }
734f4a2713aSLionel Sambuc DVs[i]->setIsInvalidated();
735f4a2713aSLionel Sambuc }
736f4a2713aSLionel Sambuc }
737f4a2713aSLionel Sambuc }
738f4a2713aSLionel Sambuc
739f4a2713aSLionel Sambuc // ProcessSourceNode - Process nodes with source order numbers. These are added
740f4a2713aSLionel Sambuc // to a vector which EmitSchedule uses to determine how to insert dbg_value
741f4a2713aSLionel Sambuc // instructions in the right order.
742f4a2713aSLionel Sambuc static void
ProcessSourceNode(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,DenseMap<SDValue,unsigned> & VRBaseMap,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,SmallSet<unsigned,8> & Seen)743f4a2713aSLionel Sambuc ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
744f4a2713aSLionel Sambuc DenseMap<SDValue, unsigned> &VRBaseMap,
745f4a2713aSLionel Sambuc SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
746f4a2713aSLionel Sambuc SmallSet<unsigned, 8> &Seen) {
747f4a2713aSLionel Sambuc unsigned Order = N->getIROrder();
748*0a6a1f1dSLionel Sambuc if (!Order || !Seen.insert(Order).second) {
749f4a2713aSLionel Sambuc // Process any valid SDDbgValues even if node does not have any order
750f4a2713aSLionel Sambuc // assigned.
751f4a2713aSLionel Sambuc ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
752f4a2713aSLionel Sambuc return;
753f4a2713aSLionel Sambuc }
754f4a2713aSLionel Sambuc
755f4a2713aSLionel Sambuc MachineBasicBlock *BB = Emitter.getBlock();
756f4a2713aSLionel Sambuc if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI() ||
757f4a2713aSLionel Sambuc // Fast-isel may have inserted some instructions, in which case the
758f4a2713aSLionel Sambuc // BB->back().isPHI() test will not fire when we want it to.
759*0a6a1f1dSLionel Sambuc std::prev(Emitter.getInsertPos())->isPHI()) {
760f4a2713aSLionel Sambuc // Did not insert any instruction.
761*0a6a1f1dSLionel Sambuc Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr));
762f4a2713aSLionel Sambuc return;
763f4a2713aSLionel Sambuc }
764f4a2713aSLionel Sambuc
765*0a6a1f1dSLionel Sambuc Orders.push_back(std::make_pair(Order, std::prev(Emitter.getInsertPos())));
766f4a2713aSLionel Sambuc ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
767f4a2713aSLionel Sambuc }
768f4a2713aSLionel Sambuc
769f4a2713aSLionel Sambuc void ScheduleDAGSDNodes::
EmitPhysRegCopy(SUnit * SU,DenseMap<SUnit *,unsigned> & VRBaseMap,MachineBasicBlock::iterator InsertPos)770f4a2713aSLionel Sambuc EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
771f4a2713aSLionel Sambuc MachineBasicBlock::iterator InsertPos) {
772f4a2713aSLionel Sambuc for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
773f4a2713aSLionel Sambuc I != E; ++I) {
774f4a2713aSLionel Sambuc if (I->isCtrl()) continue; // ignore chain preds
775f4a2713aSLionel Sambuc if (I->getSUnit()->CopyDstRC) {
776f4a2713aSLionel Sambuc // Copy to physical register.
777f4a2713aSLionel Sambuc DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
778f4a2713aSLionel Sambuc assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
779f4a2713aSLionel Sambuc // Find the destination physical register.
780f4a2713aSLionel Sambuc unsigned Reg = 0;
781f4a2713aSLionel Sambuc for (SUnit::const_succ_iterator II = SU->Succs.begin(),
782f4a2713aSLionel Sambuc EE = SU->Succs.end(); II != EE; ++II) {
783f4a2713aSLionel Sambuc if (II->isCtrl()) continue; // ignore chain preds
784f4a2713aSLionel Sambuc if (II->getReg()) {
785f4a2713aSLionel Sambuc Reg = II->getReg();
786f4a2713aSLionel Sambuc break;
787f4a2713aSLionel Sambuc }
788f4a2713aSLionel Sambuc }
789f4a2713aSLionel Sambuc BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
790f4a2713aSLionel Sambuc .addReg(VRI->second);
791f4a2713aSLionel Sambuc } else {
792f4a2713aSLionel Sambuc // Copy from physical register.
793f4a2713aSLionel Sambuc assert(I->getReg() && "Unknown physical register!");
794f4a2713aSLionel Sambuc unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
795f4a2713aSLionel Sambuc bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
796f4a2713aSLionel Sambuc (void)isNew; // Silence compiler warning.
797f4a2713aSLionel Sambuc assert(isNew && "Node emitted out of order - early");
798f4a2713aSLionel Sambuc BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
799f4a2713aSLionel Sambuc .addReg(I->getReg());
800f4a2713aSLionel Sambuc }
801f4a2713aSLionel Sambuc break;
802f4a2713aSLionel Sambuc }
803f4a2713aSLionel Sambuc }
804f4a2713aSLionel Sambuc
805f4a2713aSLionel Sambuc /// EmitSchedule - Emit the machine code in scheduled order. Return the new
806f4a2713aSLionel Sambuc /// InsertPos and MachineBasicBlock that contains this insertion
807f4a2713aSLionel Sambuc /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
808f4a2713aSLionel Sambuc /// not necessarily refer to returned BB. The emitter may split blocks.
809f4a2713aSLionel Sambuc MachineBasicBlock *ScheduleDAGSDNodes::
EmitSchedule(MachineBasicBlock::iterator & InsertPos)810f4a2713aSLionel Sambuc EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
811f4a2713aSLionel Sambuc InstrEmitter Emitter(BB, InsertPos);
812f4a2713aSLionel Sambuc DenseMap<SDValue, unsigned> VRBaseMap;
813f4a2713aSLionel Sambuc DenseMap<SUnit*, unsigned> CopyVRBaseMap;
814f4a2713aSLionel Sambuc SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
815f4a2713aSLionel Sambuc SmallSet<unsigned, 8> Seen;
816f4a2713aSLionel Sambuc bool HasDbg = DAG->hasDebugValues();
817f4a2713aSLionel Sambuc
818f4a2713aSLionel Sambuc // If this is the first BB, emit byval parameter dbg_value's.
819f4a2713aSLionel Sambuc if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
820f4a2713aSLionel Sambuc SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
821f4a2713aSLionel Sambuc SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
822f4a2713aSLionel Sambuc for (; PDI != PDE; ++PDI) {
823f4a2713aSLionel Sambuc MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
824f4a2713aSLionel Sambuc if (DbgMI)
825f4a2713aSLionel Sambuc BB->insert(InsertPos, DbgMI);
826f4a2713aSLionel Sambuc }
827f4a2713aSLionel Sambuc }
828f4a2713aSLionel Sambuc
829f4a2713aSLionel Sambuc for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
830f4a2713aSLionel Sambuc SUnit *SU = Sequence[i];
831f4a2713aSLionel Sambuc if (!SU) {
832f4a2713aSLionel Sambuc // Null SUnit* is a noop.
833f4a2713aSLionel Sambuc TII->insertNoop(*Emitter.getBlock(), InsertPos);
834f4a2713aSLionel Sambuc continue;
835f4a2713aSLionel Sambuc }
836f4a2713aSLionel Sambuc
837f4a2713aSLionel Sambuc // For pre-regalloc scheduling, create instructions corresponding to the
838f4a2713aSLionel Sambuc // SDNode and any glued SDNodes and append them to the block.
839f4a2713aSLionel Sambuc if (!SU->getNode()) {
840f4a2713aSLionel Sambuc // Emit a copy.
841f4a2713aSLionel Sambuc EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
842f4a2713aSLionel Sambuc continue;
843f4a2713aSLionel Sambuc }
844f4a2713aSLionel Sambuc
845f4a2713aSLionel Sambuc SmallVector<SDNode *, 4> GluedNodes;
846f4a2713aSLionel Sambuc for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
847f4a2713aSLionel Sambuc GluedNodes.push_back(N);
848f4a2713aSLionel Sambuc while (!GluedNodes.empty()) {
849f4a2713aSLionel Sambuc SDNode *N = GluedNodes.back();
850f4a2713aSLionel Sambuc Emitter.EmitNode(GluedNodes.back(), SU->OrigNode != SU, SU->isCloned,
851f4a2713aSLionel Sambuc VRBaseMap);
852f4a2713aSLionel Sambuc // Remember the source order of the inserted instruction.
853f4a2713aSLionel Sambuc if (HasDbg)
854f4a2713aSLionel Sambuc ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
855f4a2713aSLionel Sambuc GluedNodes.pop_back();
856f4a2713aSLionel Sambuc }
857f4a2713aSLionel Sambuc Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
858f4a2713aSLionel Sambuc VRBaseMap);
859f4a2713aSLionel Sambuc // Remember the source order of the inserted instruction.
860f4a2713aSLionel Sambuc if (HasDbg)
861f4a2713aSLionel Sambuc ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
862f4a2713aSLionel Sambuc Seen);
863f4a2713aSLionel Sambuc }
864f4a2713aSLionel Sambuc
865f4a2713aSLionel Sambuc // Insert all the dbg_values which have not already been inserted in source
866f4a2713aSLionel Sambuc // order sequence.
867f4a2713aSLionel Sambuc if (HasDbg) {
868f4a2713aSLionel Sambuc MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
869f4a2713aSLionel Sambuc
870f4a2713aSLionel Sambuc // Sort the source order instructions and use the order to insert debug
871f4a2713aSLionel Sambuc // values.
872f4a2713aSLionel Sambuc std::sort(Orders.begin(), Orders.end(), less_first());
873f4a2713aSLionel Sambuc
874f4a2713aSLionel Sambuc SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
875f4a2713aSLionel Sambuc SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
876f4a2713aSLionel Sambuc // Now emit the rest according to source order.
877f4a2713aSLionel Sambuc unsigned LastOrder = 0;
878f4a2713aSLionel Sambuc for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
879f4a2713aSLionel Sambuc unsigned Order = Orders[i].first;
880f4a2713aSLionel Sambuc MachineInstr *MI = Orders[i].second;
881f4a2713aSLionel Sambuc // Insert all SDDbgValue's whose order(s) are before "Order".
882f4a2713aSLionel Sambuc if (!MI)
883f4a2713aSLionel Sambuc continue;
884f4a2713aSLionel Sambuc for (; DI != DE &&
885f4a2713aSLionel Sambuc (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
886f4a2713aSLionel Sambuc if ((*DI)->isInvalidated())
887f4a2713aSLionel Sambuc continue;
888f4a2713aSLionel Sambuc MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
889f4a2713aSLionel Sambuc if (DbgMI) {
890f4a2713aSLionel Sambuc if (!LastOrder)
891f4a2713aSLionel Sambuc // Insert to start of the BB (after PHIs).
892f4a2713aSLionel Sambuc BB->insert(BBBegin, DbgMI);
893f4a2713aSLionel Sambuc else {
894f4a2713aSLionel Sambuc // Insert at the instruction, which may be in a different
895f4a2713aSLionel Sambuc // block, if the block was split by a custom inserter.
896f4a2713aSLionel Sambuc MachineBasicBlock::iterator Pos = MI;
897f4a2713aSLionel Sambuc MI->getParent()->insert(Pos, DbgMI);
898f4a2713aSLionel Sambuc }
899f4a2713aSLionel Sambuc }
900f4a2713aSLionel Sambuc }
901f4a2713aSLionel Sambuc LastOrder = Order;
902f4a2713aSLionel Sambuc }
903f4a2713aSLionel Sambuc // Add trailing DbgValue's before the terminator. FIXME: May want to add
904f4a2713aSLionel Sambuc // some of them before one or more conditional branches?
905f4a2713aSLionel Sambuc SmallVector<MachineInstr*, 8> DbgMIs;
906f4a2713aSLionel Sambuc while (DI != DE) {
907f4a2713aSLionel Sambuc if (!(*DI)->isInvalidated())
908f4a2713aSLionel Sambuc if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
909f4a2713aSLionel Sambuc DbgMIs.push_back(DbgMI);
910f4a2713aSLionel Sambuc ++DI;
911f4a2713aSLionel Sambuc }
912f4a2713aSLionel Sambuc
913f4a2713aSLionel Sambuc MachineBasicBlock *InsertBB = Emitter.getBlock();
914f4a2713aSLionel Sambuc MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
915f4a2713aSLionel Sambuc InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
916f4a2713aSLionel Sambuc }
917f4a2713aSLionel Sambuc
918f4a2713aSLionel Sambuc InsertPos = Emitter.getInsertPos();
919f4a2713aSLionel Sambuc return Emitter.getBlock();
920f4a2713aSLionel Sambuc }
921f4a2713aSLionel Sambuc
922f4a2713aSLionel Sambuc /// Return the basic block label.
getDAGName() const923f4a2713aSLionel Sambuc std::string ScheduleDAGSDNodes::getDAGName() const {
924f4a2713aSLionel Sambuc return "sunit-dag." + BB->getFullName();
925f4a2713aSLionel Sambuc }
926