1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AArch64.h"
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/RegAllocRegistry.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
24 using namespace llvm;
25
26 static cl::opt<bool>
27 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
28 cl::init(true), cl::Hidden);
29
30 static cl::opt<bool> EnableMCR("aarch64-mcr",
31 cl::desc("Enable the machine combiner pass"),
32 cl::init(true), cl::Hidden);
33
34 static cl::opt<bool>
35 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
36 cl::init(true), cl::Hidden);
37
38 static cl::opt<bool>
39 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
40 " integer instructions"), cl::init(false), cl::Hidden);
41
42 static cl::opt<bool>
43 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
44 "constant pass"), cl::init(true), cl::Hidden);
45
46 static cl::opt<bool>
47 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
48 " linker optimization hints (LOH)"), cl::init(true),
49 cl::Hidden);
50
51 static cl::opt<bool>
52 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
53 cl::desc("Enable the pass that removes dead"
54 " definitons and replaces stores to"
55 " them with stores to the zero"
56 " register"),
57 cl::init(true));
58
59 static cl::opt<bool>
60 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
61 " optimization pass"), cl::init(true), cl::Hidden);
62
63 static cl::opt<bool>
64 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
65 cl::desc("Run SimplifyCFG after expanding atomic operations"
66 " to make use of cmpxchg flow-based information"),
67 cl::init(true));
68
69 static cl::opt<bool>
70 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
71 cl::desc("Run early if-conversion"),
72 cl::init(true));
73
74 static cl::opt<bool>
75 EnableCondOpt("aarch64-condopt",
76 cl::desc("Enable the condition optimizer pass"),
77 cl::init(true), cl::Hidden);
78
79 static cl::opt<bool>
80 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
81 cl::desc("Work around Cortex-A53 erratum 835769"),
82 cl::init(false));
83
84 static cl::opt<bool>
85 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
86 cl::desc("Enable optimizations on complex GEPs"),
87 cl::init(true));
88
LLVMInitializeAArch64Target()89 extern "C" void LLVMInitializeAArch64Target() {
90 // Register the target.
91 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
92 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
93 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
94 }
95
96 //===----------------------------------------------------------------------===//
97 // AArch64 Lowering public interface.
98 //===----------------------------------------------------------------------===//
createTLOF(const Triple & TT)99 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
100 if (TT.isOSBinFormatMachO())
101 return make_unique<AArch64_MachoTargetObjectFile>();
102
103 return make_unique<AArch64_ELFTargetObjectFile>();
104 }
105
106 /// TargetMachine ctor - Create an AArch64 architecture model.
107 ///
AArch64TargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL,bool LittleEndian)108 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
109 StringRef CPU, StringRef FS,
110 const TargetOptions &Options,
111 Reloc::Model RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL,
113 bool LittleEndian)
114 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
115 TLOF(createTLOF(Triple(getTargetTriple()))),
116 Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
117 initAsmInfo();
118 }
119
~AArch64TargetMachine()120 AArch64TargetMachine::~AArch64TargetMachine() {}
121
122 const AArch64Subtarget *
getSubtargetImpl(const Function & F) const123 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
124 AttributeSet FnAttrs = F.getAttributes();
125 Attribute CPUAttr =
126 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
127 Attribute FSAttr =
128 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
129
130 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
131 ? CPUAttr.getValueAsString().str()
132 : TargetCPU;
133 std::string FS = !FSAttr.hasAttribute(Attribute::None)
134 ? FSAttr.getValueAsString().str()
135 : TargetFS;
136
137 auto &I = SubtargetMap[CPU + FS];
138 if (!I) {
139 // This needs to be done before we create a new subtarget since any
140 // creation will depend on the TM and the code generation flags on the
141 // function that reside in TargetOptions.
142 resetTargetOptions(F);
143 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
144 }
145 return I.get();
146 }
147
anchor()148 void AArch64leTargetMachine::anchor() { }
149
150 AArch64leTargetMachine::
AArch64leTargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)151 AArch64leTargetMachine(const Target &T, StringRef TT,
152 StringRef CPU, StringRef FS, const TargetOptions &Options,
153 Reloc::Model RM, CodeModel::Model CM,
154 CodeGenOpt::Level OL)
155 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
156
anchor()157 void AArch64beTargetMachine::anchor() { }
158
159 AArch64beTargetMachine::
AArch64beTargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)160 AArch64beTargetMachine(const Target &T, StringRef TT,
161 StringRef CPU, StringRef FS, const TargetOptions &Options,
162 Reloc::Model RM, CodeModel::Model CM,
163 CodeGenOpt::Level OL)
164 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
165
166 namespace {
167 /// AArch64 Code Generator Pass Configuration Options.
168 class AArch64PassConfig : public TargetPassConfig {
169 public:
AArch64PassConfig(AArch64TargetMachine * TM,PassManagerBase & PM)170 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
171 : TargetPassConfig(TM, PM) {
172 if (TM->getOptLevel() != CodeGenOpt::None)
173 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
174 }
175
getAArch64TargetMachine() const176 AArch64TargetMachine &getAArch64TargetMachine() const {
177 return getTM<AArch64TargetMachine>();
178 }
179
180 void addIRPasses() override;
181 bool addPreISel() override;
182 bool addInstSelector() override;
183 bool addILPOpts() override;
184 void addPreRegAlloc() override;
185 void addPostRegAlloc() override;
186 void addPreSched2() override;
187 void addPreEmitPass() override;
188 };
189 } // namespace
190
addAnalysisPasses(PassManagerBase & PM)191 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
192 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
193 // allows the AArch64 pass to delegate to the target independent layer when
194 // appropriate.
195 PM.add(createBasicTargetTransformInfoPass(this));
196 PM.add(createAArch64TargetTransformInfoPass(this));
197 }
198
createPassConfig(PassManagerBase & PM)199 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
200 return new AArch64PassConfig(this, PM);
201 }
202
addIRPasses()203 void AArch64PassConfig::addIRPasses() {
204 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
205 // ourselves.
206 addPass(createAtomicExpandPass(TM));
207
208 // Cmpxchg instructions are often used with a subsequent comparison to
209 // determine whether it succeeded. We can exploit existing control-flow in
210 // ldrex/strex loops to simplify this, but it needs tidying up.
211 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
212 addPass(createCFGSimplificationPass());
213
214 TargetPassConfig::addIRPasses();
215
216 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
217 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
218 // and lower a GEP with multiple indices to either arithmetic operations or
219 // multiple GEPs with single index.
220 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
221 // Call EarlyCSE pass to find and remove subexpressions in the lowered
222 // result.
223 addPass(createEarlyCSEPass());
224 // Do loop invariant code motion in case part of the lowered result is
225 // invariant.
226 addPass(createLICMPass());
227 }
228 }
229
230 // Pass Pipeline Configuration
addPreISel()231 bool AArch64PassConfig::addPreISel() {
232 // Run promote constant before global merge, so that the promoted constants
233 // get a chance to be merged
234 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
235 addPass(createAArch64PromoteConstantPass());
236 if (TM->getOptLevel() != CodeGenOpt::None)
237 addPass(createGlobalMergePass(TM));
238 if (TM->getOptLevel() != CodeGenOpt::None)
239 addPass(createAArch64AddressTypePromotionPass());
240
241 return false;
242 }
243
addInstSelector()244 bool AArch64PassConfig::addInstSelector() {
245 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
246
247 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
248 // references to _TLS_MODULE_BASE_ as possible.
249 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
250 getOptLevel() != CodeGenOpt::None)
251 addPass(createAArch64CleanupLocalDynamicTLSPass());
252
253 return false;
254 }
255
addILPOpts()256 bool AArch64PassConfig::addILPOpts() {
257 if (EnableCondOpt)
258 addPass(createAArch64ConditionOptimizerPass());
259 if (EnableCCMP)
260 addPass(createAArch64ConditionalCompares());
261 if (EnableMCR)
262 addPass(&MachineCombinerID);
263 if (EnableEarlyIfConversion)
264 addPass(&EarlyIfConverterID);
265 if (EnableStPairSuppress)
266 addPass(createAArch64StorePairSuppressPass());
267 return true;
268 }
269
addPreRegAlloc()270 void AArch64PassConfig::addPreRegAlloc() {
271 // Use AdvSIMD scalar instructions whenever profitable.
272 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
273 addPass(createAArch64AdvSIMDScalar());
274 // The AdvSIMD pass may produce copies that can be rewritten to
275 // be register coaleascer friendly.
276 addPass(&PeepholeOptimizerID);
277 }
278 }
279
addPostRegAlloc()280 void AArch64PassConfig::addPostRegAlloc() {
281 // Change dead register definitions to refer to the zero register.
282 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
283 addPass(createAArch64DeadRegisterDefinitions());
284 if (TM->getOptLevel() != CodeGenOpt::None &&
285 (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
286 TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
287 usingDefaultRegAlloc())
288 // Improve performance for some FP/SIMD code for A57.
289 addPass(createAArch64A57FPLoadBalancing());
290 }
291
addPreSched2()292 void AArch64PassConfig::addPreSched2() {
293 // Expand some pseudo instructions to allow proper scheduling.
294 addPass(createAArch64ExpandPseudoPass());
295 // Use load/store pair instructions when possible.
296 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
297 addPass(createAArch64LoadStoreOptimizationPass());
298 }
299
addPreEmitPass()300 void AArch64PassConfig::addPreEmitPass() {
301 if (EnableA53Fix835769)
302 addPass(createAArch64A53Fix835769());
303 // Relax conditional branch instructions if they're otherwise out of
304 // range of their destination.
305 addPass(createAArch64BranchRelaxation());
306 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
307 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
308 addPass(createAArch64CollectLOHPass());
309 }
310