1//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This describes the calling conventions for ARM architecture.
10//===----------------------------------------------------------------------===//
11
12/// CCIfAlign - Match of the original alignment of the arg
13class CCIfAlign<string Align, CCAction A>:
14  CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
15
16//===----------------------------------------------------------------------===//
17// ARM APCS Calling Convention
18//===----------------------------------------------------------------------===//
19def CC_ARM_APCS : CallingConv<[
20
21  // Handles byval parameters.
22  CCIfByVal<CCPassByVal<4, 4>>,
23
24  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
25
26  // Handle all vector types as either f64 or v2f64.
27  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
28  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
29
30  // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
31  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
32
33  CCIfType<[f32], CCBitConvertToType<i32>>,
34  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
35
36  CCIfType<[i32], CCAssignToStack<4, 4>>,
37  CCIfType<[f64], CCAssignToStack<8, 4>>,
38  CCIfType<[v2f64], CCAssignToStack<16, 4>>
39]>;
40
41def RetCC_ARM_APCS : CallingConv<[
42  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
43  CCIfType<[f32], CCBitConvertToType<i32>>,
44
45  // Handle all vector types as either f64 or v2f64.
46  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
47  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
48
49  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
50
51  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
52  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
53]>;
54
55//===----------------------------------------------------------------------===//
56// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
57//===----------------------------------------------------------------------===//
58def FastCC_ARM_APCS : CallingConv<[
59  // Handle all vector types as either f64 or v2f64.
60  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
61  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
62
63  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
64  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
65  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
66                                 S9, S10, S11, S12, S13, S14, S15]>>,
67  CCDelegateTo<CC_ARM_APCS>
68]>;
69
70def RetFastCC_ARM_APCS : CallingConv<[
71  // Handle all vector types as either f64 or v2f64.
72  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
73  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
74
75  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
76  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
77  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
78                                 S9, S10, S11, S12, S13, S14, S15]>>,
79  CCDelegateTo<RetCC_ARM_APCS>
80]>;
81
82//===----------------------------------------------------------------------===//
83// ARM APCS Calling Convention for GHC
84//===----------------------------------------------------------------------===//
85
86def CC_ARM_APCS_GHC : CallingConv<[
87  // Handle all vector types as either f64 or v2f64.
88  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
89  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
90
91  CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
92  CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
93  CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
94
95  // Promote i8/i16 arguments to i32.
96  CCIfType<[i8, i16], CCPromoteToType<i32>>,
97
98  // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
99  CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
100]>;
101
102//===----------------------------------------------------------------------===//
103// ARM AAPCS (EABI) Calling Convention, common parts
104//===----------------------------------------------------------------------===//
105
106def CC_ARM_AAPCS_Common : CallingConv<[
107
108  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
109
110  // i64/f64 is passed in even pairs of GPRs
111  // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
112  // (and the same is true for f64 if VFP is not enabled)
113  CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
114  CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8",
115                       CCAssignToReg<[R0, R1, R2, R3]>>>,
116
117  CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, R3>>>,
118  CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
119  CCIfType<[f64], CCAssignToStack<8, 8>>,
120  CCIfType<[v2f64], CCAssignToStack<16, 8>>
121]>;
122
123def RetCC_ARM_AAPCS_Common : CallingConv<[
124  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
125  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
126  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
127]>;
128
129//===----------------------------------------------------------------------===//
130// ARM AAPCS (EABI) Calling Convention
131//===----------------------------------------------------------------------===//
132
133def CC_ARM_AAPCS : CallingConv<[
134  // Handles byval parameters.
135  CCIfByVal<CCPassByVal<4, 4>>,
136
137  // Handle all vector types as either f64 or v2f64.
138  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
139  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
140
141  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
142  CCIfType<[f32], CCBitConvertToType<i32>>,
143  CCDelegateTo<CC_ARM_AAPCS_Common>
144]>;
145
146def RetCC_ARM_AAPCS : CallingConv<[
147  // Handle all vector types as either f64 or v2f64.
148  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
149  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
150
151  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
152  CCIfType<[f32], CCBitConvertToType<i32>>,
153  CCDelegateTo<RetCC_ARM_AAPCS_Common>
154]>;
155
156//===----------------------------------------------------------------------===//
157// ARM AAPCS-VFP (EABI) Calling Convention
158// Also used for FastCC (when VFP2 or later is available)
159//===----------------------------------------------------------------------===//
160
161def CC_ARM_AAPCS_VFP : CallingConv<[
162  // Handles byval parameters.
163  CCIfByVal<CCPassByVal<4, 4>>,
164
165  // Handle all vector types as either f64 or v2f64.
166  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
167  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
168
169  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
170  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
171  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
172                                 S9, S10, S11, S12, S13, S14, S15]>>,
173  CCDelegateTo<CC_ARM_AAPCS_Common>
174]>;
175
176def RetCC_ARM_AAPCS_VFP : CallingConv<[
177  // Handle all vector types as either f64 or v2f64.
178  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
179  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
180
181  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
182  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
183  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
184                                 S9, S10, S11, S12, S13, S14, S15]>>,
185  CCDelegateTo<RetCC_ARM_AAPCS_Common>
186]>;
187
188//===----------------------------------------------------------------------===//
189// Callee-saved register lists.
190//===----------------------------------------------------------------------===//
191
192def CSR_NoRegs : CalleeSavedRegs<(add)>;
193
194def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
195                                     (sequence "D%u", 15, 8))>;
196
197// Constructors and destructors return 'this' in the ARM C++ ABI; since 'this'
198// and the pointer return value are both passed in R0 in these cases, this can
199// be partially modelled by treating R0 as a callee-saved register
200// Only the resulting RegMask is used; the SaveList is ignored
201def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
202                                            R5, R4, (sequence "D%u", 15, 8),
203                                            R0)>;
204
205// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
206// Also save R7-R4 first to match the stack frame fixed spill areas.
207def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
208
209def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
210                                         (sub CSR_AAPCS_ThisReturn, R9))>;
211
212// The "interrupt" attribute is used to generate code that is acceptable in
213// exception-handlers of various kinds. It makes us use a different return
214// instruction (handled elsewhere) and affects which registers we must return to
215// our "caller" in the same state as we receive them.
216
217// For most interrupts, all registers except SP and LR are shared with
218// user-space. We mark LR to be saved anyway, since this is what the ARM backend
219// generally does rather than tracking its liveness as a normal register.
220def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>;
221
222// The fast interrupt handlers have more private state and get their own copies
223// of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
224
225// FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
226// current frame lowering expects to encounter it while processing callee-saved
227// registers.
228def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;
229
230
231