1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM VFP instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 15def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 16def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 17def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 18 SDTCisSameAs<1, 2>]>; 19 20def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>; 21def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; 22def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; 23def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; 24def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 25def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 26def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 27def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 28 29 30//===----------------------------------------------------------------------===// 31// Operand Definitions. 32// 33 34// 8-bit floating-point immediate encodings. 35def FPImmOperand : AsmOperandClass { 36 let Name = "FPImm"; 37 let ParserMethod = "parseFPImm"; 38} 39 40def vfp_f32imm : Operand<f32>, 41 PatLeaf<(f32 fpimm), [{ 42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 43 }], SDNodeXForm<fpimm, [{ 44 APFloat InVal = N->getValueAPF(); 45 uint32_t enc = ARM_AM::getFP32Imm(InVal); 46 return CurDAG->getTargetConstant(enc, MVT::i32); 47 }]>> { 48 let PrintMethod = "printFPImmOperand"; 49 let ParserMatchClass = FPImmOperand; 50} 51 52def vfp_f64imm : Operand<f64>, 53 PatLeaf<(f64 fpimm), [{ 54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 55 }], SDNodeXForm<fpimm, [{ 56 APFloat InVal = N->getValueAPF(); 57 uint32_t enc = ARM_AM::getFP64Imm(InVal); 58 return CurDAG->getTargetConstant(enc, MVT::i32); 59 }]>> { 60 let PrintMethod = "printFPImmOperand"; 61 let ParserMatchClass = FPImmOperand; 62} 63 64def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 65 return cast<LoadSDNode>(N)->getAlignment() >= 4; 66}]>; 67 68def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 69 (store node:$val, node:$ptr), [{ 70 return cast<StoreSDNode>(N)->getAlignment() >= 4; 71}]>; 72 73// The VCVT to/from fixed-point instructions encode the 'fbits' operand 74// (the number of fixed bits) differently than it appears in the assembly 75// source. It's encoded as "Size - fbits" where Size is the size of the 76// fixed-point representation (32 or 16) and fbits is the value appearing 77// in the assembly source, an integer in [0,16] or (0,32], depending on size. 78def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 79def fbits32 : Operand<i32> { 80 let PrintMethod = "printFBits32"; 81 let ParserMatchClass = fbits32_asm_operand; 82} 83 84def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 85def fbits16 : Operand<i32> { 86 let PrintMethod = "printFBits16"; 87 let ParserMatchClass = fbits16_asm_operand; 88} 89 90//===----------------------------------------------------------------------===// 91// Load / store Instructions. 92// 93 94let canFoldAsLoad = 1, isReMaterializable = 1 in { 95 96def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 97 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>; 99 100def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 101 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 102 [(set SPR:$Sd, (load addrmode5:$addr))]> { 103 // Some single precision VFP instructions may be executed on both NEON and VFP 104 // pipelines. 105 let D = VFPNeonDomain; 106} 107 108} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 109 110def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 111 IIC_fpStore64, "vstr", "\t$Dd, $addr", 112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>; 113 114def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 115 IIC_fpStore32, "vstr", "\t$Sd, $addr", 116 [(store SPR:$Sd, addrmode5:$addr)]> { 117 // Some single precision VFP instructions may be executed on both NEON and VFP 118 // pipelines. 119 let D = VFPNeonDomain; 120} 121 122//===----------------------------------------------------------------------===// 123// Load / store multiple Instructions. 124// 125 126multiclass vfp_ldst_mult<string asm, bit L_bit, 127 InstrItinClass itin, InstrItinClass itin_upd> { 128 // Double Precision 129 def DIA : 130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 131 IndexModeNone, itin, 132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 133 let Inst{24-23} = 0b01; // Increment After 134 let Inst{21} = 0; // No writeback 135 let Inst{20} = L_bit; 136 } 137 def DIA_UPD : 138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 139 variable_ops), 140 IndexModeUpd, itin_upd, 141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 142 let Inst{24-23} = 0b01; // Increment After 143 let Inst{21} = 1; // Writeback 144 let Inst{20} = L_bit; 145 } 146 def DDB_UPD : 147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 148 variable_ops), 149 IndexModeUpd, itin_upd, 150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 151 let Inst{24-23} = 0b10; // Decrement Before 152 let Inst{21} = 1; // Writeback 153 let Inst{20} = L_bit; 154 } 155 156 // Single Precision 157 def SIA : 158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 159 IndexModeNone, itin, 160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 161 let Inst{24-23} = 0b01; // Increment After 162 let Inst{21} = 0; // No writeback 163 let Inst{20} = L_bit; 164 165 // Some single precision VFP instructions may be executed on both NEON and 166 // VFP pipelines. 167 let D = VFPNeonDomain; 168 } 169 def SIA_UPD : 170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 171 variable_ops), 172 IndexModeUpd, itin_upd, 173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 174 let Inst{24-23} = 0b01; // Increment After 175 let Inst{21} = 1; // Writeback 176 let Inst{20} = L_bit; 177 178 // Some single precision VFP instructions may be executed on both NEON and 179 // VFP pipelines. 180 let D = VFPNeonDomain; 181 } 182 def SDB_UPD : 183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 184 variable_ops), 185 IndexModeUpd, itin_upd, 186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 187 let Inst{24-23} = 0b10; // Decrement Before 188 let Inst{21} = 1; // Writeback 189 let Inst{20} = L_bit; 190 191 // Some single precision VFP instructions may be executed on both NEON and 192 // VFP pipelines. 193 let D = VFPNeonDomain; 194 } 195} 196 197let hasSideEffects = 0 in { 198 199let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 200defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 201 202let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 203defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>; 204 205} // hasSideEffects 206 207def : MnemonicAlias<"vldm", "vldmia">; 208def : MnemonicAlias<"vstm", "vstmia">; 209 210// FLDM/FSTM - Load / Store multiple single / double precision registers for 211// pre-ARMv6 cores. 212// These instructions are deprecated! 213def : VFP2MnemonicAlias<"fldmias", "vldmia">; 214def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">; 215def : VFP2MnemonicAlias<"fldmeas", "vldmdb">; 216def : VFP2MnemonicAlias<"fldmfds", "vldmia">; 217def : VFP2MnemonicAlias<"fldmiad", "vldmia">; 218def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">; 219def : VFP2MnemonicAlias<"fldmead", "vldmdb">; 220def : VFP2MnemonicAlias<"fldmfdd", "vldmia">; 221 222def : VFP2MnemonicAlias<"fstmias", "vstmia">; 223def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">; 224def : VFP2MnemonicAlias<"fstmeas", "vstmia">; 225def : VFP2MnemonicAlias<"fstmfds", "vstmdb">; 226def : VFP2MnemonicAlias<"fstmiad", "vstmia">; 227def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">; 228def : VFP2MnemonicAlias<"fstmead", "vstmia">; 229def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">; 230 231def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>, 232 Requires<[HasVFP2]>; 233def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>, 234 Requires<[HasVFP2]>; 235def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>, 236 Requires<[HasVFP2]>; 237def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>, 238 Requires<[HasVFP2]>; 239defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 240 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 241defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 242 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 243defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 244 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 245defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 246 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 247 248// FLDMX, FSTMX - Load and store multiple unknown precision registers for 249// pre-armv6 cores. 250// These instruction are deprecated so we don't want them to get selected. 251multiclass vfp_ldstx_mult<string asm, bit L_bit> { 252 // Unknown precision 253 def XIA : 254 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 255 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 256 let Inst{24-23} = 0b01; // Increment After 257 let Inst{21} = 0; // No writeback 258 let Inst{20} = L_bit; 259 } 260 def XIA_UPD : 261 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 262 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 263 let Inst{24-23} = 0b01; // Increment After 264 let Inst{21} = 1; // Writeback 265 let Inst{20} = L_bit; 266 } 267 def XDB_UPD : 268 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 269 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 270 let Inst{24-23} = 0b10; // Decrement Before 271 let Inst{21} = 1; // Writeback 272 let Inst{20} = L_bit; 273 } 274} 275 276defm FLDM : vfp_ldstx_mult<"fldm", 1>; 277defm FSTM : vfp_ldstx_mult<"fstm", 0>; 278 279def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">; 280def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">; 281 282def : VFP2MnemonicAlias<"fstmeax", "fstmiax">; 283def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; 284 285//===----------------------------------------------------------------------===// 286// FP Binary Operations. 287// 288 289let TwoOperandAliasConstraint = "$Dn = $Dd" in 290def VADDD : ADbI<0b11100, 0b11, 0, 0, 291 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 292 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 293 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; 294 295let TwoOperandAliasConstraint = "$Sn = $Sd" in 296def VADDS : ASbIn<0b11100, 0b11, 0, 0, 297 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 298 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 299 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { 300 // Some single precision VFP instructions may be executed on both NEON and 301 // VFP pipelines on A8. 302 let D = VFPNeonA8Domain; 303} 304 305let TwoOperandAliasConstraint = "$Dn = $Dd" in 306def VSUBD : ADbI<0b11100, 0b11, 1, 0, 307 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 308 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 309 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; 310 311let TwoOperandAliasConstraint = "$Sn = $Sd" in 312def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 313 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 314 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 315 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> { 316 // Some single precision VFP instructions may be executed on both NEON and 317 // VFP pipelines on A8. 318 let D = VFPNeonA8Domain; 319} 320 321let TwoOperandAliasConstraint = "$Dn = $Dd" in 322def VDIVD : ADbI<0b11101, 0b00, 0, 0, 323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 324 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 325 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; 326 327let TwoOperandAliasConstraint = "$Sn = $Sd" in 328def VDIVS : ASbI<0b11101, 0b00, 0, 0, 329 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 330 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 331 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; 332 333let TwoOperandAliasConstraint = "$Dn = $Dd" in 334def VMULD : ADbI<0b11100, 0b10, 0, 0, 335 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 336 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 337 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; 338 339let TwoOperandAliasConstraint = "$Sn = $Sd" in 340def VMULS : ASbIn<0b11100, 0b10, 0, 0, 341 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 342 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 343 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> { 344 // Some single precision VFP instructions may be executed on both NEON and 345 // VFP pipelines on A8. 346 let D = VFPNeonA8Domain; 347} 348 349def VNMULD : ADbI<0b11100, 0b10, 1, 0, 350 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 351 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 352 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; 353 354def VNMULS : ASbI<0b11100, 0b10, 1, 0, 355 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 356 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 357 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> { 358 // Some single precision VFP instructions may be executed on both NEON and 359 // VFP pipelines on A8. 360 let D = VFPNeonA8Domain; 361} 362 363multiclass vsel_inst<string op, bits<2> opc, int CC> { 364 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 365 Uses = [CPSR], AddedComplexity = 4 in { 366 def S : ASbInp<0b11100, opc, 0, 367 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 368 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 369 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, 370 Requires<[HasFPARMv8]>; 371 372 def D : ADbInp<0b11100, opc, 0, 373 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 374 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 375 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, 376 Requires<[HasFPARMv8, HasDPVFP]>; 377 } 378} 379 380// The CC constants here match ARMCC::CondCodes. 381defm VSELGT : vsel_inst<"gt", 0b11, 12>; 382defm VSELGE : vsel_inst<"ge", 0b10, 10>; 383defm VSELEQ : vsel_inst<"eq", 0b00, 0>; 384defm VSELVS : vsel_inst<"vs", 0b01, 6>; 385 386multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { 387 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { 388 def S : ASbInp<0b11101, 0b00, opc, 389 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 390 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 391 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>, 392 Requires<[HasFPARMv8]>; 393 394 def D : ADbInp<0b11101, 0b00, opc, 395 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 396 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 397 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>, 398 Requires<[HasFPARMv8, HasDPVFP]>; 399 } 400} 401 402defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>; 403defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>; 404 405// Match reassociated forms only if not sign dependent rounding. 406def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 407 (VNMULD DPR:$a, DPR:$b)>, 408 Requires<[NoHonorSignDependentRounding,HasDPVFP]>; 409def : Pat<(fmul (fneg SPR:$a), SPR:$b), 410 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 411 412// These are encoded as unary instructions. 413let Defs = [FPSCR_NZCV] in { 414def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 415 (outs), (ins DPR:$Dd, DPR:$Dm), 416 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 417 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 418 419def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 420 (outs), (ins SPR:$Sd, SPR:$Sm), 421 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 422 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 423 // Some single precision VFP instructions may be executed on both NEON and 424 // VFP pipelines on A8. 425 let D = VFPNeonA8Domain; 426} 427 428// FIXME: Verify encoding after integrated assembler is working. 429def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 430 (outs), (ins DPR:$Dd, DPR:$Dm), 431 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 432 [/* For disassembly only; pattern left blank */]>; 433 434def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 435 (outs), (ins SPR:$Sd, SPR:$Sm), 436 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 437 [/* For disassembly only; pattern left blank */]> { 438 // Some single precision VFP instructions may be executed on both NEON and 439 // VFP pipelines on A8. 440 let D = VFPNeonA8Domain; 441} 442} // Defs = [FPSCR_NZCV] 443 444//===----------------------------------------------------------------------===// 445// FP Unary Operations. 446// 447 448def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 449 (outs DPR:$Dd), (ins DPR:$Dm), 450 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 451 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 452 453def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 454 (outs SPR:$Sd), (ins SPR:$Sm), 455 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 456 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 457 // Some single precision VFP instructions may be executed on both NEON and 458 // VFP pipelines on A8. 459 let D = VFPNeonA8Domain; 460} 461 462let Defs = [FPSCR_NZCV] in { 463def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 464 (outs), (ins DPR:$Dd), 465 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 466 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 467 let Inst{3-0} = 0b0000; 468 let Inst{5} = 0; 469} 470 471def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 472 (outs), (ins SPR:$Sd), 473 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 474 [(arm_cmpfp0 SPR:$Sd)]> { 475 let Inst{3-0} = 0b0000; 476 let Inst{5} = 0; 477 478 // Some single precision VFP instructions may be executed on both NEON and 479 // VFP pipelines on A8. 480 let D = VFPNeonA8Domain; 481} 482 483// FIXME: Verify encoding after integrated assembler is working. 484def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 485 (outs), (ins DPR:$Dd), 486 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 487 [/* For disassembly only; pattern left blank */]> { 488 let Inst{3-0} = 0b0000; 489 let Inst{5} = 0; 490} 491 492def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 493 (outs), (ins SPR:$Sd), 494 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 495 [/* For disassembly only; pattern left blank */]> { 496 let Inst{3-0} = 0b0000; 497 let Inst{5} = 0; 498 499 // Some single precision VFP instructions may be executed on both NEON and 500 // VFP pipelines on A8. 501 let D = VFPNeonA8Domain; 502} 503} // Defs = [FPSCR_NZCV] 504 505def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 506 (outs DPR:$Dd), (ins SPR:$Sm), 507 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 508 [(set DPR:$Dd, (fextend SPR:$Sm))]> { 509 // Instruction operands. 510 bits<5> Dd; 511 bits<5> Sm; 512 513 // Encode instruction operands. 514 let Inst{3-0} = Sm{4-1}; 515 let Inst{5} = Sm{0}; 516 let Inst{15-12} = Dd{3-0}; 517 let Inst{22} = Dd{4}; 518 519 let Predicates = [HasVFP2, HasDPVFP]; 520} 521 522// Special case encoding: bits 11-8 is 0b1011. 523def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 524 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 525 [(set SPR:$Sd, (fround DPR:$Dm))]> { 526 // Instruction operands. 527 bits<5> Sd; 528 bits<5> Dm; 529 530 // Encode instruction operands. 531 let Inst{3-0} = Dm{3-0}; 532 let Inst{5} = Dm{4}; 533 let Inst{15-12} = Sd{4-1}; 534 let Inst{22} = Sd{0}; 535 536 let Inst{27-23} = 0b11101; 537 let Inst{21-16} = 0b110111; 538 let Inst{11-8} = 0b1011; 539 let Inst{7-6} = 0b11; 540 let Inst{4} = 0; 541 542 let Predicates = [HasVFP2, HasDPVFP]; 543} 544 545// Between half, single and double-precision. For disassembly only. 546 547// FIXME: Verify encoding after integrated assembler is working. 548def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 549 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 550 [/* For disassembly only; pattern left blank */]>; 551 552def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 553 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 554 [/* For disassembly only; pattern left blank */]>; 555 556def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 557 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 558 [/* For disassembly only; pattern left blank */]>; 559 560def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 561 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 562 [/* For disassembly only; pattern left blank */]>; 563 564def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 565 (outs DPR:$Dd), (ins SPR:$Sm), 566 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", 567 []>, Requires<[HasFPARMv8, HasDPVFP]> { 568 // Instruction operands. 569 bits<5> Sm; 570 571 // Encode instruction operands. 572 let Inst{3-0} = Sm{4-1}; 573 let Inst{5} = Sm{0}; 574} 575 576def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 577 (outs SPR:$Sd), (ins DPR:$Dm), 578 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", 579 []>, Requires<[HasFPARMv8, HasDPVFP]> { 580 // Instruction operands. 581 bits<5> Sd; 582 bits<5> Dm; 583 584 // Encode instruction operands. 585 let Inst{3-0} = Dm{3-0}; 586 let Inst{5} = Dm{4}; 587 let Inst{15-12} = Sd{4-1}; 588 let Inst{22} = Sd{0}; 589} 590 591def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 592 (outs DPR:$Dd), (ins SPR:$Sm), 593 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", 594 []>, Requires<[HasFPARMv8, HasDPVFP]> { 595 // Instruction operands. 596 bits<5> Sm; 597 598 // Encode instruction operands. 599 let Inst{3-0} = Sm{4-1}; 600 let Inst{5} = Sm{0}; 601} 602 603def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 604 (outs SPR:$Sd), (ins DPR:$Dm), 605 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", 606 []>, Requires<[HasFPARMv8, HasDPVFP]> { 607 // Instruction operands. 608 bits<5> Sd; 609 bits<5> Dm; 610 611 // Encode instruction operands. 612 let Inst{15-12} = Sd{4-1}; 613 let Inst{22} = Sd{0}; 614 let Inst{3-0} = Dm{3-0}; 615 let Inst{5} = Dm{4}; 616} 617 618def : Pat<(fp_to_f16 SPR:$a), 619 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 620 621def : Pat<(fp_to_f16 (f64 DPR:$a)), 622 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>; 623 624def : Pat<(f16_to_fp GPR:$a), 625 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 626 627def : Pat<(f64 (f16_to_fp GPR:$a)), 628 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>; 629 630multiclass vcvt_inst<string opc, bits<2> rm, 631 SDPatternOperator node = null_frag> { 632 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 633 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 634 (outs SPR:$Sd), (ins SPR:$Sm), 635 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 636 [(set SPR:$Sd, (arm_ftosi (node SPR:$Sm)))]>, 637 Requires<[HasFPARMv8]> { 638 let Inst{17-16} = rm; 639 } 640 641 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 642 (outs SPR:$Sd), (ins SPR:$Sm), 643 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 644 [(set SPR:$Sd, (arm_ftoui (node SPR:$Sm)))]>, 645 Requires<[HasFPARMv8]> { 646 let Inst{17-16} = rm; 647 } 648 649 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 650 (outs SPR:$Sd), (ins DPR:$Dm), 651 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 652 [(set SPR:$Sd, (arm_ftosi (f64 (node (f64 DPR:$Dm)))))]>, 653 Requires<[HasFPARMv8, HasDPVFP]> { 654 bits<5> Dm; 655 656 let Inst{17-16} = rm; 657 658 // Encode instruction operands 659 let Inst{3-0} = Dm{3-0}; 660 let Inst{5} = Dm{4}; 661 let Inst{8} = 1; 662 } 663 664 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 665 (outs SPR:$Sd), (ins DPR:$Dm), 666 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 667 [(set SPR:$Sd, (arm_ftoui (f64 (node (f64 DPR:$Dm)))))]>, 668 Requires<[HasFPARMv8, HasDPVFP]> { 669 bits<5> Dm; 670 671 let Inst{17-16} = rm; 672 673 // Encode instruction operands 674 let Inst{3-0} = Dm{3-0}; 675 let Inst{5} = Dm{4}; 676 let Inst{8} = 1; 677 } 678 } 679} 680 681defm VCVTA : vcvt_inst<"a", 0b00, frnd>; 682defm VCVTN : vcvt_inst<"n", 0b01>; 683defm VCVTP : vcvt_inst<"p", 0b10, fceil>; 684defm VCVTM : vcvt_inst<"m", 0b11, ffloor>; 685 686def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 687 (outs DPR:$Dd), (ins DPR:$Dm), 688 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 689 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 690 691def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 692 (outs SPR:$Sd), (ins SPR:$Sm), 693 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 694 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 695 // Some single precision VFP instructions may be executed on both NEON and 696 // VFP pipelines on A8. 697 let D = VFPNeonA8Domain; 698} 699 700multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { 701 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 702 (outs SPR:$Sd), (ins SPR:$Sm), 703 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", 704 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 705 Requires<[HasFPARMv8]> { 706 let Inst{7} = op2; 707 let Inst{16} = op; 708 } 709 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 710 (outs DPR:$Dd), (ins DPR:$Dm), 711 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", 712 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 713 Requires<[HasFPARMv8, HasDPVFP]> { 714 let Inst{7} = op2; 715 let Inst{16} = op; 716 } 717 718 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), 719 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>, 720 Requires<[HasFPARMv8]>; 721 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), 722 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>, 723 Requires<[HasFPARMv8,HasDPVFP]>; 724} 725 726defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>; 727defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>; 728defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>; 729 730multiclass vrint_inst_anpm<string opc, bits<2> rm, 731 SDPatternOperator node = null_frag> { 732 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 733 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 734 (outs SPR:$Sd), (ins SPR:$Sm), 735 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 736 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 737 Requires<[HasFPARMv8]> { 738 let Inst{17-16} = rm; 739 } 740 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 741 (outs DPR:$Dd), (ins DPR:$Dm), 742 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 743 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 744 Requires<[HasFPARMv8, HasDPVFP]> { 745 let Inst{17-16} = rm; 746 } 747 } 748 749 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 750 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>, 751 Requires<[HasFPARMv8]>; 752 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 753 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>, 754 Requires<[HasFPARMv8,HasDPVFP]>; 755} 756 757defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>; 758defm VRINTN : vrint_inst_anpm<"n", 0b01>; 759defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>; 760defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>; 761 762def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 763 (outs DPR:$Dd), (ins DPR:$Dm), 764 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 765 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; 766 767def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 768 (outs SPR:$Sd), (ins SPR:$Sm), 769 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 770 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; 771 772let hasSideEffects = 0 in { 773def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 774 (outs DPR:$Dd), (ins DPR:$Dm), 775 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; 776 777def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 778 (outs SPR:$Sd), (ins SPR:$Sm), 779 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; 780} // hasSideEffects 781 782//===----------------------------------------------------------------------===// 783// FP <-> GPR Copies. Int <-> FP Conversions. 784// 785 786def VMOVRS : AVConv2I<0b11100001, 0b1010, 787 (outs GPR:$Rt), (ins SPR:$Sn), 788 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 789 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { 790 // Instruction operands. 791 bits<4> Rt; 792 bits<5> Sn; 793 794 // Encode instruction operands. 795 let Inst{19-16} = Sn{4-1}; 796 let Inst{7} = Sn{0}; 797 let Inst{15-12} = Rt; 798 799 let Inst{6-5} = 0b00; 800 let Inst{3-0} = 0b0000; 801 802 // Some single precision VFP instructions may be executed on both NEON and VFP 803 // pipelines. 804 let D = VFPNeonDomain; 805} 806 807// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 808def VMOVSR : AVConv4I<0b11100000, 0b1010, 809 (outs SPR:$Sn), (ins GPR:$Rt), 810 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 811 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 812 Requires<[HasVFP2, UseVMOVSR]> { 813 // Instruction operands. 814 bits<5> Sn; 815 bits<4> Rt; 816 817 // Encode instruction operands. 818 let Inst{19-16} = Sn{4-1}; 819 let Inst{7} = Sn{0}; 820 let Inst{15-12} = Rt; 821 822 let Inst{6-5} = 0b00; 823 let Inst{3-0} = 0b0000; 824 825 // Some single precision VFP instructions may be executed on both NEON and VFP 826 // pipelines. 827 let D = VFPNeonDomain; 828} 829 830let hasSideEffects = 0 in { 831def VMOVRRD : AVConv3I<0b11000101, 0b1011, 832 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 833 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 834 [/* FIXME: Can't write pattern for multiple result instr*/]> { 835 // Instruction operands. 836 bits<5> Dm; 837 bits<4> Rt; 838 bits<4> Rt2; 839 840 // Encode instruction operands. 841 let Inst{3-0} = Dm{3-0}; 842 let Inst{5} = Dm{4}; 843 let Inst{15-12} = Rt; 844 let Inst{19-16} = Rt2; 845 846 let Inst{7-6} = 0b00; 847 848 // Some single precision VFP instructions may be executed on both NEON and VFP 849 // pipelines. 850 let D = VFPNeonDomain; 851 852 // This instruction is equivalent to 853 // $Rt = EXTRACT_SUBREG $Dm, ssub_0 854 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1 855 let isExtractSubreg = 1; 856} 857 858def VMOVRRS : AVConv3I<0b11000101, 0b1010, 859 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 860 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 861 [/* For disassembly only; pattern left blank */]> { 862 bits<5> src1; 863 bits<4> Rt; 864 bits<4> Rt2; 865 866 // Encode instruction operands. 867 let Inst{3-0} = src1{4-1}; 868 let Inst{5} = src1{0}; 869 let Inst{15-12} = Rt; 870 let Inst{19-16} = Rt2; 871 872 let Inst{7-6} = 0b00; 873 874 // Some single precision VFP instructions may be executed on both NEON and VFP 875 // pipelines. 876 let D = VFPNeonDomain; 877 let DecoderMethod = "DecodeVMOVRRS"; 878} 879} // hasSideEffects 880 881// FMDHR: GPR -> SPR 882// FMDLR: GPR -> SPR 883 884def VMOVDRR : AVConv5I<0b11000100, 0b1011, 885 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 886 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 887 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> { 888 // Instruction operands. 889 bits<5> Dm; 890 bits<4> Rt; 891 bits<4> Rt2; 892 893 // Encode instruction operands. 894 let Inst{3-0} = Dm{3-0}; 895 let Inst{5} = Dm{4}; 896 let Inst{15-12} = Rt; 897 let Inst{19-16} = Rt2; 898 899 let Inst{7-6} = 0b00; 900 901 // Some single precision VFP instructions may be executed on both NEON and VFP 902 // pipelines. 903 let D = VFPNeonDomain; 904 905 // This instruction is equivalent to 906 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1 907 let isRegSequence = 1; 908} 909 910let hasSideEffects = 0 in 911def VMOVSRR : AVConv5I<0b11000100, 0b1010, 912 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 913 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 914 [/* For disassembly only; pattern left blank */]> { 915 // Instruction operands. 916 bits<5> dst1; 917 bits<4> src1; 918 bits<4> src2; 919 920 // Encode instruction operands. 921 let Inst{3-0} = dst1{4-1}; 922 let Inst{5} = dst1{0}; 923 let Inst{15-12} = src1; 924 let Inst{19-16} = src2; 925 926 let Inst{7-6} = 0b00; 927 928 // Some single precision VFP instructions may be executed on both NEON and VFP 929 // pipelines. 930 let D = VFPNeonDomain; 931 932 let DecoderMethod = "DecodeVMOVSRR"; 933} 934 935// FMRDH: SPR -> GPR 936// FMRDL: SPR -> GPR 937// FMRRS: SPR -> GPR 938// FMRX: SPR system reg -> GPR 939// FMSRR: GPR -> SPR 940// FMXR: GPR -> VFP system reg 941 942 943// Int -> FP: 944 945class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 946 bits<4> opcod4, dag oops, dag iops, 947 InstrItinClass itin, string opc, string asm, 948 list<dag> pattern> 949 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 950 pattern> { 951 // Instruction operands. 952 bits<5> Dd; 953 bits<5> Sm; 954 955 // Encode instruction operands. 956 let Inst{3-0} = Sm{4-1}; 957 let Inst{5} = Sm{0}; 958 let Inst{15-12} = Dd{3-0}; 959 let Inst{22} = Dd{4}; 960 961 let Predicates = [HasVFP2, HasDPVFP]; 962} 963 964class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 965 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 966 string opc, string asm, list<dag> pattern> 967 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 968 pattern> { 969 // Instruction operands. 970 bits<5> Sd; 971 bits<5> Sm; 972 973 // Encode instruction operands. 974 let Inst{3-0} = Sm{4-1}; 975 let Inst{5} = Sm{0}; 976 let Inst{15-12} = Sd{4-1}; 977 let Inst{22} = Sd{0}; 978} 979 980def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 981 (outs DPR:$Dd), (ins SPR:$Sm), 982 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 983 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> { 984 let Inst{7} = 1; // s32 985} 986 987def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 988 (outs SPR:$Sd),(ins SPR:$Sm), 989 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 990 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> { 991 let Inst{7} = 1; // s32 992 993 // Some single precision VFP instructions may be executed on both NEON and 994 // VFP pipelines on A8. 995 let D = VFPNeonA8Domain; 996} 997 998def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 999 (outs DPR:$Dd), (ins SPR:$Sm), 1000 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 1001 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> { 1002 let Inst{7} = 0; // u32 1003} 1004 1005def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1006 (outs SPR:$Sd), (ins SPR:$Sm), 1007 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 1008 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> { 1009 let Inst{7} = 0; // u32 1010 1011 // Some single precision VFP instructions may be executed on both NEON and 1012 // VFP pipelines on A8. 1013 let D = VFPNeonA8Domain; 1014} 1015 1016// FP -> Int: 1017 1018class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1019 bits<4> opcod4, dag oops, dag iops, 1020 InstrItinClass itin, string opc, string asm, 1021 list<dag> pattern> 1022 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1023 pattern> { 1024 // Instruction operands. 1025 bits<5> Sd; 1026 bits<5> Dm; 1027 1028 // Encode instruction operands. 1029 let Inst{3-0} = Dm{3-0}; 1030 let Inst{5} = Dm{4}; 1031 let Inst{15-12} = Sd{4-1}; 1032 let Inst{22} = Sd{0}; 1033 1034 let Predicates = [HasVFP2, HasDPVFP]; 1035} 1036 1037class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1038 bits<4> opcod4, dag oops, dag iops, 1039 InstrItinClass itin, string opc, string asm, 1040 list<dag> pattern> 1041 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1042 pattern> { 1043 // Instruction operands. 1044 bits<5> Sd; 1045 bits<5> Sm; 1046 1047 // Encode instruction operands. 1048 let Inst{3-0} = Sm{4-1}; 1049 let Inst{5} = Sm{0}; 1050 let Inst{15-12} = Sd{4-1}; 1051 let Inst{22} = Sd{0}; 1052} 1053 1054// Always set Z bit in the instruction, i.e. "round towards zero" variants. 1055def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1056 (outs SPR:$Sd), (ins DPR:$Dm), 1057 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 1058 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> { 1059 let Inst{7} = 1; // Z bit 1060} 1061 1062def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1063 (outs SPR:$Sd), (ins SPR:$Sm), 1064 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 1065 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> { 1066 let Inst{7} = 1; // Z bit 1067 1068 // Some single precision VFP instructions may be executed on both NEON and 1069 // VFP pipelines on A8. 1070 let D = VFPNeonA8Domain; 1071} 1072 1073def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1074 (outs SPR:$Sd), (ins DPR:$Dm), 1075 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1076 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> { 1077 let Inst{7} = 1; // Z bit 1078} 1079 1080def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1081 (outs SPR:$Sd), (ins SPR:$Sm), 1082 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1083 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> { 1084 let Inst{7} = 1; // Z bit 1085 1086 // Some single precision VFP instructions may be executed on both NEON and 1087 // VFP pipelines on A8. 1088 let D = VFPNeonA8Domain; 1089} 1090 1091// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1092let Uses = [FPSCR] in { 1093// FIXME: Verify encoding after integrated assembler is working. 1094def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1095 (outs SPR:$Sd), (ins DPR:$Dm), 1096 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1097 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{ 1098 let Inst{7} = 0; // Z bit 1099} 1100 1101def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1102 (outs SPR:$Sd), (ins SPR:$Sm), 1103 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1104 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> { 1105 let Inst{7} = 0; // Z bit 1106} 1107 1108def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1109 (outs SPR:$Sd), (ins DPR:$Dm), 1110 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1111 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{ 1112 let Inst{7} = 0; // Z bit 1113} 1114 1115def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1116 (outs SPR:$Sd), (ins SPR:$Sm), 1117 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1118 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> { 1119 let Inst{7} = 0; // Z bit 1120} 1121} 1122 1123// Convert between floating-point and fixed-point 1124// Data type for fixed-point naming convention: 1125// S16 (U=0, sx=0) -> SH 1126// U16 (U=1, sx=0) -> UH 1127// S32 (U=0, sx=1) -> SL 1128// U32 (U=1, sx=1) -> UL 1129 1130let Constraints = "$a = $dst" in { 1131 1132// FP to Fixed-Point: 1133 1134// Single Precision register 1135class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1136 bit op5, dag oops, dag iops, InstrItinClass itin, 1137 string opc, string asm, list<dag> pattern> 1138 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1139 Sched<[WriteCvtFP]> { 1140 bits<5> dst; 1141 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1142 let Inst{22} = dst{0}; 1143 let Inst{15-12} = dst{4-1}; 1144} 1145 1146// Double Precision register 1147class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1148 bit op5, dag oops, dag iops, InstrItinClass itin, 1149 string opc, string asm, list<dag> pattern> 1150 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1151 Sched<[WriteCvtFP]> { 1152 bits<5> dst; 1153 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1154 let Inst{22} = dst{4}; 1155 let Inst{15-12} = dst{3-0}; 1156 1157 let Predicates = [HasVFP2, HasDPVFP]; 1158} 1159 1160def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1161 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1162 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> { 1163 // Some single precision VFP instructions may be executed on both NEON and 1164 // VFP pipelines on A8. 1165 let D = VFPNeonA8Domain; 1166} 1167 1168def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1169 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1170 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> { 1171 // Some single precision VFP instructions may be executed on both NEON and 1172 // VFP pipelines on A8. 1173 let D = VFPNeonA8Domain; 1174} 1175 1176def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1177 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1178 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> { 1179 // Some single precision VFP instructions may be executed on both NEON and 1180 // VFP pipelines on A8. 1181 let D = VFPNeonA8Domain; 1182} 1183 1184def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1185 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1186 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> { 1187 // Some single precision VFP instructions may be executed on both NEON and 1188 // VFP pipelines on A8. 1189 let D = VFPNeonA8Domain; 1190} 1191 1192def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1193 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1194 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>; 1195 1196def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1197 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1198 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>; 1199 1200def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1201 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1202 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>; 1203 1204def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1205 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1206 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>; 1207 1208// Fixed-Point to FP: 1209 1210def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1211 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1212 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> { 1213 // Some single precision VFP instructions may be executed on both NEON and 1214 // VFP pipelines on A8. 1215 let D = VFPNeonA8Domain; 1216} 1217 1218def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1219 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1220 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> { 1221 // Some single precision VFP instructions may be executed on both NEON and 1222 // VFP pipelines on A8. 1223 let D = VFPNeonA8Domain; 1224} 1225 1226def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1227 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1228 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> { 1229 // Some single precision VFP instructions may be executed on both NEON and 1230 // VFP pipelines on A8. 1231 let D = VFPNeonA8Domain; 1232} 1233 1234def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1235 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1236 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> { 1237 // Some single precision VFP instructions may be executed on both NEON and 1238 // VFP pipelines on A8. 1239 let D = VFPNeonA8Domain; 1240} 1241 1242def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1243 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1244 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>; 1245 1246def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1247 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1248 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>; 1249 1250def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1251 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1252 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>; 1253 1254def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1255 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1256 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>; 1257 1258} // End of 'let Constraints = "$a = $dst" in' 1259 1260//===----------------------------------------------------------------------===// 1261// FP Multiply-Accumulate Operations. 1262// 1263 1264def VMLAD : ADbI<0b11100, 0b00, 0, 0, 1265 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1266 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 1267 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1268 (f64 DPR:$Ddin)))]>, 1269 RegConstraint<"$Ddin = $Dd">, 1270 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1271 1272def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 1273 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1274 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 1275 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1276 SPR:$Sdin))]>, 1277 RegConstraint<"$Sdin = $Sd">, 1278 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1279 // Some single precision VFP instructions may be executed on both NEON and 1280 // VFP pipelines on A8. 1281 let D = VFPNeonA8Domain; 1282} 1283 1284def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1285 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1286 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1287def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1288 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1289 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>; 1290 1291def VMLSD : ADbI<0b11100, 0b00, 1, 0, 1292 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1293 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 1294 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1295 (f64 DPR:$Ddin)))]>, 1296 RegConstraint<"$Ddin = $Dd">, 1297 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1298 1299def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 1300 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1301 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 1302 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1303 SPR:$Sdin))]>, 1304 RegConstraint<"$Sdin = $Sd">, 1305 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1306 // Some single precision VFP instructions may be executed on both NEON and 1307 // VFP pipelines on A8. 1308 let D = VFPNeonA8Domain; 1309} 1310 1311def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1312 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1313 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1314def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1315 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1316 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1317 1318def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 1319 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1320 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 1321 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1322 (f64 DPR:$Ddin)))]>, 1323 RegConstraint<"$Ddin = $Dd">, 1324 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1325 1326def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 1327 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1328 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 1329 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1330 SPR:$Sdin))]>, 1331 RegConstraint<"$Sdin = $Sd">, 1332 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1333 // Some single precision VFP instructions may be executed on both NEON and 1334 // VFP pipelines on A8. 1335 let D = VFPNeonA8Domain; 1336} 1337 1338def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1339 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1340 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1341def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1342 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1343 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1344 1345def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 1346 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1347 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 1348 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1349 (f64 DPR:$Ddin)))]>, 1350 RegConstraint<"$Ddin = $Dd">, 1351 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1352 1353def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 1354 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1355 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 1356 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1357 RegConstraint<"$Sdin = $Sd">, 1358 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1359 // Some single precision VFP instructions may be executed on both NEON and 1360 // VFP pipelines on A8. 1361 let D = VFPNeonA8Domain; 1362} 1363 1364def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1365 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1366 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1367def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1368 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1369 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1370 1371//===----------------------------------------------------------------------===// 1372// Fused FP Multiply-Accumulate Operations. 1373// 1374def VFMAD : ADbI<0b11101, 0b10, 0, 0, 1375 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1376 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 1377 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1378 (f64 DPR:$Ddin)))]>, 1379 RegConstraint<"$Ddin = $Dd">, 1380 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1381 1382def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 1383 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1384 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 1385 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1386 SPR:$Sdin))]>, 1387 RegConstraint<"$Sdin = $Sd">, 1388 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1389 // Some single precision VFP instructions may be executed on both NEON and 1390 // VFP pipelines. 1391} 1392 1393def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1394 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1395 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1396def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1397 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1398 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1399 1400// Match @llvm.fma.* intrinsics 1401// (fma x, y, z) -> (vfms z, x, y) 1402def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 1403 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1404 Requires<[HasVFP4,HasDPVFP]>; 1405def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 1406 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1407 Requires<[HasVFP4]>; 1408 1409def VFMSD : ADbI<0b11101, 0b10, 1, 0, 1410 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1411 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 1412 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1413 (f64 DPR:$Ddin)))]>, 1414 RegConstraint<"$Ddin = $Dd">, 1415 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1416 1417def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 1418 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1419 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 1420 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1421 SPR:$Sdin))]>, 1422 RegConstraint<"$Sdin = $Sd">, 1423 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1424 // Some single precision VFP instructions may be executed on both NEON and 1425 // VFP pipelines. 1426} 1427 1428def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1429 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1430 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1431def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1432 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1433 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1434 1435// Match @llvm.fma.* intrinsics 1436// (fma (fneg x), y, z) -> (vfms z, x, y) 1437def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 1438 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1439 Requires<[HasVFP4,HasDPVFP]>; 1440def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 1441 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1442 Requires<[HasVFP4]>; 1443// (fma x, (fneg y), z) -> (vfms z, x, y) 1444def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)), 1445 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1446 Requires<[HasVFP4,HasDPVFP]>; 1447def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), 1448 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1449 Requires<[HasVFP4]>; 1450 1451def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 1452 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1453 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 1454 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1455 (f64 DPR:$Ddin)))]>, 1456 RegConstraint<"$Ddin = $Dd">, 1457 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1458 1459def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 1460 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1461 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 1462 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1463 SPR:$Sdin))]>, 1464 RegConstraint<"$Sdin = $Sd">, 1465 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1466 // Some single precision VFP instructions may be executed on both NEON and 1467 // VFP pipelines. 1468} 1469 1470def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1471 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1472 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1473def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1474 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1475 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1476 1477// Match @llvm.fma.* intrinsics 1478// (fneg (fma x, y, z)) -> (vfnma z, x, y) 1479def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 1480 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1481 Requires<[HasVFP4,HasDPVFP]>; 1482def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 1483 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1484 Requires<[HasVFP4]>; 1485// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 1486def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 1487 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1488 Requires<[HasVFP4,HasDPVFP]>; 1489def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 1490 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1491 Requires<[HasVFP4]>; 1492 1493def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 1494 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1495 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 1496 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1497 (f64 DPR:$Ddin)))]>, 1498 RegConstraint<"$Ddin = $Dd">, 1499 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1500 1501def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 1502 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1503 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 1504 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1505 RegConstraint<"$Sdin = $Sd">, 1506 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1507 // Some single precision VFP instructions may be executed on both NEON and 1508 // VFP pipelines. 1509} 1510 1511def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1512 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1513 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1514def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1515 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1516 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1517 1518// Match @llvm.fma.* intrinsics 1519 1520// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 1521def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 1522 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1523 Requires<[HasVFP4,HasDPVFP]>; 1524def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 1525 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1526 Requires<[HasVFP4]>; 1527// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 1528def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 1529 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1530 Requires<[HasVFP4,HasDPVFP]>; 1531def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 1532 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1533 Requires<[HasVFP4]>; 1534// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y) 1535def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))), 1536 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1537 Requires<[HasVFP4,HasDPVFP]>; 1538def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))), 1539 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1540 Requires<[HasVFP4]>; 1541 1542//===----------------------------------------------------------------------===// 1543// FP Conditional moves. 1544// 1545 1546let hasSideEffects = 0 in { 1547def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), 1548 IIC_fpUNA64, 1549 [(set (f64 DPR:$Dd), 1550 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>, 1551 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>; 1552 1553def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p), 1554 IIC_fpUNA32, 1555 [(set (f32 SPR:$Sd), 1556 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>, 1557 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>; 1558} // hasSideEffects 1559 1560//===----------------------------------------------------------------------===// 1561// Move from VFP System Register to ARM core register. 1562// 1563 1564class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1565 list<dag> pattern>: 1566 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1567 1568 // Instruction operand. 1569 bits<4> Rt; 1570 1571 let Inst{27-20} = 0b11101111; 1572 let Inst{19-16} = opc19_16; 1573 let Inst{15-12} = Rt; 1574 let Inst{11-8} = 0b1010; 1575 let Inst{7} = 0; 1576 let Inst{6-5} = 0b00; 1577 let Inst{4} = 1; 1578 let Inst{3-0} = 0b0000; 1579} 1580 1581// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 1582// to APSR. 1583let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in 1584def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 1585 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 1586 1587// Application level FPSCR -> GPR 1588let hasSideEffects = 1, Uses = [FPSCR] in 1589def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), 1590 "vmrs", "\t$Rt, fpscr", 1591 [(set GPR:$Rt, (int_arm_get_fpscr))]>; 1592 1593// System level FPEXC, FPSID -> GPR 1594let Uses = [FPSCR] in { 1595 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), 1596 "vmrs", "\t$Rt, fpexc", []>; 1597 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), 1598 "vmrs", "\t$Rt, fpsid", []>; 1599 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins), 1600 "vmrs", "\t$Rt, mvfr0", []>; 1601 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins), 1602 "vmrs", "\t$Rt, mvfr1", []>; 1603 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins), 1604 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>; 1605 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins), 1606 "vmrs", "\t$Rt, fpinst", []>; 1607 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins), 1608 "vmrs", "\t$Rt, fpinst2", []>; 1609} 1610 1611//===----------------------------------------------------------------------===// 1612// Move from ARM core register to VFP System Register. 1613// 1614 1615class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1616 list<dag> pattern>: 1617 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1618 1619 // Instruction operand. 1620 bits<4> src; 1621 1622 // Encode instruction operand. 1623 let Inst{15-12} = src; 1624 1625 let Inst{27-20} = 0b11101110; 1626 let Inst{19-16} = opc19_16; 1627 let Inst{11-8} = 0b1010; 1628 let Inst{7} = 0; 1629 let Inst{4} = 1; 1630} 1631 1632let Defs = [FPSCR] in { 1633 // Application level GPR -> FPSCR 1634 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), 1635 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; 1636 // System level GPR -> FPEXC 1637 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), 1638 "vmsr", "\tfpexc, $src", []>; 1639 // System level GPR -> FPSID 1640 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), 1641 "vmsr", "\tfpsid, $src", []>; 1642 1643 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src), 1644 "vmsr", "\tfpinst, $src", []>; 1645 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src), 1646 "vmsr", "\tfpinst2, $src", []>; 1647} 1648 1649//===----------------------------------------------------------------------===// 1650// Misc. 1651// 1652 1653// Materialize FP immediates. VFP3 only. 1654let isReMaterializable = 1 in { 1655def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 1656 VFPMiscFrm, IIC_fpUNA64, 1657 "vmov", ".f64\t$Dd, $imm", 1658 [(set DPR:$Dd, vfp_f64imm:$imm)]>, 1659 Requires<[HasVFP3,HasDPVFP]> { 1660 bits<5> Dd; 1661 bits<8> imm; 1662 1663 let Inst{27-23} = 0b11101; 1664 let Inst{22} = Dd{4}; 1665 let Inst{21-20} = 0b11; 1666 let Inst{19-16} = imm{7-4}; 1667 let Inst{15-12} = Dd{3-0}; 1668 let Inst{11-9} = 0b101; 1669 let Inst{8} = 1; // Double precision. 1670 let Inst{7-4} = 0b0000; 1671 let Inst{3-0} = imm{3-0}; 1672} 1673 1674def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 1675 VFPMiscFrm, IIC_fpUNA32, 1676 "vmov", ".f32\t$Sd, $imm", 1677 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 1678 bits<5> Sd; 1679 bits<8> imm; 1680 1681 let Inst{27-23} = 0b11101; 1682 let Inst{22} = Sd{0}; 1683 let Inst{21-20} = 0b11; 1684 let Inst{19-16} = imm{7-4}; 1685 let Inst{15-12} = Sd{4-1}; 1686 let Inst{11-9} = 0b101; 1687 let Inst{8} = 0; // Single precision. 1688 let Inst{7-4} = 0b0000; 1689 let Inst{3-0} = imm{3-0}; 1690} 1691} 1692 1693//===----------------------------------------------------------------------===// 1694// Assembler aliases. 1695// 1696// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to 1697// support them all, but supporting at least some of the basics is 1698// good to be friendly. 1699def : VFP2MnemonicAlias<"flds", "vldr">; 1700def : VFP2MnemonicAlias<"fldd", "vldr">; 1701def : VFP2MnemonicAlias<"fmrs", "vmov">; 1702def : VFP2MnemonicAlias<"fmsr", "vmov">; 1703def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 1704def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 1705def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 1706def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 1707def : VFP2MnemonicAlias<"fmrdd", "vmov">; 1708def : VFP2MnemonicAlias<"fmrds", "vmov">; 1709def : VFP2MnemonicAlias<"fmrrd", "vmov">; 1710def : VFP2MnemonicAlias<"fmdrr", "vmov">; 1711def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 1712def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 1713def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 1714def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 1715def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 1716def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 1717def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 1718def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 1719def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 1720def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 1721def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 1722def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 1723def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 1724def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 1725def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 1726def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 1727def : VFP2MnemonicAlias<"fsts", "vstr">; 1728def : VFP2MnemonicAlias<"fstd", "vstr">; 1729def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 1730def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 1731def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 1732def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 1733def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 1734def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 1735def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 1736def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 1737def : VFP2MnemonicAlias<"fmrx", "vmrs">; 1738def : VFP2MnemonicAlias<"fmxr", "vmsr">; 1739 1740// Be friendly and accept the old form of zero-compare 1741def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 1742def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 1743 1744 1745def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>; 1746def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 1747 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1748def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm", 1749 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1750def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 1751 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1752def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm", 1753 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1754 1755// No need for the size suffix on VSQRT. It's implied by the register classes. 1756def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 1757def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 1758 1759// VLDR/VSTR accept an optional type suffix. 1760def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 1761 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1762def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 1763 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1764def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 1765 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1766def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 1767 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1768 1769// VMOV can accept optional 32-bit or less data type suffix suffix. 1770def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 1771 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1772def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 1773 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1774def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 1775 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1776def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 1777 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1778def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 1779 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1780def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 1781 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1782 1783def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 1784 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 1785def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 1786 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 1787 1788// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 1789// VMOVD does. 1790def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 1791 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 1792 1793// FCONSTD/FCONSTS alias for vmov.f64/vmov.f32 1794// These aliases provide added functionality over vmov.f instructions by 1795// allowing users to write assembly containing encoded floating point constants 1796// (e.g. #0x70 vs #1.0). Without these alises there is no way for the 1797// assembler to accept encoded fp constants (but the equivalent fp-literal is 1798// accepted directly by vmovf). 1799def : VFP3InstAlias<"fconstd${p} $Dd, $val", 1800 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>; 1801def : VFP3InstAlias<"fconsts${p} $Sd, $val", 1802 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>; 1803