1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb1 implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb1FrameLowering.h" 15 #include "ARMMachineFunctionInfo.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 21 using namespace llvm; 22 23 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{ 24 const MachineFrameInfo *FFI = MF.getFrameInfo(); 25 unsigned CFSize = FFI->getMaxCallFrameSize(); 26 // It's not always a good idea to include the call frame as part of the 27 // stack frame. ARM (especially Thumb) has small immediate offset to 28 // address the stack frame. So a large call frame can cause poor codegen 29 // and may even makes it impossible to scavenge a register. 30 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 31 return false; 32 33 return !MF.getFrameInfo()->hasVarSizedObjects(); 34 } 35 36 static void 37 emitSPUpdate(MachineBasicBlock &MBB, 38 MachineBasicBlock::iterator &MBBI, 39 const TargetInstrInfo &TII, DebugLoc dl, 40 const Thumb1RegisterInfo &MRI, 41 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 43 MRI, MIFlags); 44 } 45 46 47 void Thumb1FrameLowering:: 48 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 49 MachineBasicBlock::iterator I) const { 50 const Thumb1InstrInfo &TII = 51 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 52 const Thumb1RegisterInfo *RegInfo = 53 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 54 if (!hasReservedCallFrame(MF)) { 55 // If we have alloca, convert as follows: 56 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 57 // ADJCALLSTACKUP -> add, sp, sp, amount 58 MachineInstr *Old = I; 59 DebugLoc dl = Old->getDebugLoc(); 60 unsigned Amount = Old->getOperand(0).getImm(); 61 if (Amount != 0) { 62 // We need to keep the stack aligned properly. To do this, we round the 63 // amount of space needed for the outgoing arguments up to the next 64 // alignment boundary. 65 unsigned Align = getStackAlignment(); 66 Amount = (Amount+Align-1)/Align*Align; 67 68 // Replace the pseudo instruction with a new instruction... 69 unsigned Opc = Old->getOpcode(); 70 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 72 } else { 73 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 75 } 76 } 77 } 78 MBB.erase(I); 79 } 80 81 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const { 82 MachineBasicBlock &MBB = MF.front(); 83 MachineBasicBlock::iterator MBBI = MBB.begin(); 84 MachineFrameInfo *MFI = MF.getFrameInfo(); 85 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 86 const Thumb1RegisterInfo *RegInfo = 87 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 88 const Thumb1InstrInfo &TII = 89 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 90 91 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 92 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align); 93 unsigned NumBytes = MFI->getStackSize(); 94 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 95 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 96 unsigned FramePtr = RegInfo->getFrameRegister(MF); 97 unsigned BasePtr = RegInfo->getBaseRegister(); 98 99 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 100 NumBytes = (NumBytes + 3) & ~3; 101 MFI->setStackSize(NumBytes); 102 103 // Determine the sizes of each callee-save spill areas and record which frame 104 // belongs to which callee-save spill areas. 105 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 106 int FramePtrSpillFI = 0; 107 108 if (ArgRegsSaveSize) 109 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 110 MachineInstr::FrameSetup); 111 112 if (!AFI->hasStackFrame()) { 113 if (NumBytes != 0) 114 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 115 MachineInstr::FrameSetup); 116 return; 117 } 118 119 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 120 unsigned Reg = CSI[i].getReg(); 121 int FI = CSI[i].getFrameIdx(); 122 switch (Reg) { 123 case ARM::R4: 124 case ARM::R5: 125 case ARM::R6: 126 case ARM::R7: 127 case ARM::LR: 128 if (Reg == FramePtr) 129 FramePtrSpillFI = FI; 130 GPRCS1Size += 4; 131 break; 132 case ARM::R8: 133 case ARM::R9: 134 case ARM::R10: 135 case ARM::R11: 136 if (Reg == FramePtr) 137 FramePtrSpillFI = FI; 138 if (STI.isTargetIOS()) 139 GPRCS2Size += 4; 140 else 141 GPRCS1Size += 4; 142 break; 143 default: 144 DPRCSSize += 8; 145 } 146 } 147 148 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { 149 ++MBBI; 150 if (MBBI != MBB.end()) 151 dl = MBBI->getDebugLoc(); 152 } 153 154 // Determine starting offsets of spill areas. 155 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 156 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 157 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 158 bool HasFP = hasFP(MF); 159 if (HasFP) 160 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 161 NumBytes); 162 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 163 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 164 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 165 NumBytes = DPRCSOffset; 166 167 int FramePtrOffsetInBlock = 0; 168 if (tryFoldSPUpdateIntoPushPop(MF, prior(MBBI), NumBytes)) { 169 FramePtrOffsetInBlock = NumBytes; 170 NumBytes = 0; 171 } 172 173 // Adjust FP so it point to the stack slot that contains the previous FP. 174 if (HasFP) { 175 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI) + GPRCS1Size; 176 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) 177 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4) 178 .setMIFlags(MachineInstr::FrameSetup)); 179 if (NumBytes > 508) 180 // If offset is > 508 then sp cannot be adjusted in a single instruction, 181 // try restoring from fp instead. 182 AFI->setShouldRestoreSPFromFP(true); 183 } 184 185 if (NumBytes) 186 // Insert it after all the callee-save spills. 187 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 188 MachineInstr::FrameSetup); 189 190 if (STI.isTargetELF() && HasFP) 191 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 192 AFI->getFramePtrSpillOffset()); 193 194 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 195 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 196 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 197 198 // Thumb1 does not currently support dynamic stack realignment. Report a 199 // fatal error rather then silently generate bad code. 200 if (RegInfo->needsStackRealignment(MF)) 201 report_fatal_error("Dynamic stack realignment not supported for thumb1."); 202 203 // If we need a base pointer, set it up here. It's whatever the value 204 // of the stack pointer is at this point. Any variable size objects 205 // will be allocated after this, so we can still use the base pointer 206 // to reference locals. 207 if (RegInfo->hasBasePointer(MF)) 208 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) 209 .addReg(ARM::SP)); 210 211 // If the frame has variable sized objects then the epilogue must restore 212 // the sp from fp. We can assume there's an FP here since hasFP already 213 // checks for hasVarSizedObjects. 214 if (MFI->hasVarSizedObjects()) 215 AFI->setShouldRestoreSPFromFP(true); 216 } 217 218 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) { 219 for (unsigned i = 0; CSRegs[i]; ++i) 220 if (Reg == CSRegs[i]) 221 return true; 222 return false; 223 } 224 225 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) { 226 if (MI->getOpcode() == ARM::tLDRspi && 227 MI->getOperand(1).isFI() && 228 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) 229 return true; 230 else if (MI->getOpcode() == ARM::tPOP) { 231 // The first two operands are predicates. The last two are 232 // imp-def and imp-use of SP. Check everything in between. 233 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i) 234 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 235 return false; 236 return true; 237 } 238 return false; 239 } 240 241 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, 242 MachineBasicBlock &MBB) const { 243 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 244 assert((MBBI->getOpcode() == ARM::tBX_RET || 245 MBBI->getOpcode() == ARM::tPOP_RET) && 246 "Can only insert epilog into returning blocks"); 247 DebugLoc dl = MBBI->getDebugLoc(); 248 MachineFrameInfo *MFI = MF.getFrameInfo(); 249 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 250 const Thumb1RegisterInfo *RegInfo = 251 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 252 const Thumb1InstrInfo &TII = 253 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 254 255 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 256 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align); 257 int NumBytes = (int)MFI->getStackSize(); 258 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(); 259 unsigned FramePtr = RegInfo->getFrameRegister(MF); 260 261 if (!AFI->hasStackFrame()) { 262 if (NumBytes != 0) 263 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 264 } else { 265 // Unwind MBBI to point to first LDR / VLDRD. 266 if (MBBI != MBB.begin()) { 267 do 268 --MBBI; 269 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 270 if (!isCSRestore(MBBI, CSRegs)) 271 ++MBBI; 272 } 273 274 // Move SP to start of FP callee save spill area. 275 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 276 AFI->getGPRCalleeSavedArea2Size() + 277 AFI->getDPRCalleeSavedAreaSize()); 278 279 if (AFI->shouldRestoreSPFromFP()) { 280 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 281 // Reset SP based on frame pointer only if the stack frame extends beyond 282 // frame pointer stack slot, the target is ELF and the function has FP, or 283 // the target uses var sized objects. 284 if (NumBytes) { 285 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 286 "No scratch register to restore SP from FP!"); 287 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 288 TII, *RegInfo); 289 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 290 ARM::SP) 291 .addReg(ARM::R4)); 292 } else 293 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 294 ARM::SP) 295 .addReg(FramePtr)); 296 } else { 297 if (MBBI->getOpcode() == ARM::tBX_RET && 298 &MBB.front() != MBBI && 299 prior(MBBI)->getOpcode() == ARM::tPOP) { 300 MachineBasicBlock::iterator PMBBI = prior(MBBI); 301 if (!tryFoldSPUpdateIntoPushPop(MF, PMBBI, NumBytes)) 302 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes); 303 } else if (!tryFoldSPUpdateIntoPushPop(MF, MBBI, NumBytes)) 304 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 305 } 306 } 307 308 if (ArgRegsSaveSize) { 309 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore 310 // to LR, and we can't pop the value directly to the PC since 311 // we need to update the SP after popping the value. Therefore, we 312 // pop the old LR into R3 as a temporary. 313 314 // Move back past the callee-saved register restoration 315 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs)) 316 ++MBBI; 317 // Epilogue for vararg functions: pop LR to R3 and branch off it. 318 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) 319 .addReg(ARM::R3, RegState::Define); 320 321 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize); 322 323 MachineInstrBuilder MIB = 324 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) 325 .addReg(ARM::R3, RegState::Kill); 326 AddDefaultPred(MIB); 327 MIB.copyImplicitOps(&*MBBI); 328 // erase the old tBX_RET instruction 329 MBB.erase(MBBI); 330 } 331 } 332 333 bool Thumb1FrameLowering:: 334 spillCalleeSavedRegisters(MachineBasicBlock &MBB, 335 MachineBasicBlock::iterator MI, 336 const std::vector<CalleeSavedInfo> &CSI, 337 const TargetRegisterInfo *TRI) const { 338 if (CSI.empty()) 339 return false; 340 341 DebugLoc DL; 342 MachineFunction &MF = *MBB.getParent(); 343 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 344 345 if (MI != MBB.end()) DL = MI->getDebugLoc(); 346 347 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); 348 AddDefaultPred(MIB); 349 for (unsigned i = CSI.size(); i != 0; --i) { 350 unsigned Reg = CSI[i-1].getReg(); 351 bool isKill = true; 352 353 // Add the callee-saved register as live-in unless it's LR and 354 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 355 // then it's already added to the function and entry block live-in sets. 356 if (Reg == ARM::LR) { 357 MachineFunction &MF = *MBB.getParent(); 358 if (MF.getFrameInfo()->isReturnAddressTaken() && 359 MF.getRegInfo().isLiveIn(Reg)) 360 isKill = false; 361 } 362 363 if (isKill) 364 MBB.addLiveIn(Reg); 365 366 MIB.addReg(Reg, getKillRegState(isKill)); 367 } 368 MIB.setMIFlags(MachineInstr::FrameSetup); 369 return true; 370 } 371 372 bool Thumb1FrameLowering:: 373 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 374 MachineBasicBlock::iterator MI, 375 const std::vector<CalleeSavedInfo> &CSI, 376 const TargetRegisterInfo *TRI) const { 377 if (CSI.empty()) 378 return false; 379 380 MachineFunction &MF = *MBB.getParent(); 381 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 382 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 383 384 bool isVarArg = AFI->getArgRegsSaveSize() > 0; 385 DebugLoc DL = MI->getDebugLoc(); 386 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); 387 AddDefaultPred(MIB); 388 389 bool NumRegs = false; 390 for (unsigned i = CSI.size(); i != 0; --i) { 391 unsigned Reg = CSI[i-1].getReg(); 392 if (Reg == ARM::LR) { 393 // Special epilogue for vararg functions. See emitEpilogue 394 if (isVarArg) 395 continue; 396 Reg = ARM::PC; 397 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); 398 MIB.copyImplicitOps(&*MI); 399 MI = MBB.erase(MI); 400 } 401 MIB.addReg(Reg, getDefRegState(true)); 402 NumRegs = true; 403 } 404 405 // It's illegal to emit pop instruction without operands. 406 if (NumRegs) 407 MBB.insert(MI, &*MIB); 408 else 409 MF.DeleteMachineInstr(MIB); 410 411 return true; 412 } 413