1//===-- MSP430InstrInfo.td - MSP430 Instruction defs -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the MSP430 instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14include "MSP430InstrFormats.td"
15
16//===----------------------------------------------------------------------===//
17// Type Constraints.
18//===----------------------------------------------------------------------===//
19class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
21
22//===----------------------------------------------------------------------===//
23// Type Profiles.
24//===----------------------------------------------------------------------===//
25def SDT_MSP430Call         : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27def SDT_MSP430CallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28def SDT_MSP430Wrapper      : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
29                                                  SDTCisPtrTy<0>]>;
30def SDT_MSP430Cmp          : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
31def SDT_MSP430BrCC         : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
32                                                  SDTCisVT<1, i8>]>;
33def SDT_MSP430SelectCC     : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
34                                                  SDTCisSameAs<1, 2>,
35                                                  SDTCisVT<3, i8>]>;
36def SDT_MSP430Shift        : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
37                                                  SDTCisI8<2>]>;
38
39//===----------------------------------------------------------------------===//
40// MSP430 Specific Node Definitions.
41//===----------------------------------------------------------------------===//
42def MSP430retflag  : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
43                       [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
44def MSP430retiflag : SDNode<"MSP430ISD::RETI_FLAG", SDTNone,
45                       [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
46
47def MSP430rra     : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
48def MSP430rla     : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
49def MSP430rrc     : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>;
50
51def MSP430call    : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
52                     [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
53def MSP430callseq_start :
54                 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
55                        [SDNPHasChain, SDNPOutGlue]>;
56def MSP430callseq_end :
57                 SDNode<"ISD::CALLSEQ_END",   SDT_MSP430CallSeqEnd,
58                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
59def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
60def MSP430cmp     : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutGlue]>;
61def MSP430brcc    : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC,
62                            [SDNPHasChain, SDNPInGlue]>;
63def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC,
64                            [SDNPInGlue]>;
65def MSP430shl     : SDNode<"MSP430ISD::SHL", SDT_MSP430Shift, []>;
66def MSP430sra     : SDNode<"MSP430ISD::SRA", SDT_MSP430Shift, []>;
67def MSP430srl     : SDNode<"MSP430ISD::SRL", SDT_MSP430Shift, []>;
68
69//===----------------------------------------------------------------------===//
70// MSP430 Operand Definitions.
71//===----------------------------------------------------------------------===//
72
73// Address operands
74def memsrc : Operand<i16> {
75  let PrintMethod = "printSrcMemOperand";
76  let MIOperandInfo = (ops GR16, i16imm);
77}
78
79def memdst : Operand<i16> {
80  let PrintMethod = "printSrcMemOperand";
81  let MIOperandInfo = (ops GR16, i16imm);
82}
83
84// Short jump targets have OtherVT type and are printed as pcrel imm values.
85def jmptarget : Operand<OtherVT> {
86  let PrintMethod = "printPCRelImmOperand";
87}
88
89// Operand for printing out a condition code.
90def cc : Operand<i8> {
91  let PrintMethod = "printCCOperand";
92}
93
94//===----------------------------------------------------------------------===//
95// MSP430 Complex Pattern Definitions.
96//===----------------------------------------------------------------------===//
97
98def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
99
100//===----------------------------------------------------------------------===//
101// Pattern Fragments
102def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
103def  extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
104def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
105  return N->hasOneUse();
106}]>;
107//===----------------------------------------------------------------------===//
108// Instruction list..
109
110// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
111// a stack adjustment and the codegen must know that they may modify the stack
112// pointer before prolog-epilog rewriting occurs.
113// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
114// sub / add which can clobber SR.
115let Defs = [SP, SR], Uses = [SP] in {
116def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
117                              "#ADJCALLSTACKDOWN",
118                              [(MSP430callseq_start timm:$amt)]>;
119def ADJCALLSTACKUP   : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
120                              "#ADJCALLSTACKUP",
121                              [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
122}
123
124let usesCustomInserter = 1 in {
125  def Select8  : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
126                        "# Select8 PSEUDO",
127                        [(set GR8:$dst,
128                          (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>;
129  def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
130                        "# Select16 PSEUDO",
131                        [(set GR16:$dst,
132                          (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>;
133  let Defs = [SR] in {
134  def Shl8     : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
135                        "# Shl8 PSEUDO",
136                        [(set GR8:$dst, (MSP430shl GR8:$src, GR8:$cnt))]>;
137  def Shl16    : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
138                        "# Shl16 PSEUDO",
139                        [(set GR16:$dst, (MSP430shl GR16:$src, GR8:$cnt))]>;
140  def Sra8     : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
141                        "# Sra8 PSEUDO",
142                        [(set GR8:$dst, (MSP430sra GR8:$src, GR8:$cnt))]>;
143  def Sra16    : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
144                        "# Sra16 PSEUDO",
145                        [(set GR16:$dst, (MSP430sra GR16:$src, GR8:$cnt))]>;
146  def Srl8     : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
147                        "# Srl8 PSEUDO",
148                        [(set GR8:$dst, (MSP430srl GR8:$src, GR8:$cnt))]>;
149  def Srl16    : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
150                        "# Srl16 PSEUDO",
151                        [(set GR16:$dst, (MSP430srl GR16:$src, GR8:$cnt))]>;
152
153  }
154}
155
156let hasSideEffects = 0 in
157def NOP : Pseudo<(outs), (ins), "nop", []>;
158
159//===----------------------------------------------------------------------===//
160//  Control Flow Instructions...
161//
162
163// FIXME: Provide proper encoding!
164let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
165  def RET  : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
166                     (outs), (ins), "ret",  [(MSP430retflag)]>;
167  def RETI : II16r<0x0, (outs), (ins), "reti", [(MSP430retiflag)]>;
168}
169
170let isBranch = 1, isTerminator = 1 in {
171
172// FIXME: expand opcode & cond field for branches!
173
174// Direct branch
175let isBarrier = 1 in {
176  // Short branch
177  def JMP : CJForm<0, 0, (outs), (ins jmptarget:$dst),
178                   "jmp\t$dst",
179                   [(br bb:$dst)]>;
180  let isIndirectBranch = 1 in {
181    // Long branches
182    def Bi  : I16ri<0, (outs), (ins i16imm:$brdst),
183                    "br\t$brdst",
184                    [(brind tblockaddress:$brdst)]>;
185    def Br  : I16rr<0, (outs), (ins GR16:$brdst),
186                    "br\t$brdst",
187                    [(brind GR16:$brdst)]>;
188    def Bm  : I16rm<0, (outs), (ins memsrc:$brdst),
189                    "br\t$brdst",
190                    [(brind (load addr:$brdst))]>;
191  }
192}
193
194// Conditional branches
195let Uses = [SR] in
196  def JCC : CJForm<0, 0,
197                   (outs), (ins jmptarget:$dst, cc:$cc),
198                   "j$cc\t$dst",
199                   [(MSP430brcc bb:$dst, imm:$cc)]>;
200} // isBranch, isTerminator
201
202//===----------------------------------------------------------------------===//
203//  Call Instructions...
204//
205let isCall = 1 in
206  // All calls clobber the non-callee saved registers. SPW is marked as
207  // a use to prevent stack-pointer assignments that appear immediately
208  // before calls from potentially appearing dead. Uses for argument
209  // registers are added manually.
210  let Defs = [R12, R13, R14, R15, SR],
211      Uses = [SP] in {
212    def CALLi     : II16i<0x0,
213                          (outs), (ins i16imm:$dst),
214                          "call\t$dst", [(MSP430call imm:$dst)]>;
215    def CALLr     : II16r<0x0,
216                          (outs), (ins GR16:$dst),
217                          "call\t$dst", [(MSP430call GR16:$dst)]>;
218    def CALLm     : II16m<0x0,
219                          (outs), (ins memsrc:$dst),
220                          "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
221  }
222
223
224//===----------------------------------------------------------------------===//
225//  Miscellaneous Instructions...
226//
227let Defs = [SP], Uses = [SP], hasSideEffects=0 in {
228let mayLoad = 1 in
229def POP16r   : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
230                       (outs GR16:$reg), (ins), "pop.w\t$reg", []>;
231
232let mayStore = 1 in
233def PUSH16r  : II16r<0x0,
234                     (outs), (ins GR16:$reg), "push.w\t$reg",[]>;
235}
236
237//===----------------------------------------------------------------------===//
238// Move Instructions
239
240// FIXME: Provide proper encoding!
241let hasSideEffects = 0 in {
242def MOV8rr  : I8rr<0x0,
243                   (outs GR8:$dst), (ins GR8:$src),
244                   "mov.b\t{$src, $dst}",
245                   []>;
246def MOV16rr : I16rr<0x0,
247                    (outs GR16:$dst), (ins GR16:$src),
248                    "mov.w\t{$src, $dst}",
249                    []>;
250}
251
252// FIXME: Provide proper encoding!
253let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
254def MOV8ri  : I8ri<0x0,
255                   (outs GR8:$dst), (ins i8imm:$src),
256                   "mov.b\t{$src, $dst}",
257                   [(set GR8:$dst, imm:$src)]>;
258def MOV16ri : I16ri<0x0,
259                    (outs GR16:$dst), (ins i16imm:$src),
260                    "mov.w\t{$src, $dst}",
261                    [(set GR16:$dst, imm:$src)]>;
262}
263
264let canFoldAsLoad = 1, isReMaterializable = 1 in {
265def MOV8rm  : I8rm<0x0,
266                   (outs GR8:$dst), (ins memsrc:$src),
267                   "mov.b\t{$src, $dst}",
268                   [(set GR8:$dst, (load addr:$src))]>;
269def MOV16rm : I16rm<0x0,
270                    (outs GR16:$dst), (ins memsrc:$src),
271                    "mov.w\t{$src, $dst}",
272                    [(set GR16:$dst, (load addr:$src))]>;
273}
274
275def MOVZX16rr8 : I8rr<0x0,
276                      (outs GR16:$dst), (ins GR8:$src),
277                      "mov.b\t{$src, $dst}",
278                      [(set GR16:$dst, (zext GR8:$src))]>;
279def MOVZX16rm8 : I8rm<0x0,
280                      (outs GR16:$dst), (ins memsrc:$src),
281                      "mov.b\t{$src, $dst}",
282                      [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
283
284let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in {
285def MOV8rm_POST  : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
286                         (outs GR8:$dst, GR16:$base_wb), (ins GR16:$base),
287                         "mov.b\t{@$base+, $dst}", []>;
288def MOV16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
289                           (outs GR16:$dst, GR16:$base_wb), (ins GR16:$base),
290                           "mov.w\t{@$base+, $dst}", []>;
291}
292
293// Any instruction that defines a 8-bit result leaves the high half of the
294// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
295// be copying from a truncate, but any other 8-bit operation will zero-extend
296// up to 16 bits.
297def def8 : PatLeaf<(i8 GR8:$src), [{
298  return N->getOpcode() != ISD::TRUNCATE &&
299         N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
300         N->getOpcode() != ISD::CopyFromReg;
301}]>;
302
303// In the case of a 8-bit def that is known to implicitly zero-extend,
304// we can use a SUBREG_TO_REG.
305def : Pat<(i16 (zext def8:$src)),
306          (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
307
308def MOV8mi  : I8mi<0x0,
309                   (outs), (ins memdst:$dst, i8imm:$src),
310                   "mov.b\t{$src, $dst}",
311                   [(store (i8 imm:$src), addr:$dst)]>;
312def MOV16mi : I16mi<0x0,
313                    (outs), (ins memdst:$dst, i16imm:$src),
314                    "mov.w\t{$src, $dst}",
315                    [(store (i16 imm:$src), addr:$dst)]>;
316
317def MOV8mr  : I8mr<0x0,
318                   (outs), (ins memdst:$dst, GR8:$src),
319                   "mov.b\t{$src, $dst}",
320                   [(store GR8:$src, addr:$dst)]>;
321def MOV16mr : I16mr<0x0,
322                    (outs), (ins memdst:$dst, GR16:$src),
323                    "mov.w\t{$src, $dst}",
324                    [(store GR16:$src, addr:$dst)]>;
325
326def MOV8mm  : I8mm<0x0,
327                   (outs), (ins memdst:$dst, memsrc:$src),
328                   "mov.b\t{$src, $dst}",
329                   [(store (i8 (load addr:$src)), addr:$dst)]>;
330def MOV16mm : I16mm<0x0,
331                    (outs), (ins memdst:$dst, memsrc:$src),
332                    "mov.w\t{$src, $dst}",
333                    [(store (i16 (load addr:$src)), addr:$dst)]>;
334
335//===----------------------------------------------------------------------===//
336// Arithmetic Instructions
337
338let Constraints = "$src = $dst" in {
339
340let Defs = [SR] in {
341
342let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
343
344def ADD8rr  : I8rr<0x0,
345                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
346                   "add.b\t{$src2, $dst}",
347                   [(set GR8:$dst, (add GR8:$src, GR8:$src2)),
348                    (implicit SR)]>;
349def ADD16rr : I16rr<0x0,
350                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
351                    "add.w\t{$src2, $dst}",
352                    [(set GR16:$dst, (add GR16:$src, GR16:$src2)),
353                     (implicit SR)]>;
354}
355
356def ADD8rm  : I8rm<0x0,
357                   (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
358                   "add.b\t{$src2, $dst}",
359                   [(set GR8:$dst, (add GR8:$src, (load addr:$src2))),
360                    (implicit SR)]>;
361def ADD16rm : I16rm<0x0,
362                    (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
363                    "add.w\t{$src2, $dst}",
364                    [(set GR16:$dst, (add GR16:$src, (load addr:$src2))),
365                     (implicit SR)]>;
366
367let mayLoad = 1, hasExtraDefRegAllocReq = 1,
368Constraints = "$base = $base_wb, $src = $dst" in {
369def ADD8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
370                         (outs GR8:$dst, GR16:$base_wb),
371                         (ins GR8:$src, GR16:$base),
372                         "add.b\t{@$base+, $dst}", []>;
373def ADD16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
374                           (outs GR16:$dst, GR16:$base_wb),
375                           (ins GR16:$src, GR16:$base),
376                          "add.w\t{@$base+, $dst}", []>;
377}
378
379
380def ADD8ri  : I8ri<0x0,
381                   (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
382                   "add.b\t{$src2, $dst}",
383                   [(set GR8:$dst, (add GR8:$src, imm:$src2)),
384                    (implicit SR)]>;
385def ADD16ri : I16ri<0x0,
386                    (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
387                    "add.w\t{$src2, $dst}",
388                    [(set GR16:$dst, (add GR16:$src, imm:$src2)),
389                     (implicit SR)]>;
390
391let Constraints = "" in {
392def ADD8mr  : I8mr<0x0,
393                   (outs), (ins memdst:$dst, GR8:$src),
394                   "add.b\t{$src, $dst}",
395                   [(store (add (load addr:$dst), GR8:$src), addr:$dst),
396                    (implicit SR)]>;
397def ADD16mr : I16mr<0x0,
398                    (outs), (ins memdst:$dst, GR16:$src),
399                    "add.w\t{$src, $dst}",
400                    [(store (add (load addr:$dst), GR16:$src), addr:$dst),
401                     (implicit SR)]>;
402
403def ADD8mi  : I8mi<0x0,
404                   (outs), (ins memdst:$dst, i8imm:$src),
405                   "add.b\t{$src, $dst}",
406                   [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
407                    (implicit SR)]>;
408def ADD16mi : I16mi<0x0,
409                    (outs), (ins memdst:$dst, i16imm:$src),
410                    "add.w\t{$src, $dst}",
411                    [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
412                     (implicit SR)]>;
413
414def ADD8mm  : I8mm<0x0,
415                   (outs), (ins memdst:$dst, memsrc:$src),
416                   "add.b\t{$src, $dst}",
417                   [(store (add (load addr:$dst),
418                                (i8 (load addr:$src))), addr:$dst),
419                    (implicit SR)]>;
420def ADD16mm : I16mm<0x0,
421                    (outs), (ins memdst:$dst, memsrc:$src),
422                    "add.w\t{$src, $dst}",
423                    [(store (add (load addr:$dst),
424                                  (i16 (load addr:$src))), addr:$dst),
425                     (implicit SR)]>;
426}
427
428let Uses = [SR] in {
429
430let isCommutable = 1 in { // X = ADDC Y, Z  == X = ADDC Z, Y
431def ADC8rr  : I8rr<0x0,
432                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
433                   "addc.b\t{$src2, $dst}",
434                   [(set GR8:$dst, (adde GR8:$src, GR8:$src2)),
435                    (implicit SR)]>;
436def ADC16rr : I16rr<0x0,
437                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
438                    "addc.w\t{$src2, $dst}",
439                    [(set GR16:$dst, (adde GR16:$src, GR16:$src2)),
440                     (implicit SR)]>;
441} // isCommutable
442
443def ADC8ri  : I8ri<0x0,
444                   (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
445                   "addc.b\t{$src2, $dst}",
446                   [(set GR8:$dst, (adde GR8:$src, imm:$src2)),
447                    (implicit SR)]>;
448def ADC16ri : I16ri<0x0,
449                    (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
450                    "addc.w\t{$src2, $dst}",
451                    [(set GR16:$dst, (adde GR16:$src, imm:$src2)),
452                     (implicit SR)]>;
453
454def ADC8rm  : I8rm<0x0,
455                   (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
456                   "addc.b\t{$src2, $dst}",
457                   [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))),
458                    (implicit SR)]>;
459def ADC16rm : I16rm<0x0,
460                    (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
461                    "addc.w\t{$src2, $dst}",
462                    [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))),
463                     (implicit SR)]>;
464
465let Constraints = "" in {
466def ADC8mr  : I8mr<0x0,
467                   (outs), (ins memdst:$dst, GR8:$src),
468                   "addc.b\t{$src, $dst}",
469                   [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
470                    (implicit SR)]>;
471def ADC16mr : I16mr<0x0,
472                    (outs), (ins memdst:$dst, GR16:$src),
473                    "addc.w\t{$src, $dst}",
474                    [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
475                     (implicit SR)]>;
476
477def ADC8mi  : I8mi<0x0,
478                   (outs), (ins memdst:$dst, i8imm:$src),
479                   "addc.b\t{$src, $dst}",
480                   [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
481                    (implicit SR)]>;
482def ADC16mi : I16mi<0x0,
483                    (outs), (ins memdst:$dst, i16imm:$src),
484                    "addc.w\t{$src, $dst}",
485                    [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
486                     (implicit SR)]>;
487
488def ADC8mm  : I8mm<0x0,
489                   (outs), (ins memdst:$dst, memsrc:$src),
490                   "addc.b\t{$src, $dst}",
491                   [(store (adde (load addr:$dst),
492                                 (i8 (load addr:$src))), addr:$dst),
493                    (implicit SR)]>;
494def ADC16mm : I8mm<0x0,
495                   (outs), (ins memdst:$dst, memsrc:$src),
496                   "addc.w\t{$src, $dst}",
497                   [(store (adde (load addr:$dst),
498                                 (i16 (load addr:$src))), addr:$dst),
499                    (implicit SR)]>;
500}
501
502} // Uses = [SR]
503
504let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
505def AND8rr  : I8rr<0x0,
506                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
507                   "and.b\t{$src2, $dst}",
508                   [(set GR8:$dst, (and GR8:$src, GR8:$src2)),
509                    (implicit SR)]>;
510def AND16rr : I16rr<0x0,
511                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
512                    "and.w\t{$src2, $dst}",
513                    [(set GR16:$dst, (and GR16:$src, GR16:$src2)),
514                     (implicit SR)]>;
515}
516
517def AND8ri  : I8ri<0x0,
518                   (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
519                   "and.b\t{$src2, $dst}",
520                   [(set GR8:$dst, (and GR8:$src, imm:$src2)),
521                    (implicit SR)]>;
522def AND16ri : I16ri<0x0,
523                    (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
524                    "and.w\t{$src2, $dst}",
525                    [(set GR16:$dst, (and GR16:$src, imm:$src2)),
526                     (implicit SR)]>;
527
528def AND8rm  : I8rm<0x0,
529                   (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
530                   "and.b\t{$src2, $dst}",
531                   [(set GR8:$dst, (and GR8:$src, (load addr:$src2))),
532                    (implicit SR)]>;
533def AND16rm : I16rm<0x0,
534                    (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
535                    "and.w\t{$src2, $dst}",
536                    [(set GR16:$dst, (and GR16:$src, (load addr:$src2))),
537                     (implicit SR)]>;
538
539let mayLoad = 1, hasExtraDefRegAllocReq = 1,
540Constraints = "$base = $base_wb, $src = $dst" in {
541def AND8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
542                         (outs GR8:$dst, GR16:$base_wb),
543                         (ins GR8:$src, GR16:$base),
544                         "and.b\t{@$base+, $dst}", []>;
545def AND16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
546                           (outs GR16:$dst, GR16:$base_wb),
547                           (ins GR16:$src, GR16:$base),
548                           "and.w\t{@$base+, $dst}", []>;
549}
550
551let Constraints = "" in {
552def AND8mr  : I8mr<0x0,
553                   (outs), (ins memdst:$dst, GR8:$src),
554                   "and.b\t{$src, $dst}",
555                   [(store (and (load addr:$dst), GR8:$src), addr:$dst),
556                    (implicit SR)]>;
557def AND16mr : I16mr<0x0,
558                    (outs), (ins memdst:$dst, GR16:$src),
559                    "and.w\t{$src, $dst}",
560                    [(store (and (load addr:$dst), GR16:$src), addr:$dst),
561                     (implicit SR)]>;
562
563def AND8mi  : I8mi<0x0,
564                   (outs), (ins memdst:$dst, i8imm:$src),
565                   "and.b\t{$src, $dst}",
566                   [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
567                    (implicit SR)]>;
568def AND16mi : I16mi<0x0,
569                    (outs), (ins memdst:$dst, i16imm:$src),
570                    "and.w\t{$src, $dst}",
571                    [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
572                     (implicit SR)]>;
573
574def AND8mm  : I8mm<0x0,
575                   (outs), (ins memdst:$dst, memsrc:$src),
576                   "and.b\t{$src, $dst}",
577                   [(store (and (load addr:$dst),
578                                (i8 (load addr:$src))), addr:$dst),
579                    (implicit SR)]>;
580def AND16mm : I16mm<0x0,
581                    (outs), (ins memdst:$dst, memsrc:$src),
582                    "and.w\t{$src, $dst}",
583                    [(store (and (load addr:$dst),
584                                 (i16 (load addr:$src))), addr:$dst),
585                     (implicit SR)]>;
586}
587
588let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
589def OR8rr  : I8rr<0x0,
590                  (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
591                  "bis.b\t{$src2, $dst}",
592                  [(set GR8:$dst, (or GR8:$src, GR8:$src2))]>;
593def OR16rr : I16rr<0x0,
594                   (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
595                   "bis.w\t{$src2, $dst}",
596                   [(set GR16:$dst, (or GR16:$src, GR16:$src2))]>;
597}
598
599def OR8ri  : I8ri<0x0,
600                  (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
601                  "bis.b\t{$src2, $dst}",
602                  [(set GR8:$dst, (or GR8:$src, imm:$src2))]>;
603def OR16ri : I16ri<0x0,
604                   (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
605                   "bis.w\t{$src2, $dst}",
606                   [(set GR16:$dst, (or GR16:$src, imm:$src2))]>;
607
608def OR8rm  : I8rm<0x0,
609                  (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
610                  "bis.b\t{$src2, $dst}",
611                  [(set GR8:$dst, (or GR8:$src, (load addr:$src2)))]>;
612def OR16rm : I16rm<0x0,
613                   (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
614                   "bis.w\t{$src2, $dst}",
615                   [(set GR16:$dst, (or GR16:$src, (load addr:$src2)))]>;
616
617let mayLoad = 1, hasExtraDefRegAllocReq = 1,
618Constraints = "$base = $base_wb, $src = $dst" in {
619def OR8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
620                        (outs GR8:$dst, GR16:$base_wb),
621                        (ins GR8:$src, GR16:$base),
622                        "bis.b\t{@$base+, $dst}", []>;
623def OR16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
624                          (outs GR16:$dst, GR16:$base_wb),
625                          (ins GR16:$src, GR16:$base),
626                          "bis.w\t{@$base+, $dst}", []>;
627}
628
629let Constraints = "" in {
630def OR8mr  : I8mr<0x0,
631                  (outs), (ins memdst:$dst, GR8:$src),
632                  "bis.b\t{$src, $dst}",
633                  [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
634def OR16mr : I16mr<0x0,
635                   (outs), (ins memdst:$dst, GR16:$src),
636                   "bis.w\t{$src, $dst}",
637                   [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
638
639def OR8mi  : I8mi<0x0,
640                  (outs), (ins memdst:$dst, i8imm:$src),
641                  "bis.b\t{$src, $dst}",
642                  [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
643def OR16mi : I16mi<0x0,
644                   (outs), (ins memdst:$dst, i16imm:$src),
645                   "bis.w\t{$src, $dst}",
646                   [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
647
648def OR8mm  : I8mm<0x0,
649                  (outs), (ins memdst:$dst, memsrc:$src),
650                  "bis.b\t{$src, $dst}",
651                  [(store (or (i8 (load addr:$dst)),
652                              (i8 (load addr:$src))), addr:$dst)]>;
653def OR16mm : I16mm<0x0,
654                   (outs), (ins memdst:$dst, memsrc:$src),
655                   "bis.w\t{$src, $dst}",
656                   [(store (or (i16 (load addr:$dst)),
657                               (i16 (load addr:$src))), addr:$dst)]>;
658}
659
660// bic does not modify condition codes
661def BIC8rr :  I8rr<0x0,
662                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
663                   "bic.b\t{$src2, $dst}",
664                   [(set GR8:$dst, (and GR8:$src, (not GR8:$src2)))]>;
665def BIC16rr : I16rr<0x0,
666                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
667                    "bic.w\t{$src2, $dst}",
668                    [(set GR16:$dst, (and GR16:$src, (not GR16:$src2)))]>;
669
670def BIC8rm :  I8rm<0x0,
671                   (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
672                   "bic.b\t{$src2, $dst}",
673                    [(set GR8:$dst, (and GR8:$src, (not (i8 (load addr:$src2)))))]>;
674def BIC16rm : I16rm<0x0,
675                    (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
676                    "bic.w\t{$src2, $dst}",
677                    [(set GR16:$dst, (and GR16:$src, (not (i16 (load addr:$src2)))))]>;
678
679let Constraints = "" in {
680def BIC8mr :  I8mr<0x0,
681                   (outs), (ins memdst:$dst, GR8:$src),
682                   "bic.b\t{$src, $dst}",
683                   [(store (and (load addr:$dst), (not GR8:$src)), addr:$dst)]>;
684def BIC16mr : I16mr<0x0,
685                    (outs), (ins memdst:$dst, GR16:$src),
686                    "bic.w\t{$src, $dst}",
687                    [(store (and (load addr:$dst), (not GR16:$src)), addr:$dst)]>;
688
689def BIC8mm :  I8mm<0x0,
690                   (outs), (ins memdst:$dst, memsrc:$src),
691                   "bic.b\t{$src, $dst}",
692                   [(store (and (load addr:$dst),
693                                (not (i8 (load addr:$src)))), addr:$dst)]>;
694def BIC16mm : I16mm<0x0,
695                    (outs), (ins memdst:$dst, memsrc:$src),
696                    "bic.w\t{$src, $dst}",
697                    [(store (and (load addr:$dst),
698                                 (not (i16 (load addr:$src)))), addr:$dst)]>;
699}
700
701let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
702def XOR8rr  : I8rr<0x0,
703                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
704                   "xor.b\t{$src2, $dst}",
705                   [(set GR8:$dst, (xor GR8:$src, GR8:$src2)),
706                    (implicit SR)]>;
707def XOR16rr : I16rr<0x0,
708                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
709                    "xor.w\t{$src2, $dst}",
710                    [(set GR16:$dst, (xor GR16:$src, GR16:$src2)),
711                     (implicit SR)]>;
712}
713
714def XOR8ri  : I8ri<0x0,
715                   (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
716                   "xor.b\t{$src2, $dst}",
717                   [(set GR8:$dst, (xor GR8:$src, imm:$src2)),
718                    (implicit SR)]>;
719def XOR16ri : I16ri<0x0,
720                    (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
721                    "xor.w\t{$src2, $dst}",
722                    [(set GR16:$dst, (xor GR16:$src, imm:$src2)),
723                     (implicit SR)]>;
724
725def XOR8rm  : I8rm<0x0,
726                   (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
727                   "xor.b\t{$src2, $dst}",
728                   [(set GR8:$dst, (xor GR8:$src, (load addr:$src2))),
729                    (implicit SR)]>;
730def XOR16rm : I16rm<0x0,
731                    (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
732                    "xor.w\t{$src2, $dst}",
733                    [(set GR16:$dst, (xor GR16:$src, (load addr:$src2))),
734                     (implicit SR)]>;
735
736let mayLoad = 1, hasExtraDefRegAllocReq = 1,
737Constraints = "$base = $base_wb, $src = $dst" in {
738def XOR8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
739                         (outs GR8:$dst, GR16:$base_wb),
740                         (ins GR8:$src, GR16:$base),
741                         "xor.b\t{@$base+, $dst}", []>;
742def XOR16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
743                           (outs GR16:$dst, GR16:$base_wb),
744                           (ins GR16:$src, GR16:$base),
745                           "xor.w\t{@$base+, $dst}", []>;
746}
747
748let Constraints = "" in {
749def XOR8mr  : I8mr<0x0,
750                   (outs), (ins memdst:$dst, GR8:$src),
751                   "xor.b\t{$src, $dst}",
752                   [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
753                    (implicit SR)]>;
754def XOR16mr : I16mr<0x0,
755                    (outs), (ins memdst:$dst, GR16:$src),
756                    "xor.w\t{$src, $dst}",
757                    [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
758                     (implicit SR)]>;
759
760def XOR8mi  : I8mi<0x0,
761                   (outs), (ins memdst:$dst, i8imm:$src),
762                   "xor.b\t{$src, $dst}",
763                   [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
764                    (implicit SR)]>;
765def XOR16mi : I16mi<0x0,
766                    (outs), (ins memdst:$dst, i16imm:$src),
767                    "xor.w\t{$src, $dst}",
768                    [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
769                     (implicit SR)]>;
770
771def XOR8mm  : I8mm<0x0,
772                   (outs), (ins memdst:$dst, memsrc:$src),
773                   "xor.b\t{$src, $dst}",
774                   [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
775                    (implicit SR)]>;
776def XOR16mm : I16mm<0x0,
777                    (outs), (ins memdst:$dst, memsrc:$src),
778                    "xor.w\t{$src, $dst}",
779                    [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
780                     (implicit SR)]>;
781}
782
783
784def SUB8rr  : I8rr<0x0,
785                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
786                   "sub.b\t{$src2, $dst}",
787                   [(set GR8:$dst, (sub GR8:$src, GR8:$src2)),
788                    (implicit SR)]>;
789def SUB16rr : I16rr<0x0,
790                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
791                    "sub.w\t{$src2, $dst}",
792                    [(set GR16:$dst, (sub GR16:$src, GR16:$src2)),
793                     (implicit SR)]>;
794
795def SUB8ri  : I8ri<0x0,
796                   (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
797                   "sub.b\t{$src2, $dst}",
798                   [(set GR8:$dst, (sub GR8:$src, imm:$src2)),
799                    (implicit SR)]>;
800def SUB16ri : I16ri<0x0,
801                    (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
802                    "sub.w\t{$src2, $dst}",
803                    [(set GR16:$dst, (sub GR16:$src, imm:$src2)),
804                     (implicit SR)]>;
805
806def SUB8rm  : I8rm<0x0,
807                   (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
808                   "sub.b\t{$src2, $dst}",
809                   [(set GR8:$dst, (sub GR8:$src, (load addr:$src2))),
810                    (implicit SR)]>;
811def SUB16rm : I16rm<0x0,
812                    (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
813                    "sub.w\t{$src2, $dst}",
814                    [(set GR16:$dst, (sub GR16:$src, (load addr:$src2))),
815                     (implicit SR)]>;
816
817let mayLoad = 1, hasExtraDefRegAllocReq = 1,
818Constraints = "$base = $base_wb, $src = $dst" in {
819def SUB8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
820                         (outs GR8:$dst, GR16:$base_wb),
821                         (ins GR8:$src, GR16:$base),
822                         "sub.b\t{@$base+, $dst}", []>;
823def SUB16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
824                          (outs GR16:$dst, GR16:$base_wb),
825                          (ins GR16:$src, GR16:$base),
826                          "sub.w\t{@$base+, $dst}", []>;
827}
828
829let Constraints = "" in {
830def SUB8mr  : I8mr<0x0,
831                   (outs), (ins memdst:$dst, GR8:$src),
832                   "sub.b\t{$src, $dst}",
833                   [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
834                    (implicit SR)]>;
835def SUB16mr : I16mr<0x0,
836                    (outs), (ins memdst:$dst, GR16:$src),
837                    "sub.w\t{$src, $dst}",
838                    [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
839                     (implicit SR)]>;
840
841def SUB8mi  : I8mi<0x0,
842                   (outs), (ins memdst:$dst, i8imm:$src),
843                   "sub.b\t{$src, $dst}",
844                   [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
845                    (implicit SR)]>;
846def SUB16mi : I16mi<0x0,
847                    (outs), (ins memdst:$dst, i16imm:$src),
848                    "sub.w\t{$src, $dst}",
849                    [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
850                     (implicit SR)]>;
851
852def SUB8mm  : I8mm<0x0,
853                   (outs), (ins memdst:$dst, memsrc:$src),
854                   "sub.b\t{$src, $dst}",
855                   [(store (sub (load addr:$dst),
856                                (i8 (load addr:$src))), addr:$dst),
857                    (implicit SR)]>;
858def SUB16mm : I16mm<0x0,
859                    (outs), (ins memdst:$dst, memsrc:$src),
860                    "sub.w\t{$src, $dst}",
861                    [(store (sub (load addr:$dst),
862                                 (i16 (load addr:$src))), addr:$dst),
863                     (implicit SR)]>;
864}
865
866let Uses = [SR] in {
867def SBC8rr  : I8rr<0x0,
868                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
869                   "subc.b\t{$src2, $dst}",
870                   [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
871                    (implicit SR)]>;
872def SBC16rr : I16rr<0x0,
873                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
874                    "subc.w\t{$src2, $dst}",
875                    [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
876                     (implicit SR)]>;
877
878def SBC8ri  : I8ri<0x0,
879                   (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
880                   "subc.b\t{$src2, $dst}",
881                   [(set GR8:$dst, (sube GR8:$src, imm:$src2)),
882                    (implicit SR)]>;
883def SBC16ri : I16ri<0x0,
884                    (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
885                    "subc.w\t{$src2, $dst}",
886                    [(set GR16:$dst, (sube GR16:$src, imm:$src2)),
887                     (implicit SR)]>;
888
889def SBC8rm  : I8rm<0x0,
890                   (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
891                   "subc.b\t{$src2, $dst}",
892                   [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
893                    (implicit SR)]>;
894def SBC16rm : I16rm<0x0,
895                    (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
896                    "subc.w\t{$src2, $dst}",
897                    [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
898                     (implicit SR)]>;
899
900let Constraints = "" in {
901def SBC8mr  : I8mr<0x0,
902                   (outs), (ins memdst:$dst, GR8:$src),
903                   "subc.b\t{$src, $dst}",
904                  [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
905                   (implicit SR)]>;
906def SBC16mr : I16mr<0x0,
907                    (outs), (ins memdst:$dst, GR16:$src),
908                    "subc.w\t{$src, $dst}",
909                    [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
910                     (implicit SR)]>;
911
912def SBC8mi  : I8mi<0x0,
913                   (outs), (ins memdst:$dst, i8imm:$src),
914                   "subc.b\t{$src, $dst}",
915                   [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
916                    (implicit SR)]>;
917def SBC16mi : I16mi<0x0,
918                    (outs), (ins memdst:$dst, i16imm:$src),
919                    "subc.w\t{$src, $dst}",
920                    [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
921                     (implicit SR)]>;
922
923def SBC8mm  : I8mm<0x0,
924                   (outs), (ins memdst:$dst, memsrc:$src),
925                   "subc.b\t{$src, $dst}",
926                   [(store (sube (load addr:$dst),
927                                 (i8 (load addr:$src))), addr:$dst),
928                    (implicit SR)]>;
929def SBC16mm : I16mm<0x0,
930                    (outs), (ins memdst:$dst, memsrc:$src),
931                    "subc.w\t{$src, $dst}",
932                    [(store (sube (load addr:$dst),
933                            (i16 (load addr:$src))), addr:$dst),
934                     (implicit SR)]>;
935}
936
937} // Uses = [SR]
938
939// FIXME: memory variant!
940def SAR8r1  : II8r<0x0,
941                   (outs GR8:$dst), (ins GR8:$src),
942                   "rra.b\t$dst",
943                   [(set GR8:$dst, (MSP430rra GR8:$src)),
944                    (implicit SR)]>;
945def SAR16r1 : II16r<0x0,
946                    (outs GR16:$dst), (ins GR16:$src),
947                    "rra.w\t$dst",
948                    [(set GR16:$dst, (MSP430rra GR16:$src)),
949                     (implicit SR)]>;
950
951def SHL8r1  : I8rr<0x0,
952                   (outs GR8:$dst), (ins GR8:$src),
953                   "rla.b\t$dst",
954                   [(set GR8:$dst, (MSP430rla GR8:$src)),
955                    (implicit SR)]>;
956def SHL16r1 : I16rr<0x0,
957                    (outs GR16:$dst), (ins GR16:$src),
958                    "rla.w\t$dst",
959                    [(set GR16:$dst, (MSP430rla GR16:$src)),
960                     (implicit SR)]>;
961
962def SAR8r1c  : Pseudo<(outs GR8:$dst), (ins GR8:$src),
963                      "clrc\n\t"
964                      "rrc.b\t$dst",
965                      [(set GR8:$dst, (MSP430rrc GR8:$src)),
966                       (implicit SR)]>;
967def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
968                      "clrc\n\t"
969                      "rrc.w\t$dst",
970                      [(set GR16:$dst, (MSP430rrc GR16:$src)),
971                       (implicit SR)]>;
972
973// FIXME: Memory sext's ?
974def SEXT16r : II16r<0x0,
975                    (outs GR16:$dst), (ins GR16:$src),
976                    "sxt\t$dst",
977                    [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
978                     (implicit SR)]>;
979
980} // Defs = [SR]
981
982def ZEXT16r : I8rr<0x0,
983                   (outs GR16:$dst), (ins GR16:$src),
984                   "mov.b\t{$src, $dst}",
985                   [(set GR16:$dst, (zext (trunc GR16:$src)))]>;
986
987// FIXME: Memory bitswaps?
988def SWPB16r : II16r<0x0,
989                    (outs GR16:$dst), (ins GR16:$src),
990                    "swpb\t$dst",
991                    [(set GR16:$dst, (bswap GR16:$src))]>;
992
993} // Constraints = "$src = $dst"
994
995// Integer comparisons
996let Defs = [SR] in {
997def CMP8rr  : I8rr<0x0,
998                   (outs), (ins GR8:$src, GR8:$src2),
999                   "cmp.b\t{$src2, $src}",
1000                   [(MSP430cmp GR8:$src, GR8:$src2), (implicit SR)]>;
1001def CMP16rr : I16rr<0x0,
1002                    (outs), (ins GR16:$src, GR16:$src2),
1003                    "cmp.w\t{$src2, $src}",
1004                    [(MSP430cmp GR16:$src, GR16:$src2), (implicit SR)]>;
1005
1006def CMP8ri  : I8ri<0x0,
1007                   (outs), (ins GR8:$src, i8imm:$src2),
1008                   "cmp.b\t{$src2, $src}",
1009                   [(MSP430cmp GR8:$src, imm:$src2), (implicit SR)]>;
1010def CMP16ri : I16ri<0x0,
1011                    (outs), (ins GR16:$src, i16imm:$src2),
1012                    "cmp.w\t{$src2, $src}",
1013                    [(MSP430cmp GR16:$src, imm:$src2), (implicit SR)]>;
1014
1015def CMP8mi  : I8mi<0x0,
1016                   (outs), (ins memsrc:$src, i8imm:$src2),
1017                   "cmp.b\t{$src2, $src}",
1018                   [(MSP430cmp (load addr:$src),
1019                               (i8 imm:$src2)), (implicit SR)]>;
1020def CMP16mi : I16mi<0x0,
1021                    (outs), (ins memsrc:$src, i16imm:$src2),
1022                    "cmp.w\t{$src2, $src}",
1023                     [(MSP430cmp (load addr:$src),
1024                                 (i16 imm:$src2)), (implicit SR)]>;
1025
1026def CMP8rm  : I8rm<0x0,
1027                   (outs), (ins GR8:$src, memsrc:$src2),
1028                   "cmp.b\t{$src2, $src}",
1029                   [(MSP430cmp GR8:$src, (load addr:$src2)),
1030                    (implicit SR)]>;
1031def CMP16rm : I16rm<0x0,
1032                    (outs), (ins GR16:$src, memsrc:$src2),
1033                    "cmp.w\t{$src2, $src}",
1034                    [(MSP430cmp GR16:$src, (load addr:$src2)),
1035                     (implicit SR)]>;
1036
1037def CMP8mr  : I8mr<0x0,
1038                   (outs), (ins memsrc:$src, GR8:$src2),
1039                   "cmp.b\t{$src2, $src}",
1040                   [(MSP430cmp (load addr:$src), GR8:$src2),
1041                    (implicit SR)]>;
1042def CMP16mr : I16mr<0x0,
1043                    (outs), (ins memsrc:$src, GR16:$src2),
1044                    "cmp.w\t{$src2, $src}",
1045                    [(MSP430cmp (load addr:$src), GR16:$src2),
1046                     (implicit SR)]>;
1047
1048
1049// BIT TESTS, just sets condition codes
1050// Note that the C condition is set differently than when using CMP.
1051let isCommutable = 1 in {
1052def BIT8rr  : I8rr<0x0,
1053                   (outs), (ins GR8:$src, GR8:$src2),
1054                   "bit.b\t{$src2, $src}",
1055                   [(MSP430cmp (and_su GR8:$src, GR8:$src2), 0),
1056                    (implicit SR)]>;
1057def BIT16rr : I16rr<0x0,
1058                    (outs), (ins GR16:$src, GR16:$src2),
1059                    "bit.w\t{$src2, $src}",
1060                    [(MSP430cmp (and_su GR16:$src, GR16:$src2), 0),
1061                     (implicit SR)]>;
1062}
1063def BIT8ri  : I8ri<0x0,
1064                   (outs), (ins GR8:$src, i8imm:$src2),
1065                   "bit.b\t{$src2, $src}",
1066                   [(MSP430cmp (and_su GR8:$src, imm:$src2), 0),
1067                    (implicit SR)]>;
1068def BIT16ri : I16ri<0x0,
1069                    (outs), (ins GR16:$src, i16imm:$src2),
1070                    "bit.w\t{$src2, $src}",
1071                    [(MSP430cmp (and_su GR16:$src, imm:$src2), 0),
1072                     (implicit SR)]>;
1073
1074def BIT8rm  : I8rm<0x0,
1075                   (outs), (ins GR8:$src, memdst:$src2),
1076                   "bit.b\t{$src2, $src}",
1077                   [(MSP430cmp (and_su GR8:$src,  (load addr:$src2)), 0),
1078                    (implicit SR)]>;
1079def BIT16rm : I16rm<0x0,
1080                    (outs), (ins GR16:$src, memdst:$src2),
1081                    "bit.w\t{$src2, $src}",
1082                    [(MSP430cmp (and_su GR16:$src,  (load addr:$src2)), 0),
1083                     (implicit SR)]>;
1084
1085def BIT8mr  : I8mr<0x0,
1086                  (outs), (ins memsrc:$src, GR8:$src2),
1087                  "bit.b\t{$src2, $src}",
1088                  [(MSP430cmp (and_su (load addr:$src), GR8:$src2), 0),
1089                   (implicit SR)]>;
1090def BIT16mr : I16mr<0x0,
1091                    (outs), (ins memsrc:$src, GR16:$src2),
1092                    "bit.w\t{$src2, $src}",
1093                    [(MSP430cmp (and_su (load addr:$src), GR16:$src2), 0),
1094                     (implicit SR)]>;
1095
1096def BIT8mi  : I8mi<0x0,
1097                   (outs), (ins memsrc:$src, i8imm:$src2),
1098                   "bit.b\t{$src2, $src}",
1099                   [(MSP430cmp (and_su (load addr:$src), (i8 imm:$src2)), 0),
1100                    (implicit SR)]>;
1101def BIT16mi : I16mi<0x0,
1102                    (outs), (ins memsrc:$src, i16imm:$src2),
1103                    "bit.w\t{$src2, $src}",
1104                    [(MSP430cmp (and_su (load addr:$src), (i16 imm:$src2)), 0),
1105                     (implicit SR)]>;
1106
1107def BIT8mm  : I8mm<0x0,
1108                   (outs), (ins memsrc:$src, memsrc:$src2),
1109                   "bit.b\t{$src2, $src}",
1110                   [(MSP430cmp (and_su (i8 (load addr:$src)),
1111                                       (load addr:$src2)),
1112                                 0),
1113                      (implicit SR)]>;
1114def BIT16mm : I16mm<0x0,
1115                    (outs), (ins memsrc:$src, memsrc:$src2),
1116                    "bit.w\t{$src2, $src}",
1117                    [(MSP430cmp (and_su (i16 (load addr:$src)),
1118                                        (load addr:$src2)),
1119                                 0),
1120                     (implicit SR)]>;
1121} // Defs = [SR]
1122
1123//===----------------------------------------------------------------------===//
1124// Non-Instruction Patterns
1125
1126// extload
1127def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1128
1129// anyext
1130def : Pat<(i16 (anyext GR8:$src)),
1131          (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
1132
1133// truncs
1134def : Pat<(i8 (trunc GR16:$src)),
1135          (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
1136
1137// GlobalAddress, ExternalSymbol
1138def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
1139def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
1140def : Pat<(i16 (MSP430Wrapper tblockaddress:$dst)), (MOV16ri tblockaddress:$dst)>;
1141
1142def : Pat<(add GR16:$src, (MSP430Wrapper tglobaladdr :$src2)),
1143          (ADD16ri GR16:$src, tglobaladdr:$src2)>;
1144def : Pat<(add GR16:$src, (MSP430Wrapper texternalsym:$src2)),
1145          (ADD16ri GR16:$src, texternalsym:$src2)>;
1146def : Pat<(add GR16:$src, (MSP430Wrapper tblockaddress:$src2)),
1147          (ADD16ri GR16:$src, tblockaddress:$src2)>;
1148
1149def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
1150          (MOV16mi addr:$dst, tglobaladdr:$src)>;
1151def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
1152          (MOV16mi addr:$dst, texternalsym:$src)>;
1153def : Pat<(store (i16 (MSP430Wrapper tblockaddress:$src)), addr:$dst),
1154          (MOV16mi addr:$dst, tblockaddress:$src)>;
1155
1156// calls
1157def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
1158          (CALLi tglobaladdr:$dst)>;
1159def : Pat<(MSP430call (i16 texternalsym:$dst)),
1160          (CALLi texternalsym:$dst)>;
1161
1162// add and sub always produce carry
1163def : Pat<(addc GR16:$src, GR16:$src2),
1164          (ADD16rr GR16:$src, GR16:$src2)>;
1165def : Pat<(addc GR16:$src, (load addr:$src2)),
1166          (ADD16rm GR16:$src, addr:$src2)>;
1167def : Pat<(addc GR16:$src, imm:$src2),
1168          (ADD16ri GR16:$src, imm:$src2)>;
1169def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
1170          (ADD16mr addr:$dst, GR16:$src)>;
1171def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
1172          (ADD16mm addr:$dst, addr:$src)>;
1173
1174def : Pat<(addc GR8:$src, GR8:$src2),
1175          (ADD8rr GR8:$src, GR8:$src2)>;
1176def : Pat<(addc GR8:$src, (load addr:$src2)),
1177          (ADD8rm GR8:$src, addr:$src2)>;
1178def : Pat<(addc GR8:$src, imm:$src2),
1179          (ADD8ri GR8:$src, imm:$src2)>;
1180def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
1181          (ADD8mr addr:$dst, GR8:$src)>;
1182def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
1183          (ADD8mm addr:$dst, addr:$src)>;
1184
1185def : Pat<(subc GR16:$src, GR16:$src2),
1186          (SUB16rr GR16:$src, GR16:$src2)>;
1187def : Pat<(subc GR16:$src, (load addr:$src2)),
1188          (SUB16rm GR16:$src, addr:$src2)>;
1189def : Pat<(subc GR16:$src, imm:$src2),
1190          (SUB16ri GR16:$src, imm:$src2)>;
1191def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
1192          (SUB16mr addr:$dst, GR16:$src)>;
1193def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
1194          (SUB16mm addr:$dst, addr:$src)>;
1195
1196def : Pat<(subc GR8:$src, GR8:$src2),
1197          (SUB8rr GR8:$src, GR8:$src2)>;
1198def : Pat<(subc GR8:$src, (load addr:$src2)),
1199          (SUB8rm GR8:$src, addr:$src2)>;
1200def : Pat<(subc GR8:$src, imm:$src2),
1201          (SUB8ri GR8:$src, imm:$src2)>;
1202def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
1203          (SUB8mr addr:$dst, GR8:$src)>;
1204def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
1205          (SUB8mm addr:$dst, addr:$src)>;
1206
1207// peephole patterns
1208def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>;
1209def : Pat<(MSP430cmp (trunc (and_su GR16:$src, GR16:$src2)), 0),
1210          (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit),
1211                  (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>;
1212