1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
18 #include "Mips.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/IR/BasicBlock.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/Mangler.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCSectionELF.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include <string>
51
52 using namespace llvm;
53
54 #define DEBUG_TYPE "mips-asm-printer"
55
getTargetStreamer() const56 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
57 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
58 }
59
runOnMachineFunction(MachineFunction & MF)60 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
61 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62
63 // Initialize TargetLoweringObjectFile.
64 const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
65 .Initialize(OutContext, TM);
66
67 MipsFI = MF.getInfo<MipsFunctionInfo>();
68 if (Subtarget->inMips16Mode())
69 for (std::map<
70 const char *,
71 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
72 it = MipsFI->StubsNeeded.begin();
73 it != MipsFI->StubsNeeded.end(); ++it) {
74 const char *Symbol = it->first;
75 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
76 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
77 StubsNeeded[Symbol] = Signature;
78 }
79 MCP = MF.getConstantPool();
80
81 // In NaCl, all indirect jump targets must be aligned to bundle size.
82 if (Subtarget->isTargetNaCl())
83 NaClAlignIndirectJumpTargets(MF);
84
85 AsmPrinter::runOnMachineFunction(MF);
86 return true;
87 }
88
lowerOperand(const MachineOperand & MO,MCOperand & MCOp)89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
90 MCOp = MCInstLowering.LowerOperand(MO);
91 return MCOp.isValid();
92 }
93
94 #include "MipsGenMCPseudoLowering.inc"
95
96 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
97 // JALR, or JALR64 as appropriate for the target
emitPseudoIndirectBranch(MCStreamer & OutStreamer,const MachineInstr * MI)98 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
99 const MachineInstr *MI) {
100 bool HasLinkReg = false;
101 MCInst TmpInst0;
102
103 if (Subtarget->hasMips64r6()) {
104 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
105 TmpInst0.setOpcode(Mips::JALR64);
106 HasLinkReg = true;
107 } else if (Subtarget->hasMips32r6()) {
108 // MIPS32r6 should use (JALR ZERO, $rs)
109 TmpInst0.setOpcode(Mips::JALR);
110 HasLinkReg = true;
111 } else if (Subtarget->inMicroMipsMode())
112 // microMIPS should use (JR_MM $rs)
113 TmpInst0.setOpcode(Mips::JR_MM);
114 else {
115 // Everything else should use (JR $rs)
116 TmpInst0.setOpcode(Mips::JR);
117 }
118
119 MCOperand MCOp;
120
121 if (HasLinkReg) {
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
123 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
124 }
125
126 lowerOperand(MI->getOperand(0), MCOp);
127 TmpInst0.addOperand(MCOp);
128
129 EmitToStreamer(OutStreamer, TmpInst0);
130 }
131
EmitInstruction(const MachineInstr * MI)132 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
133 MipsTargetStreamer &TS = getTargetStreamer();
134 TS.forbidModuleDirective();
135
136 if (MI->isDebugValue()) {
137 SmallString<128> Str;
138 raw_svector_ostream OS(Str);
139
140 PrintDebugValueComment(MI, OS);
141 return;
142 }
143
144 // If we just ended a constant pool, mark it as such.
145 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
146 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
147 InConstantPool = false;
148 }
149 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
150 // CONSTPOOL_ENTRY - This instruction represents a floating
151 //constant pool in the function. The first operand is the ID#
152 // for this instruction, the second is the index into the
153 // MachineConstantPool that this is, the third is the size in
154 // bytes of this constant pool entry.
155 // The required alignment is specified on the basic block holding this MI.
156 //
157 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
158 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
159
160 // If this is the first entry of the pool, mark it.
161 if (!InConstantPool) {
162 OutStreamer.EmitDataRegion(MCDR_DataRegion);
163 InConstantPool = true;
164 }
165
166 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
167
168 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
169 if (MCPE.isMachineConstantPoolEntry())
170 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
171 else
172 EmitGlobalConstant(MCPE.Val.ConstVal);
173 return;
174 }
175
176
177 MachineBasicBlock::const_instr_iterator I = MI;
178 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
179
180 do {
181 // Do any auto-generated pseudo lowerings.
182 if (emitPseudoExpansionLowering(OutStreamer, &*I))
183 continue;
184
185 if (I->getOpcode() == Mips::PseudoReturn ||
186 I->getOpcode() == Mips::PseudoReturn64 ||
187 I->getOpcode() == Mips::PseudoIndirectBranch ||
188 I->getOpcode() == Mips::PseudoIndirectBranch64) {
189 emitPseudoIndirectBranch(OutStreamer, &*I);
190 continue;
191 }
192
193 // The inMips16Mode() test is not permanent.
194 // Some instructions are marked as pseudo right now which
195 // would make the test fail for the wrong reason but
196 // that will be fixed soon. We need this here because we are
197 // removing another test for this situation downstream in the
198 // callchain.
199 //
200 if (I->isPseudo() && !Subtarget->inMips16Mode()
201 && !isLongBranchPseudo(I->getOpcode()))
202 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
203
204 MCInst TmpInst0;
205 MCInstLowering.Lower(I, TmpInst0);
206 EmitToStreamer(OutStreamer, TmpInst0);
207 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
208 }
209
210 //===----------------------------------------------------------------------===//
211 //
212 // Mips Asm Directives
213 //
214 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
215 // Describe the stack frame.
216 //
217 // -- Mask directives "(f)mask bitmask, offset"
218 // Tells the assembler which registers are saved and where.
219 // bitmask - contain a little endian bitset indicating which registers are
220 // saved on function prologue (e.g. with a 0x80000000 mask, the
221 // assembler knows the register 31 (RA) is saved at prologue.
222 // offset - the position before stack pointer subtraction indicating where
223 // the first saved register on prologue is located. (e.g. with a
224 //
225 // Consider the following function prologue:
226 //
227 // .frame $fp,48,$ra
228 // .mask 0xc0000000,-8
229 // addiu $sp, $sp, -48
230 // sw $ra, 40($sp)
231 // sw $fp, 36($sp)
232 //
233 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
234 // 30 (FP) are saved at prologue. As the save order on prologue is from
235 // left to right, RA is saved first. A -8 offset means that after the
236 // stack pointer subtration, the first register in the mask (RA) will be
237 // saved at address 48-8=40.
238 //
239 //===----------------------------------------------------------------------===//
240
241 //===----------------------------------------------------------------------===//
242 // Mask directives
243 //===----------------------------------------------------------------------===//
244
245 // Create a bitmask with all callee saved registers for CPU or Floating Point
246 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
printSavedRegsBitmask()247 void MipsAsmPrinter::printSavedRegsBitmask() {
248 // CPU and FPU Saved Registers Bitmasks
249 unsigned CPUBitmask = 0, FPUBitmask = 0;
250 int CPUTopSavedRegOff, FPUTopSavedRegOff;
251
252 // Set the CPU and FPU Bitmasks
253 const MachineFrameInfo *MFI = MF->getFrameInfo();
254 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
255 // size of stack area to which FP callee-saved regs are saved.
256 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
257 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
258 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
259 bool HasAFGR64Reg = false;
260 unsigned CSFPRegsSize = 0;
261 unsigned i, e = CSI.size();
262
263 // Set FPU Bitmask.
264 for (i = 0; i != e; ++i) {
265 unsigned Reg = CSI[i].getReg();
266 if (Mips::GPR32RegClass.contains(Reg))
267 break;
268
269 unsigned RegNum =
270 TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
271 if (Mips::AFGR64RegClass.contains(Reg)) {
272 FPUBitmask |= (3 << RegNum);
273 CSFPRegsSize += AFGR64RegSize;
274 HasAFGR64Reg = true;
275 continue;
276 }
277
278 FPUBitmask |= (1 << RegNum);
279 CSFPRegsSize += FGR32RegSize;
280 }
281
282 // Set CPU Bitmask.
283 for (; i != e; ++i) {
284 unsigned Reg = CSI[i].getReg();
285 unsigned RegNum =
286 TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
287 CPUBitmask |= (1 << RegNum);
288 }
289
290 // FP Regs are saved right below where the virtual frame pointer points to.
291 FPUTopSavedRegOff = FPUBitmask ?
292 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
293
294 // CPU Regs are saved below FP Regs.
295 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
296
297 MipsTargetStreamer &TS = getTargetStreamer();
298 // Print CPUBitmask
299 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
300
301 // Print FPUBitmask
302 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
303 }
304
305 //===----------------------------------------------------------------------===//
306 // Frame and Set directives
307 //===----------------------------------------------------------------------===//
308
309 /// Frame Directive
emitFrameDirective()310 void MipsAsmPrinter::emitFrameDirective() {
311 const TargetRegisterInfo &RI = *TM.getSubtargetImpl()->getRegisterInfo();
312
313 unsigned stackReg = RI.getFrameRegister(*MF);
314 unsigned returnReg = RI.getRARegister();
315 unsigned stackSize = MF->getFrameInfo()->getStackSize();
316
317 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
318 }
319
320 /// Emit Set directives.
getCurrentABIString() const321 const char *MipsAsmPrinter::getCurrentABIString() const {
322 switch (Subtarget->getABI().GetEnumValue()) {
323 case MipsABIInfo::ABI::O32: return "abi32";
324 case MipsABIInfo::ABI::N32: return "abiN32";
325 case MipsABIInfo::ABI::N64: return "abi64";
326 case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64
327 default: llvm_unreachable("Unknown Mips ABI");
328 }
329 }
330
EmitFunctionEntryLabel()331 void MipsAsmPrinter::EmitFunctionEntryLabel() {
332 MipsTargetStreamer &TS = getTargetStreamer();
333
334 // NaCl sandboxing requires that indirect call instructions are masked.
335 // This means that function entry points should be bundle-aligned.
336 if (Subtarget->isTargetNaCl())
337 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
338
339 if (Subtarget->inMicroMipsMode())
340 TS.emitDirectiveSetMicroMips();
341 else
342 TS.emitDirectiveSetNoMicroMips();
343
344 if (Subtarget->inMips16Mode())
345 TS.emitDirectiveSetMips16();
346 else
347 TS.emitDirectiveSetNoMips16();
348
349 TS.emitDirectiveEnt(*CurrentFnSym);
350 OutStreamer.EmitLabel(CurrentFnSym);
351 }
352
353 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
354 /// the first basic block in the function.
EmitFunctionBodyStart()355 void MipsAsmPrinter::EmitFunctionBodyStart() {
356 MipsTargetStreamer &TS = getTargetStreamer();
357
358 MCInstLowering.Initialize(&MF->getContext());
359
360 bool IsNakedFunction =
361 MF->getFunction()->
362 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
363 Attribute::Naked);
364 if (!IsNakedFunction)
365 emitFrameDirective();
366
367 if (!IsNakedFunction)
368 printSavedRegsBitmask();
369
370 if (!Subtarget->inMips16Mode()) {
371 TS.emitDirectiveSetNoReorder();
372 TS.emitDirectiveSetNoMacro();
373 TS.emitDirectiveSetNoAt();
374 }
375 }
376
377 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
378 /// the last basic block in the function.
EmitFunctionBodyEnd()379 void MipsAsmPrinter::EmitFunctionBodyEnd() {
380 MipsTargetStreamer &TS = getTargetStreamer();
381
382 // There are instruction for this macros, but they must
383 // always be at the function end, and we can't emit and
384 // break with BB logic.
385 if (!Subtarget->inMips16Mode()) {
386 TS.emitDirectiveSetAt();
387 TS.emitDirectiveSetMacro();
388 TS.emitDirectiveSetReorder();
389 }
390 TS.emitDirectiveEnd(CurrentFnSym->getName());
391 // Make sure to terminate any constant pools that were at the end
392 // of the function.
393 if (!InConstantPool)
394 return;
395 InConstantPool = false;
396 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
397 }
398
399 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
400 /// exactly one predecessor and the control transfer mechanism between
401 /// the predecessor and this block is a fall-through.
isBlockOnlyReachableByFallthrough(const MachineBasicBlock * MBB) const402 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
403 MBB) const {
404 // The predecessor has to be immediately before this block.
405 const MachineBasicBlock *Pred = *MBB->pred_begin();
406
407 // If the predecessor is a switch statement, assume a jump table
408 // implementation, so it is not a fall through.
409 if (const BasicBlock *bb = Pred->getBasicBlock())
410 if (isa<SwitchInst>(bb->getTerminator()))
411 return false;
412
413 // If this is a landing pad, it isn't a fall through. If it has no preds,
414 // then nothing falls through to it.
415 if (MBB->isLandingPad() || MBB->pred_empty())
416 return false;
417
418 // If there isn't exactly one predecessor, it can't be a fall through.
419 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
420 ++PI2;
421
422 if (PI2 != MBB->pred_end())
423 return false;
424
425 // The predecessor has to be immediately before this block.
426 if (!Pred->isLayoutSuccessor(MBB))
427 return false;
428
429 // If the block is completely empty, then it definitely does fall through.
430 if (Pred->empty())
431 return true;
432
433 // Otherwise, check the last instruction.
434 // Check if the last terminator is an unconditional branch.
435 MachineBasicBlock::const_iterator I = Pred->end();
436 while (I != Pred->begin() && !(--I)->isTerminator()) ;
437
438 return !I->isBarrier();
439 }
440
441 // Print out an operand for an inline asm expression.
PrintAsmOperand(const MachineInstr * MI,unsigned OpNum,unsigned AsmVariant,const char * ExtraCode,raw_ostream & O)442 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
443 unsigned AsmVariant,const char *ExtraCode,
444 raw_ostream &O) {
445 // Does this asm operand have a single letter operand modifier?
446 if (ExtraCode && ExtraCode[0]) {
447 if (ExtraCode[1] != 0) return true; // Unknown modifier.
448
449 const MachineOperand &MO = MI->getOperand(OpNum);
450 switch (ExtraCode[0]) {
451 default:
452 // See if this is a generic print operand
453 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
454 case 'X': // hex const int
455 if ((MO.getType()) != MachineOperand::MO_Immediate)
456 return true;
457 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
458 return false;
459 case 'x': // hex const int (low 16 bits)
460 if ((MO.getType()) != MachineOperand::MO_Immediate)
461 return true;
462 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
463 return false;
464 case 'd': // decimal const int
465 if ((MO.getType()) != MachineOperand::MO_Immediate)
466 return true;
467 O << MO.getImm();
468 return false;
469 case 'm': // decimal const int minus 1
470 if ((MO.getType()) != MachineOperand::MO_Immediate)
471 return true;
472 O << MO.getImm() - 1;
473 return false;
474 case 'z': {
475 // $0 if zero, regular printing otherwise
476 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
477 O << "$0";
478 return false;
479 }
480 // If not, call printOperand as normal.
481 break;
482 }
483 case 'D': // Second part of a double word register operand
484 case 'L': // Low order register of a double word register operand
485 case 'M': // High order register of a double word register operand
486 {
487 if (OpNum == 0)
488 return true;
489 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
490 if (!FlagsOP.isImm())
491 return true;
492 unsigned Flags = FlagsOP.getImm();
493 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
494 // Number of registers represented by this operand. We are looking
495 // for 2 for 32 bit mode and 1 for 64 bit mode.
496 if (NumVals != 2) {
497 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
498 unsigned Reg = MO.getReg();
499 O << '$' << MipsInstPrinter::getRegisterName(Reg);
500 return false;
501 }
502 return true;
503 }
504
505 unsigned RegOp = OpNum;
506 if (!Subtarget->isGP64bit()){
507 // Endianess reverses which register holds the high or low value
508 // between M and L.
509 switch(ExtraCode[0]) {
510 case 'M':
511 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
512 break;
513 case 'L':
514 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
515 break;
516 case 'D': // Always the second part
517 RegOp = OpNum + 1;
518 }
519 if (RegOp >= MI->getNumOperands())
520 return true;
521 const MachineOperand &MO = MI->getOperand(RegOp);
522 if (!MO.isReg())
523 return true;
524 unsigned Reg = MO.getReg();
525 O << '$' << MipsInstPrinter::getRegisterName(Reg);
526 return false;
527 }
528 }
529 case 'w':
530 // Print MSA registers for the 'f' constraint
531 // In LLVM, the 'w' modifier doesn't need to do anything.
532 // We can just call printOperand as normal.
533 break;
534 }
535 }
536
537 printOperand(MI, OpNum, O);
538 return false;
539 }
540
PrintAsmMemoryOperand(const MachineInstr * MI,unsigned OpNum,unsigned AsmVariant,const char * ExtraCode,raw_ostream & O)541 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
542 unsigned OpNum, unsigned AsmVariant,
543 const char *ExtraCode,
544 raw_ostream &O) {
545 int Offset = 0;
546 // Currently we are expecting either no ExtraCode or 'D'
547 if (ExtraCode) {
548 if (ExtraCode[0] == 'D')
549 Offset = 4;
550 else
551 return true; // Unknown modifier.
552 }
553
554 const MachineOperand &MO = MI->getOperand(OpNum);
555 assert(MO.isReg() && "unexpected inline asm memory operand");
556 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
557
558 return false;
559 }
560
printOperand(const MachineInstr * MI,int opNum,raw_ostream & O)561 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
562 raw_ostream &O) {
563 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
564 const MachineOperand &MO = MI->getOperand(opNum);
565 bool closeP = false;
566
567 if (MO.getTargetFlags())
568 closeP = true;
569
570 switch(MO.getTargetFlags()) {
571 case MipsII::MO_GPREL: O << "%gp_rel("; break;
572 case MipsII::MO_GOT_CALL: O << "%call16("; break;
573 case MipsII::MO_GOT: O << "%got("; break;
574 case MipsII::MO_ABS_HI: O << "%hi("; break;
575 case MipsII::MO_ABS_LO: O << "%lo("; break;
576 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
577 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
578 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
579 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
580 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
581 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
582 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
583 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
584 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
585 }
586
587 switch (MO.getType()) {
588 case MachineOperand::MO_Register:
589 O << '$'
590 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
591 break;
592
593 case MachineOperand::MO_Immediate:
594 O << MO.getImm();
595 break;
596
597 case MachineOperand::MO_MachineBasicBlock:
598 O << *MO.getMBB()->getSymbol();
599 return;
600
601 case MachineOperand::MO_GlobalAddress:
602 O << *getSymbol(MO.getGlobal());
603 break;
604
605 case MachineOperand::MO_BlockAddress: {
606 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
607 O << BA->getName();
608 break;
609 }
610
611 case MachineOperand::MO_ConstantPoolIndex:
612 O << DL->getPrivateGlobalPrefix() << "CPI"
613 << getFunctionNumber() << "_" << MO.getIndex();
614 if (MO.getOffset())
615 O << "+" << MO.getOffset();
616 break;
617
618 default:
619 llvm_unreachable("<unknown operand type>");
620 }
621
622 if (closeP) O << ")";
623 }
624
printUnsignedImm(const MachineInstr * MI,int opNum,raw_ostream & O)625 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
626 raw_ostream &O) {
627 const MachineOperand &MO = MI->getOperand(opNum);
628 if (MO.isImm())
629 O << (unsigned short int)MO.getImm();
630 else
631 printOperand(MI, opNum, O);
632 }
633
printUnsignedImm8(const MachineInstr * MI,int opNum,raw_ostream & O)634 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
635 raw_ostream &O) {
636 const MachineOperand &MO = MI->getOperand(opNum);
637 if (MO.isImm())
638 O << (unsigned short int)(unsigned char)MO.getImm();
639 else
640 printOperand(MI, opNum, O);
641 }
642
643 void MipsAsmPrinter::
printMemOperand(const MachineInstr * MI,int opNum,raw_ostream & O)644 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
645 // Load/Store memory operands -- imm($reg)
646 // If PIC target the target is loaded as the
647 // pattern lw $25,%call16($28)
648
649 // opNum can be invalid if instruction has reglist as operand.
650 // MemOperand is always last operand of instruction (base + offset).
651 switch (MI->getOpcode()) {
652 default:
653 break;
654 case Mips::SWM32_MM:
655 case Mips::LWM32_MM:
656 opNum = MI->getNumOperands() - 2;
657 break;
658 }
659
660 printOperand(MI, opNum+1, O);
661 O << "(";
662 printOperand(MI, opNum, O);
663 O << ")";
664 }
665
666 void MipsAsmPrinter::
printMemOperandEA(const MachineInstr * MI,int opNum,raw_ostream & O)667 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
668 // when using stack locations for not load/store instructions
669 // print the same way as all normal 3 operand instructions.
670 printOperand(MI, opNum, O);
671 O << ", ";
672 printOperand(MI, opNum+1, O);
673 return;
674 }
675
676 void MipsAsmPrinter::
printFCCOperand(const MachineInstr * MI,int opNum,raw_ostream & O,const char * Modifier)677 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
678 const char *Modifier) {
679 const MachineOperand &MO = MI->getOperand(opNum);
680 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
681 }
682
683 void MipsAsmPrinter::
printRegisterList(const MachineInstr * MI,int opNum,raw_ostream & O)684 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
685 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
686 if (i != opNum) O << ", ";
687 printOperand(MI, i, O);
688 }
689 }
690
EmitStartOfAsmFile(Module & M)691 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
692 bool IsABICalls = Subtarget->isABICalls();
693 if (IsABICalls) {
694 getTargetStreamer().emitDirectiveAbiCalls();
695 Reloc::Model RM = TM.getRelocationModel();
696 // FIXME: This condition should be a lot more complicated that it is here.
697 // Ideally it should test for properties of the ABI and not the ABI
698 // itself.
699 // For the moment, I'm only correcting enough to make MIPS-IV work.
700 if (RM == Reloc::Static && !Subtarget->isABI_N64())
701 getTargetStreamer().emitDirectiveOptionPic0();
702 }
703
704 // Tell the assembler which ABI we are using
705 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
706 OutStreamer.SwitchSection(OutContext.getELFSection(
707 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
708
709 // NaN: At the moment we only support:
710 // 1. .nan legacy (default)
711 // 2. .nan 2008
712 Subtarget->isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
713 : getTargetStreamer().emitDirectiveNaNLegacy();
714
715 // TODO: handle O64 ABI
716
717 if (Subtarget->isABI_EABI()) {
718 if (Subtarget->isGP32bit())
719 OutStreamer.SwitchSection(
720 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
721 SectionKind::getDataRel()));
722 else
723 OutStreamer.SwitchSection(
724 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
725 SectionKind::getDataRel()));
726 }
727
728 getTargetStreamer().updateABIInfo(*Subtarget);
729
730 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
731 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
732 // -mfp64) and omit it otherwise.
733 if (Subtarget->isABI_O32() && (Subtarget->isABI_FPXX() ||
734 Subtarget->isFP64bit()))
735 getTargetStreamer().emitDirectiveModuleFP();
736
737 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
738 // accept it. We therefore emit it when it contradicts the default or an
739 // option has changed the default (i.e. FPXX) and omit it otherwise.
740 if (Subtarget->isABI_O32() && (!Subtarget->useOddSPReg() ||
741 Subtarget->isABI_FPXX()))
742 getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(),
743 Subtarget->isABI_O32());
744 }
745
emitInlineAsmStart(const MCSubtargetInfo & StartInfo) const746 void MipsAsmPrinter::emitInlineAsmStart(
747 const MCSubtargetInfo &StartInfo) const {
748 MipsTargetStreamer &TS = getTargetStreamer();
749
750 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
751 // and 'reorder') is different from LLVM's choice for generated code ('noat',
752 // 'nomacro' and 'noreorder').
753 // In order to maintain compatibility with inline assembly code which depends
754 // on GCC's assembler options being used, we have to switch to those options
755 // for the duration of the inline assembly block and then switch back.
756 TS.emitDirectiveSetPush();
757 TS.emitDirectiveSetAt();
758 TS.emitDirectiveSetMacro();
759 TS.emitDirectiveSetReorder();
760 OutStreamer.AddBlankLine();
761 }
762
emitInlineAsmEnd(const MCSubtargetInfo & StartInfo,const MCSubtargetInfo * EndInfo) const763 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
764 const MCSubtargetInfo *EndInfo) const {
765 OutStreamer.AddBlankLine();
766 getTargetStreamer().emitDirectiveSetPop();
767 }
768
EmitJal(MCSymbol * Symbol)769 void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
770 MCInst I;
771 I.setOpcode(Mips::JAL);
772 I.addOperand(
773 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
774 OutStreamer.EmitInstruction(I, getSubtargetInfo());
775 }
776
EmitInstrReg(unsigned Opcode,unsigned Reg)777 void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
778 MCInst I;
779 I.setOpcode(Opcode);
780 I.addOperand(MCOperand::CreateReg(Reg));
781 OutStreamer.EmitInstruction(I, getSubtargetInfo());
782 }
783
EmitInstrRegReg(unsigned Opcode,unsigned Reg1,unsigned Reg2)784 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
785 unsigned Reg2) {
786 MCInst I;
787 //
788 // Because of the current td files for Mips32, the operands for MTC1
789 // appear backwards from their normal assembly order. It's not a trivial
790 // change to fix this in the td file so we adjust for it here.
791 //
792 if (Opcode == Mips::MTC1) {
793 unsigned Temp = Reg1;
794 Reg1 = Reg2;
795 Reg2 = Temp;
796 }
797 I.setOpcode(Opcode);
798 I.addOperand(MCOperand::CreateReg(Reg1));
799 I.addOperand(MCOperand::CreateReg(Reg2));
800 OutStreamer.EmitInstruction(I, getSubtargetInfo());
801 }
802
EmitInstrRegRegReg(unsigned Opcode,unsigned Reg1,unsigned Reg2,unsigned Reg3)803 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
804 unsigned Reg2, unsigned Reg3) {
805 MCInst I;
806 I.setOpcode(Opcode);
807 I.addOperand(MCOperand::CreateReg(Reg1));
808 I.addOperand(MCOperand::CreateReg(Reg2));
809 I.addOperand(MCOperand::CreateReg(Reg3));
810 OutStreamer.EmitInstruction(I, getSubtargetInfo());
811 }
812
EmitMovFPIntPair(unsigned MovOpc,unsigned Reg1,unsigned Reg2,unsigned FPReg1,unsigned FPReg2,bool LE)813 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
814 unsigned Reg2, unsigned FPReg1,
815 unsigned FPReg2, bool LE) {
816 if (!LE) {
817 unsigned temp = Reg1;
818 Reg1 = Reg2;
819 Reg2 = temp;
820 }
821 EmitInstrRegReg(MovOpc, Reg1, FPReg1);
822 EmitInstrRegReg(MovOpc, Reg2, FPReg2);
823 }
824
EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,bool LE,bool ToFP)825 void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
826 bool LE, bool ToFP) {
827 using namespace Mips16HardFloatInfo;
828 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
829 switch (PV) {
830 case FSig:
831 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
832 break;
833 case FFSig:
834 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
835 break;
836 case FDSig:
837 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
838 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
839 break;
840 case DSig:
841 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
842 break;
843 case DDSig:
844 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
845 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
846 break;
847 case DFSig:
848 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
849 EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
850 break;
851 case NoSig:
852 return;
853 }
854 }
855
856 void
EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,bool LE)857 MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
858 bool LE) {
859 using namespace Mips16HardFloatInfo;
860 unsigned MovOpc = Mips::MFC1;
861 switch (RV) {
862 case FRet:
863 EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
864 break;
865 case DRet:
866 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
867 break;
868 case CFRet:
869 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
870 break;
871 case CDRet:
872 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
873 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
874 break;
875 case NoFPRet:
876 break;
877 }
878 }
879
EmitFPCallStub(const char * Symbol,const Mips16HardFloatInfo::FuncSignature * Signature)880 void MipsAsmPrinter::EmitFPCallStub(
881 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
882 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
883 using namespace Mips16HardFloatInfo;
884 bool LE = Subtarget->isLittle();
885 //
886 // .global xxxx
887 //
888 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
889 const char *RetType;
890 //
891 // make the comment field identifying the return and parameter
892 // types of the floating point stub
893 // # Stub function to call rettype xxxx (params)
894 //
895 switch (Signature->RetSig) {
896 case FRet:
897 RetType = "float";
898 break;
899 case DRet:
900 RetType = "double";
901 break;
902 case CFRet:
903 RetType = "complex";
904 break;
905 case CDRet:
906 RetType = "double complex";
907 break;
908 case NoFPRet:
909 RetType = "";
910 break;
911 }
912 const char *Parms;
913 switch (Signature->ParamSig) {
914 case FSig:
915 Parms = "float";
916 break;
917 case FFSig:
918 Parms = "float, float";
919 break;
920 case FDSig:
921 Parms = "float, double";
922 break;
923 case DSig:
924 Parms = "double";
925 break;
926 case DDSig:
927 Parms = "double, double";
928 break;
929 case DFSig:
930 Parms = "double, float";
931 break;
932 case NoSig:
933 Parms = "";
934 break;
935 }
936 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
937 Twine(Symbol) + " (" + Twine(Parms) + ")");
938 //
939 // probably not necessary but we save and restore the current section state
940 //
941 OutStreamer.PushSection();
942 //
943 // .section mips16.call.fpxxxx,"ax",@progbits
944 //
945 const MCSectionELF *M = OutContext.getELFSection(
946 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
947 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
948 OutStreamer.SwitchSection(M, nullptr);
949 //
950 // .align 2
951 //
952 OutStreamer.EmitValueToAlignment(4);
953 MipsTargetStreamer &TS = getTargetStreamer();
954 //
955 // .set nomips16
956 // .set nomicromips
957 //
958 TS.emitDirectiveSetNoMips16();
959 TS.emitDirectiveSetNoMicroMips();
960 //
961 // .ent __call_stub_fp_xxxx
962 // .type __call_stub_fp_xxxx,@function
963 // __call_stub_fp_xxxx:
964 //
965 std::string x = "__call_stub_fp_" + std::string(Symbol);
966 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
967 TS.emitDirectiveEnt(*Stub);
968 MCSymbol *MType =
969 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
970 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
971 OutStreamer.EmitLabel(Stub);
972 //
973 // we just handle non pic for now. these function will not be
974 // called otherwise. when the full stub generation is moved here
975 // we need to deal with pic.
976 //
977 if (TM.getRelocationModel() == Reloc::PIC_)
978 llvm_unreachable("should not be here if we are compiling pic");
979 TS.emitDirectiveSetReorder();
980 //
981 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
982 // stubs without raw text but this current patch is for compiler generated
983 // functions and they all return some value.
984 // The calling sequence for non pic is different in that case and we need
985 // to implement %lo and %hi in order to handle the case of no return value
986 // See the corresponding method in Mips16HardFloat for details.
987 //
988 // mov the return address to S2.
989 // we have no stack space to store it and we are about to make another call.
990 // We need to make sure that the enclosing function knows to save S2
991 // This should have already been handled.
992 //
993 // Mov $18, $31
994
995 EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
996
997 EmitSwapFPIntParams(Signature->ParamSig, LE, true);
998
999 // Jal xxxx
1000 //
1001 EmitJal(MSymbol);
1002
1003 // fix return values
1004 EmitSwapFPIntRetval(Signature->RetSig, LE);
1005 //
1006 // do the return
1007 // if (Signature->RetSig == NoFPRet)
1008 // llvm_unreachable("should not be any stubs here with no return value");
1009 // else
1010 EmitInstrReg(Mips::JR, Mips::S2);
1011
1012 MCSymbol *Tmp = OutContext.CreateTempSymbol();
1013 OutStreamer.EmitLabel(Tmp);
1014 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
1015 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
1016 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
1017 OutStreamer.EmitELFSize(Stub, T_min_E);
1018 TS.emitDirectiveEnd(x);
1019 OutStreamer.PopSection();
1020 }
1021
EmitEndOfAsmFile(Module & M)1022 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
1023 // Emit needed stubs
1024 //
1025 for (std::map<
1026 const char *,
1027 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1028 it = StubsNeeded.begin();
1029 it != StubsNeeded.end(); ++it) {
1030 const char *Symbol = it->first;
1031 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1032 EmitFPCallStub(Symbol, Signature);
1033 }
1034 // return to the text section
1035 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
1036 }
1037
PrintDebugValueComment(const MachineInstr * MI,raw_ostream & OS)1038 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1039 raw_ostream &OS) {
1040 // TODO: implement
1041 }
1042
1043 // Align all targets of indirect branches on bundle size. Used only if target
1044 // is NaCl.
NaClAlignIndirectJumpTargets(MachineFunction & MF)1045 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1046 // Align all blocks that are jumped to through jump table.
1047 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1048 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1049 for (unsigned I = 0; I < JT.size(); ++I) {
1050 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1051
1052 for (unsigned J = 0; J < MBBs.size(); ++J)
1053 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1054 }
1055 }
1056
1057 // If basic block address is taken, block can be target of indirect branch.
1058 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
1059 MBB != E; ++MBB) {
1060 if (MBB->hasAddressTaken())
1061 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1062 }
1063 }
1064
isLongBranchPseudo(int Opcode) const1065 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1066 return (Opcode == Mips::LONG_BRANCH_LUi
1067 || Opcode == Mips::LONG_BRANCH_ADDiu
1068 || Opcode == Mips::LONG_BRANCH_DADDiu);
1069 }
1070
1071 // Force static initialization.
LLVMInitializeMipsAsmPrinter()1072 extern "C" void LLVMInitializeMipsAsmPrinter() {
1073 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
1074 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
1075 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
1076 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
1077 }
1078