1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines an instruction selector for the MIPS target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "mips-isel" 15 #include "MipsISelDAGToDAG.h" 16 #include "Mips16ISelDAGToDAG.h" 17 #include "MipsSEISelDAGToDAG.h" 18 #include "Mips.h" 19 #include "MCTargetDesc/MipsBaseInfo.h" 20 #include "MipsMachineFunction.h" 21 #include "MipsRegisterInfo.h" 22 #include "llvm/CodeGen/MachineConstantPool.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/SelectionDAGNodes.h" 28 #include "llvm/IR/GlobalValue.h" 29 #include "llvm/IR/Instructions.h" 30 #include "llvm/IR/Intrinsics.h" 31 #include "llvm/IR/Type.h" 32 #include "llvm/Support/CFG.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/ErrorHandling.h" 35 #include "llvm/Support/raw_ostream.h" 36 #include "llvm/Target/TargetMachine.h" 37 using namespace llvm; 38 39 //===----------------------------------------------------------------------===// 40 // Instruction Selector Implementation 41 //===----------------------------------------------------------------------===// 42 43 //===----------------------------------------------------------------------===// 44 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine 45 // instructions for SelectionDAG operations. 46 //===----------------------------------------------------------------------===// 47 48 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 49 bool Ret = SelectionDAGISel::runOnMachineFunction(MF); 50 51 processFunctionAfterISel(MF); 52 53 return Ret; 54 } 55 56 /// getGlobalBaseReg - Output the instructions required to put the 57 /// GOT address into a register. 58 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() { 59 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(); 60 return CurDAG->getRegister(GlobalBaseReg, 61 getTargetLowering()->getPointerTy()).getNode(); 62 } 63 64 /// ComplexPattern used on MipsInstrInfo 65 /// Used on Mips Load/Store instructions 66 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, 67 SDValue &Offset) const { 68 llvm_unreachable("Unimplemented function."); 69 return false; 70 } 71 72 bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base, 73 SDValue &Offset) const { 74 llvm_unreachable("Unimplemented function."); 75 return false; 76 } 77 78 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, 79 SDValue &Offset) const { 80 llvm_unreachable("Unimplemented function."); 81 return false; 82 } 83 84 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, 85 SDValue &Offset) const { 86 llvm_unreachable("Unimplemented function."); 87 return false; 88 } 89 90 bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, 91 SDValue &Offset) const { 92 llvm_unreachable("Unimplemented function."); 93 return false; 94 } 95 96 bool MipsDAGToDAGISel::selectAddr16(SDNode *Parent, SDValue N, SDValue &Base, 97 SDValue &Offset, SDValue &Alias) { 98 llvm_unreachable("Unimplemented function."); 99 return false; 100 } 101 102 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const { 103 llvm_unreachable("Unimplemented function."); 104 return false; 105 } 106 107 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { 108 llvm_unreachable("Unimplemented function."); 109 return false; 110 } 111 112 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { 113 llvm_unreachable("Unimplemented function."); 114 return false; 115 } 116 117 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { 118 llvm_unreachable("Unimplemented function."); 119 return false; 120 } 121 122 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { 123 llvm_unreachable("Unimplemented function."); 124 return false; 125 } 126 127 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { 128 llvm_unreachable("Unimplemented function."); 129 return false; 130 } 131 132 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { 133 llvm_unreachable("Unimplemented function."); 134 return false; 135 } 136 137 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { 138 llvm_unreachable("Unimplemented function."); 139 return false; 140 } 141 142 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { 143 llvm_unreachable("Unimplemented function."); 144 return false; 145 } 146 147 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { 148 llvm_unreachable("Unimplemented function."); 149 return false; 150 } 151 152 bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const { 153 llvm_unreachable("Unimplemented function."); 154 return false; 155 } 156 157 bool MipsDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const { 158 llvm_unreachable("Unimplemented function."); 159 return false; 160 } 161 162 bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const { 163 llvm_unreachable("Unimplemented function."); 164 return false; 165 } 166 167 /// Select instructions not customized! Used for 168 /// expanded, promoted and normal instructions 169 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { 170 unsigned Opcode = Node->getOpcode(); 171 172 // Dump information about the Node being selected 173 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 174 175 // If we have a custom node, we already have selected! 176 if (Node->isMachineOpcode()) { 177 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 178 Node->setNodeId(-1); 179 return NULL; 180 } 181 182 // See if subclasses can handle this node. 183 std::pair<bool, SDNode*> Ret = selectNode(Node); 184 185 if (Ret.first) 186 return Ret.second; 187 188 switch(Opcode) { 189 default: break; 190 191 // Get target GOT address. 192 case ISD::GLOBAL_OFFSET_TABLE: 193 return getGlobalBaseReg(); 194 195 #ifndef NDEBUG 196 case ISD::LOAD: 197 case ISD::STORE: 198 assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <= 199 cast<MemSDNode>(Node)->getAlignment() && 200 "Unexpected unaligned loads/stores."); 201 break; 202 #endif 203 } 204 205 // Select the default instruction 206 SDNode *ResNode = SelectCode(Node); 207 208 DEBUG(errs() << "=> "); 209 if (ResNode == NULL || ResNode == Node) 210 DEBUG(Node->dump(CurDAG)); 211 else 212 DEBUG(ResNode->dump(CurDAG)); 213 DEBUG(errs() << "\n"); 214 return ResNode; 215 } 216 217 bool MipsDAGToDAGISel:: 218 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 219 std::vector<SDValue> &OutOps) { 220 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 221 OutOps.push_back(Op); 222 return false; 223 } 224 225 /// createMipsISelDag - This pass converts a legalized DAG into a 226 /// MIPS-specific DAG, ready for instruction scheduling. 227 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { 228 if (TM.getSubtargetImpl()->inMips16Mode()) 229 return llvm::createMips16ISelDag(TM); 230 231 return llvm::createMipsSEISelDag(TM); 232 } 233