1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
17 
18 #include "Mips.h"
19 #include "MipsSubtarget.h"
20 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include <deque>
26 #include <string>
27 
28 namespace llvm {
29   namespace MipsISD {
30     enum NodeType {
31       // Start the numbering from where ISD NodeType finishes.
32       FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 
34       // Jump and link (call)
35       JmpLink,
36 
37       // Tail call
38       TailCall,
39 
40       // Get the Higher 16 bits from a 32-bit immediate
41       // No relation with Mips Hi register
42       Hi,
43 
44       // Get the Lower 16 bits from a 32-bit immediate
45       // No relation with Mips Lo register
46       Lo,
47 
48       // Handle gp_rel (small data/bss sections) relocation.
49       GPRel,
50 
51       // Thread Pointer
52       ThreadPointer,
53 
54       // Floating Point Branch Conditional
55       FPBrcond,
56 
57       // Floating Point Compare
58       FPCmp,
59 
60       // Floating Point Conditional Moves
61       CMovFP_T,
62       CMovFP_F,
63 
64       // FP-to-int truncation node.
65       TruncIntFP,
66 
67       // Return
68       Ret,
69 
70       EH_RETURN,
71 
72       // Node used to extract integer from accumulator.
73       MFHI,
74       MFLO,
75 
76       // Node used to insert integers to accumulator.
77       MTLOHI,
78 
79       // Mult nodes.
80       Mult,
81       Multu,
82 
83       // MAdd/Sub nodes
84       MAdd,
85       MAddu,
86       MSub,
87       MSubu,
88 
89       // DivRem(u)
90       DivRem,
91       DivRemU,
92       DivRem16,
93       DivRemU16,
94 
95       BuildPairF64,
96       ExtractElementF64,
97 
98       Wrapper,
99 
100       DynAlloc,
101 
102       Sync,
103 
104       Ext,
105       Ins,
106 
107       // EXTR.W instrinsic nodes.
108       EXTP,
109       EXTPDP,
110       EXTR_S_H,
111       EXTR_W,
112       EXTR_R_W,
113       EXTR_RS_W,
114       SHILO,
115       MTHLIP,
116 
117       // DPA.W intrinsic nodes.
118       MULSAQ_S_W_PH,
119       MAQ_S_W_PHL,
120       MAQ_S_W_PHR,
121       MAQ_SA_W_PHL,
122       MAQ_SA_W_PHR,
123       DPAU_H_QBL,
124       DPAU_H_QBR,
125       DPSU_H_QBL,
126       DPSU_H_QBR,
127       DPAQ_S_W_PH,
128       DPSQ_S_W_PH,
129       DPAQ_SA_L_W,
130       DPSQ_SA_L_W,
131       DPA_W_PH,
132       DPS_W_PH,
133       DPAQX_S_W_PH,
134       DPAQX_SA_W_PH,
135       DPAX_W_PH,
136       DPSX_W_PH,
137       DPSQX_S_W_PH,
138       DPSQX_SA_W_PH,
139       MULSA_W_PH,
140 
141       MULT,
142       MULTU,
143       MADD_DSP,
144       MADDU_DSP,
145       MSUB_DSP,
146       MSUBU_DSP,
147 
148       // DSP shift nodes.
149       SHLL_DSP,
150       SHRA_DSP,
151       SHRL_DSP,
152 
153       // DSP setcc and select_cc nodes.
154       SETCC_DSP,
155       SELECT_CC_DSP,
156 
157       // Vector comparisons.
158       // These take a vector and return a boolean.
159       VALL_ZERO,
160       VANY_ZERO,
161       VALL_NONZERO,
162       VANY_NONZERO,
163 
164       // These take a vector and return a vector bitmask.
165       VCEQ,
166       VCLE_S,
167       VCLE_U,
168       VCLT_S,
169       VCLT_U,
170 
171       // Element-wise vector max/min.
172       VSMAX,
173       VSMIN,
174       VUMAX,
175       VUMIN,
176 
177       // Vector Shuffle with mask as an operand
178       VSHF,  // Generic shuffle
179       SHF,   // 4-element set shuffle.
180       ILVEV, // Interleave even elements
181       ILVOD, // Interleave odd elements
182       ILVL,  // Interleave left elements
183       ILVR,  // Interleave right elements
184       PCKEV, // Pack even elements
185       PCKOD, // Pack odd elements
186 
187       // Combined (XOR (OR $a, $b), -1)
188       VNOR,
189 
190       // Extended vector element extraction
191       VEXTRACT_SEXT_ELT,
192       VEXTRACT_ZEXT_ELT,
193 
194       // Load/Store Left/Right nodes.
195       LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
196       LWR,
197       SWL,
198       SWR,
199       LDL,
200       LDR,
201       SDL,
202       SDR
203     };
204   }
205 
206   //===--------------------------------------------------------------------===//
207   // TargetLowering Implementation
208   //===--------------------------------------------------------------------===//
209   class MipsFunctionInfo;
210 
211   class MipsTargetLowering : public TargetLowering  {
212   public:
213     explicit MipsTargetLowering(MipsTargetMachine &TM);
214 
215     static const MipsTargetLowering *create(MipsTargetMachine &TM);
216 
217     virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
218 
219     virtual void LowerOperationWrapper(SDNode *N,
220                                        SmallVectorImpl<SDValue> &Results,
221                                        SelectionDAG &DAG) const;
222 
223     /// LowerOperation - Provide custom lowering hooks for some operations.
224     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
225 
226     /// ReplaceNodeResults - Replace the results of node with an illegal result
227     /// type with new values built out of custom code.
228     ///
229     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
230                                     SelectionDAG &DAG) const;
231 
232     /// getTargetNodeName - This method returns the name of a target specific
233     //  DAG node.
234     virtual const char *getTargetNodeName(unsigned Opcode) const;
235 
236     /// getSetCCResultType - get the ISD::SETCC result ValueType
237     EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
238 
239     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
240 
241     virtual MachineBasicBlock *
242     EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
243 
244     struct LTStr {
245       bool operator()(const char *S1, const char *S2) const {
246         return strcmp(S1, S2) < 0;
247       }
248     };
249 
250   protected:
251     SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
252 
253     // This method creates the following nodes, which are necessary for
254     // computing a local symbol's address:
255     //
256     // (add (load (wrapper $gp, %got(sym)), %lo(sym))
257     template<class NodeTy>
258     SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
259                          bool HasMips64) const {
260       SDLoc DL(N);
261       unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
262       SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
263                                 getTargetNode(N, Ty, DAG, GOTFlag));
264       SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
265                                  MachinePointerInfo::getGOT(), false, false,
266                                  false, 0);
267       unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
268       SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
269                                getTargetNode(N, Ty, DAG, LoFlag));
270       return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
271     }
272 
273     // This method creates the following nodes, which are necessary for
274     // computing a global symbol's address:
275     //
276     // (load (wrapper $gp, %got(sym)))
277     template<class NodeTy>
278     SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
279                           unsigned Flag, SDValue Chain,
280                           const MachinePointerInfo &PtrInfo) const {
281       SDLoc DL(N);
282       SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
283                                 getTargetNode(N, Ty, DAG, Flag));
284       return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
285     }
286 
287     // This method creates the following nodes, which are necessary for
288     // computing a global symbol's address in large-GOT mode:
289     //
290     // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
291     template<class NodeTy>
292     SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
293                                   unsigned HiFlag, unsigned LoFlag,
294                                   SDValue Chain,
295                                   const MachinePointerInfo &PtrInfo) const {
296       SDLoc DL(N);
297       SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
298                                getTargetNode(N, Ty, DAG, HiFlag));
299       Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
300       SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
301                                     getTargetNode(N, Ty, DAG, LoFlag));
302       return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
303                          0);
304     }
305 
306     // This method creates the following nodes, which are necessary for
307     // computing a symbol's address in non-PIC mode:
308     //
309     // (add %hi(sym), %lo(sym))
310     template<class NodeTy>
311     SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
312       SDLoc DL(N);
313       SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
314       SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
315       return DAG.getNode(ISD::ADD, DL, Ty,
316                          DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
317                          DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
318     }
319 
320     /// This function fills Ops, which is the list of operands that will later
321     /// be used when a function call node is created. It also generates
322     /// copyToReg nodes to set up argument registers.
323     virtual void
324     getOpndList(SmallVectorImpl<SDValue> &Ops,
325                 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
326                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
327                 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
328 
329     /// ByValArgInfo - Byval argument information.
330     struct ByValArgInfo {
331       unsigned FirstIdx; // Index of the first register used.
332       unsigned NumRegs;  // Number of registers used for this argument.
333       unsigned Address;  // Offset of the stack area used to pass this argument.
334 
335       ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
336     };
337 
338     /// MipsCC - This class provides methods used to analyze formal and call
339     /// arguments and inquire about calling convention information.
340     class MipsCC {
341     public:
342       enum SpecialCallingConvType {
343         Mips16RetHelperConv, NoSpecialCallingConv
344       };
345 
346       MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
347              SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
348 
349 
350       void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
351                                bool IsVarArg, bool IsSoftFloat,
352                                const SDNode *CallNode,
353                                std::vector<ArgListEntry> &FuncArgs);
354       void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
355                                   bool IsSoftFloat,
356                                   Function::const_arg_iterator FuncArg);
357 
358       void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
359                              bool IsSoftFloat, const SDNode *CallNode,
360                              const Type *RetTy) const;
361 
362       void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
363                          bool IsSoftFloat, const Type *RetTy) const;
364 
365       const CCState &getCCInfo() const { return CCInfo; }
366 
367       /// hasByValArg - Returns true if function has byval arguments.
368       bool hasByValArg() const { return !ByValArgs.empty(); }
369 
370       /// regSize - Size (in number of bits) of integer registers.
371       unsigned regSize() const { return IsO32 ? 4 : 8; }
372 
373       /// numIntArgRegs - Number of integer registers available for calls.
374       unsigned numIntArgRegs() const;
375 
376       /// reservedArgArea - The size of the area the caller reserves for
377       /// register arguments. This is 16-byte if ABI is O32.
378       unsigned reservedArgArea() const;
379 
380       /// Return pointer to array of integer argument registers.
381       const uint16_t *intArgRegs() const;
382 
383       typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
384       byval_iterator byval_begin() const { return ByValArgs.begin(); }
385       byval_iterator byval_end() const { return ByValArgs.end(); }
386 
387     private:
388       void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
389                           CCValAssign::LocInfo LocInfo,
390                           ISD::ArgFlagsTy ArgFlags);
391 
392       /// useRegsForByval - Returns true if the calling convention allows the
393       /// use of registers to pass byval arguments.
394       bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
395 
396       /// Return the function that analyzes fixed argument list functions.
397       llvm::CCAssignFn *fixedArgFn() const;
398 
399       /// Return the function that analyzes variable argument list functions.
400       llvm::CCAssignFn *varArgFn() const;
401 
402       const uint16_t *shadowRegs() const;
403 
404       void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
405                         unsigned Align);
406 
407       /// Return the type of the register which is used to pass an argument or
408       /// return a value. This function returns f64 if the argument is an i64
409       /// value which has been generated as a result of softening an f128 value.
410       /// Otherwise, it just returns VT.
411       MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
412                    bool IsSoftFloat) const;
413 
414       template<typename Ty>
415       void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
416                          const SDNode *CallNode, const Type *RetTy) const;
417 
418       CCState &CCInfo;
419       CallingConv::ID CallConv;
420       bool IsO32, IsFP64;
421       SpecialCallingConvType SpecialCallingConv;
422       SmallVector<ByValArgInfo, 2> ByValArgs;
423     };
424   protected:
425     SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
426     SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
427 
428     // Subtarget Info
429     const MipsSubtarget *Subtarget;
430 
431     bool HasMips64, IsN64, IsO32;
432 
433   private:
434     // Create a TargetGlobalAddress node.
435     SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
436                           unsigned Flag) const;
437 
438     // Create a TargetExternalSymbol node.
439     SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
440                           unsigned Flag) const;
441 
442     // Create a TargetBlockAddress node.
443     SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
444                           unsigned Flag) const;
445 
446     // Create a TargetJumpTable node.
447     SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
448                           unsigned Flag) const;
449 
450     // Create a TargetConstantPool node.
451     SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
452                           unsigned Flag) const;
453 
454     MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
455     // Lower Operand helpers
456     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
457                             CallingConv::ID CallConv, bool isVarArg,
458                             const SmallVectorImpl<ISD::InputArg> &Ins,
459                             SDLoc dl, SelectionDAG &DAG,
460                             SmallVectorImpl<SDValue> &InVals,
461                             const SDNode *CallNode, const Type *RetTy) const;
462 
463     // Lower Operand specifics
464     SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
465     SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
466     SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
467     SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
468     SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
469     SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
470     SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
471     SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
472     SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
473     SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
474     SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
475     SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
476     SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
477     SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
478     SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
479     SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
480     SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
481     SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
482     SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
483                                  bool IsSRA) const;
484     SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
485     SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
486 
487     /// isEligibleForTailCallOptimization - Check whether the call is eligible
488     /// for tail call optimization.
489     virtual bool
490     isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
491                                       unsigned NextStackOffset,
492                                       const MipsFunctionInfo& FI) const = 0;
493 
494     /// copyByValArg - Copy argument registers which were used to pass a byval
495     /// argument to the stack. Create a stack frame object for the byval
496     /// argument.
497     void copyByValRegs(SDValue Chain, SDLoc DL,
498                        std::vector<SDValue> &OutChains, SelectionDAG &DAG,
499                        const ISD::ArgFlagsTy &Flags,
500                        SmallVectorImpl<SDValue> &InVals,
501                        const Argument *FuncArg,
502                        const MipsCC &CC, const ByValArgInfo &ByVal) const;
503 
504     /// passByValArg - Pass a byval argument in registers or on stack.
505     void passByValArg(SDValue Chain, SDLoc DL,
506                       std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
507                       SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
508                       MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
509                       const MipsCC &CC, const ByValArgInfo &ByVal,
510                       const ISD::ArgFlagsTy &Flags, bool isLittle) const;
511 
512     /// writeVarArgRegs - Write variable function arguments passed in registers
513     /// to the stack. Also create a stack frame object for the first variable
514     /// argument.
515     void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
516                          SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
517 
518     virtual SDValue
519       LowerFormalArguments(SDValue Chain,
520                            CallingConv::ID CallConv, bool isVarArg,
521                            const SmallVectorImpl<ISD::InputArg> &Ins,
522                            SDLoc dl, SelectionDAG &DAG,
523                            SmallVectorImpl<SDValue> &InVals) const;
524 
525     SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
526                            SDValue Arg, SDLoc DL, bool IsTailCall,
527                            SelectionDAG &DAG) const;
528 
529     virtual SDValue
530       LowerCall(TargetLowering::CallLoweringInfo &CLI,
531                 SmallVectorImpl<SDValue> &InVals) const;
532 
533     virtual bool
534       CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
535                      bool isVarArg,
536                      const SmallVectorImpl<ISD::OutputArg> &Outs,
537                      LLVMContext &Context) const;
538 
539     virtual SDValue
540       LowerReturn(SDValue Chain,
541                   CallingConv::ID CallConv, bool isVarArg,
542                   const SmallVectorImpl<ISD::OutputArg> &Outs,
543                   const SmallVectorImpl<SDValue> &OutVals,
544                   SDLoc dl, SelectionDAG &DAG) const;
545 
546     // Inline asm support
547     ConstraintType getConstraintType(const std::string &Constraint) const;
548 
549     /// Examine constraint string and operand type and determine a weight value.
550     /// The operand object must already have been set up with the operand type.
551     ConstraintWeight getSingleConstraintMatchWeight(
552       AsmOperandInfo &info, const char *constraint) const;
553 
554     /// This function parses registers that appear in inline-asm constraints.
555     /// It returns pair (0, 0) on failure.
556     std::pair<unsigned, const TargetRegisterClass *>
557     parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
558 
559     std::pair<unsigned, const TargetRegisterClass*>
560               getRegForInlineAsmConstraint(const std::string &Constraint,
561                                            MVT VT) const;
562 
563     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
564     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
565     /// true it means one of the asm constraint of the inline asm instruction
566     /// being processed is 'm'.
567     virtual void LowerAsmOperandForConstraint(SDValue Op,
568                                               std::string &Constraint,
569                                               std::vector<SDValue> &Ops,
570                                               SelectionDAG &DAG) const;
571 
572     virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
573 
574     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
575 
576     virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
577                                     unsigned SrcAlign,
578                                     bool IsMemset, bool ZeroMemset,
579                                     bool MemcpyStrSrc,
580                                     MachineFunction &MF) const;
581 
582     /// isFPImmLegal - Returns true if the target can instruction select the
583     /// specified FP immediate natively. If false, the legalizer will
584     /// materialize the FP immediate as a load from a constant pool.
585     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
586 
587     virtual unsigned getJumpTableEncoding() const;
588 
589     MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
590                     unsigned Size, unsigned BinOpcode, bool Nand = false) const;
591     MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
592                     MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
593                     bool Nand = false) const;
594     MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
595                                   MachineBasicBlock *BB, unsigned Size) const;
596     MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
597                                   MachineBasicBlock *BB, unsigned Size) const;
598   };
599 
600   /// Create MipsTargetLowering objects.
601   const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
602   const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
603 }
604 
605 #endif // MipsISELLOWERING_H
606