1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the MIPS implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "mips-reg-info" 15 16 #include "MipsRegisterInfo.h" 17 #include "Mips.h" 18 #include "MipsAnalyzeImmediate.h" 19 #include "MipsInstrInfo.h" 20 #include "MipsMachineFunction.h" 21 #include "MipsSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/ValueTypes.h" 28 #include "llvm/DebugInfo.h" 29 #include "llvm/IR/Constants.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetFrameLowering.h" 36 #include "llvm/Target/TargetInstrInfo.h" 37 #include "llvm/Target/TargetMachine.h" 38 #include "llvm/Target/TargetOptions.h" 39 40 #define GET_REGINFO_TARGET_DESC 41 #include "MipsGenRegisterInfo.inc" 42 43 using namespace llvm; 44 45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST) 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 47 48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 49 50 const TargetRegisterClass * 51 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF, 52 unsigned Kind) const { 53 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 54 } 55 56 unsigned 57 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 58 MachineFunction &MF) const { 59 switch (RC->getID()) { 60 default: 61 return 0; 62 case Mips::GPR32RegClassID: 63 case Mips::GPR64RegClassID: 64 case Mips::DSPRRegClassID: { 65 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 66 return 28 - TFI->hasFP(MF); 67 } 68 case Mips::FGR32RegClassID: 69 return 32; 70 case Mips::AFGR64RegClassID: 71 return 16; 72 case Mips::FGR64RegClassID: 73 return 32; 74 } 75 } 76 77 //===----------------------------------------------------------------------===// 78 // Callee Saved Registers methods 79 //===----------------------------------------------------------------------===// 80 81 /// Mips Callee Saved Registers 82 const uint16_t* MipsRegisterInfo:: 83 getCalleeSavedRegs(const MachineFunction *MF) const { 84 if (Subtarget.isSingleFloat()) 85 return CSR_SingleFloatOnly_SaveList; 86 87 if (Subtarget.isABI_N64()) 88 return CSR_N64_SaveList; 89 90 if (Subtarget.isABI_N32()) 91 return CSR_N32_SaveList; 92 93 if (Subtarget.isFP64bit()) 94 return CSR_O32_FP64_SaveList; 95 96 return CSR_O32_SaveList; 97 } 98 99 const uint32_t* 100 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 101 if (Subtarget.isSingleFloat()) 102 return CSR_SingleFloatOnly_RegMask; 103 104 if (Subtarget.isABI_N64()) 105 return CSR_N64_RegMask; 106 107 if (Subtarget.isABI_N32()) 108 return CSR_N32_RegMask; 109 110 if (Subtarget.isFP64bit()) 111 return CSR_O32_FP64_RegMask; 112 113 return CSR_O32_RegMask; 114 } 115 116 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() { 117 return CSR_Mips16RetHelper_RegMask; 118 } 119 120 BitVector MipsRegisterInfo:: 121 getReservedRegs(const MachineFunction &MF) const { 122 static const uint16_t ReservedGPR32[] = { 123 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP 124 }; 125 126 static const uint16_t ReservedGPR64[] = { 127 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 128 }; 129 130 BitVector Reserved(getNumRegs()); 131 typedef TargetRegisterClass::const_iterator RegIter; 132 133 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I) 134 Reserved.set(ReservedGPR32[I]); 135 136 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) 137 Reserved.set(ReservedGPR64[I]); 138 139 if (Subtarget.isFP64bit()) { 140 // Reserve all registers in AFGR64. 141 for (RegIter Reg = Mips::AFGR64RegClass.begin(), 142 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) 143 Reserved.set(*Reg); 144 } else { 145 // Reserve all registers in FGR64. 146 for (RegIter Reg = Mips::FGR64RegClass.begin(), 147 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) 148 Reserved.set(*Reg); 149 } 150 // Reserve FP if this function should have a dedicated frame pointer register. 151 if (MF.getTarget().getFrameLowering()->hasFP(MF)) { 152 if (Subtarget.inMips16Mode()) 153 Reserved.set(Mips::S0); 154 else { 155 Reserved.set(Mips::FP); 156 Reserved.set(Mips::FP_64); 157 } 158 } 159 160 // Reserve hardware registers. 161 Reserved.set(Mips::HWR29); 162 163 // Reserve DSP control register. 164 Reserved.set(Mips::DSPPos); 165 Reserved.set(Mips::DSPSCount); 166 Reserved.set(Mips::DSPCarry); 167 Reserved.set(Mips::DSPEFI); 168 Reserved.set(Mips::DSPOutFlag); 169 170 // Reserve MSA control registers. 171 Reserved.set(Mips::MSAIR); 172 Reserved.set(Mips::MSACSR); 173 Reserved.set(Mips::MSAAccess); 174 Reserved.set(Mips::MSASave); 175 Reserved.set(Mips::MSAModify); 176 Reserved.set(Mips::MSARequest); 177 Reserved.set(Mips::MSAMap); 178 Reserved.set(Mips::MSAUnmap); 179 180 // Reserve RA if in mips16 mode. 181 if (Subtarget.inMips16Mode()) { 182 Reserved.set(Mips::RA); 183 Reserved.set(Mips::RA_64); 184 Reserved.set(Mips::T0); 185 Reserved.set(Mips::T1); 186 } 187 188 // Reserve GP if small section is used. 189 if (Subtarget.useSmallSection()) { 190 Reserved.set(Mips::GP); 191 Reserved.set(Mips::GP_64); 192 } 193 194 return Reserved; 195 } 196 197 bool 198 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 199 return true; 200 } 201 202 bool 203 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 204 return true; 205 } 206 207 // FrameIndex represent objects inside a abstract stack. 208 // We must replace FrameIndex with an stack/frame pointer 209 // direct reference. 210 void MipsRegisterInfo:: 211 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 212 unsigned FIOperandNum, RegScavenger *RS) const { 213 MachineInstr &MI = *II; 214 MachineFunction &MF = *MI.getParent()->getParent(); 215 216 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; 217 errs() << "<--------->\n" << MI); 218 219 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 220 uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 221 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 222 223 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 224 << "spOffset : " << spOffset << "\n" 225 << "stackSize : " << stackSize << "\n"); 226 227 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); 228 } 229 230 unsigned MipsRegisterInfo:: 231 getFrameRegister(const MachineFunction &MF) const { 232 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 233 bool IsN64 = Subtarget.isABI_N64(); 234 235 if (Subtarget.inMips16Mode()) 236 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; 237 else 238 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 239 (IsN64 ? Mips::SP_64 : Mips::SP); 240 241 } 242 243