1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
35 using namespace llvm;
36
37 #define DEBUG_TYPE "mips-isel"
38
runOnMachineFunction(MachineFunction & MF)39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40 Subtarget = &TM.getSubtarget<MipsSubtarget>();
41 if (Subtarget->inMips16Mode())
42 return false;
43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 }
45
addDSPCtrlRegOperands(bool IsDef,MachineInstr & MI,MachineFunction & MF)46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47 MachineFunction &MF) {
48 MachineInstrBuilder MIB(MF, &MI);
49 unsigned Mask = MI.getOperand(1).getImm();
50 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
51
52 if (Mask & 1)
53 MIB.addReg(Mips::DSPPos, Flag);
54
55 if (Mask & 2)
56 MIB.addReg(Mips::DSPSCount, Flag);
57
58 if (Mask & 4)
59 MIB.addReg(Mips::DSPCarry, Flag);
60
61 if (Mask & 8)
62 MIB.addReg(Mips::DSPOutFlag, Flag);
63
64 if (Mask & 16)
65 MIB.addReg(Mips::DSPCCond, Flag);
66
67 if (Mask & 32)
68 MIB.addReg(Mips::DSPEFI, Flag);
69 }
70
getMSACtrlReg(const SDValue RegIdx) const71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
73 default:
74 llvm_unreachable("Could not map int to register");
75 case 0: return Mips::MSAIR;
76 case 1: return Mips::MSACSR;
77 case 2: return Mips::MSAAccess;
78 case 3: return Mips::MSASave;
79 case 4: return Mips::MSAModify;
80 case 5: return Mips::MSARequest;
81 case 6: return Mips::MSAMap;
82 case 7: return Mips::MSAUnmap;
83 }
84 }
85
replaceUsesWithZeroReg(MachineRegisterInfo * MRI,const MachineInstr & MI)86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
87 const MachineInstr& MI) {
88 unsigned DstReg = 0, ZeroReg = 0;
89
90 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91 if ((MI.getOpcode() == Mips::ADDiu) &&
92 (MI.getOperand(1).getReg() == Mips::ZERO) &&
93 (MI.getOperand(2).getImm() == 0)) {
94 DstReg = MI.getOperand(0).getReg();
95 ZeroReg = Mips::ZERO;
96 } else if ((MI.getOpcode() == Mips::DADDiu) &&
97 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
98 (MI.getOperand(2).getImm() == 0)) {
99 DstReg = MI.getOperand(0).getReg();
100 ZeroReg = Mips::ZERO_64;
101 }
102
103 if (!DstReg)
104 return false;
105
106 // Replace uses with ZeroReg.
107 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
108 E = MRI->use_end(); U != E;) {
109 MachineOperand &MO = *U;
110 unsigned OpNo = U.getOperandNo();
111 MachineInstr *MI = MO.getParent();
112 ++U;
113
114 // Do not replace if it is a phi's operand or is tied to def operand.
115 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
116 continue;
117
118 MO.setReg(ZeroReg);
119 }
120
121 return true;
122 }
123
initGlobalBaseReg(MachineFunction & MF)124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
125 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
126
127 if (!MipsFI->globalBaseRegSet())
128 return;
129
130 MachineBasicBlock &MBB = MF.front();
131 MachineBasicBlock::iterator I = MBB.begin();
132 MachineRegisterInfo &RegInfo = MF.getRegInfo();
133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
134 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136 const TargetRegisterClass *RC;
137
138 RC = (Subtarget->isABI_N64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
139
140 V0 = RegInfo.createVirtualRegister(RC);
141 V1 = RegInfo.createVirtualRegister(RC);
142
143 if (Subtarget->isABI_N64()) {
144 MF.getRegInfo().addLiveIn(Mips::T9_64);
145 MBB.addLiveIn(Mips::T9_64);
146
147 // lui $v0, %hi(%neg(%gp_rel(fname)))
148 // daddu $v1, $v0, $t9
149 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
150 const GlobalValue *FName = MF.getFunction();
151 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
152 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
153 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
154 .addReg(Mips::T9_64);
155 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
156 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
157 return;
158 }
159
160 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
161 // Set global register to __gnu_local_gp.
162 //
163 // lui $v0, %hi(__gnu_local_gp)
164 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
165 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
166 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
167 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
168 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
169 return;
170 }
171
172 MF.getRegInfo().addLiveIn(Mips::T9);
173 MBB.addLiveIn(Mips::T9);
174
175 if (Subtarget->isABI_N32()) {
176 // lui $v0, %hi(%neg(%gp_rel(fname)))
177 // addu $v1, $v0, $t9
178 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
179 const GlobalValue *FName = MF.getFunction();
180 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
181 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
182 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
184 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
185 return;
186 }
187
188 assert(Subtarget->isABI_O32());
189
190 // For O32 ABI, the following instruction sequence is emitted to initialize
191 // the global base register:
192 //
193 // 0. lui $2, %hi(_gp_disp)
194 // 1. addiu $2, $2, %lo(_gp_disp)
195 // 2. addu $globalbasereg, $2, $t9
196 //
197 // We emit only the last instruction here.
198 //
199 // GNU linker requires that the first two instructions appear at the beginning
200 // of a function and no instructions be inserted before or between them.
201 // The two instructions are emitted during lowering to MC layer in order to
202 // avoid any reordering.
203 //
204 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
205 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
206 // reads it.
207 MF.getRegInfo().addLiveIn(Mips::V0);
208 MBB.addLiveIn(Mips::V0);
209 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
210 .addReg(Mips::V0).addReg(Mips::T9);
211 }
212
processFunctionAfterISel(MachineFunction & MF)213 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
214 initGlobalBaseReg(MF);
215
216 MachineRegisterInfo *MRI = &MF.getRegInfo();
217
218 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
219 ++MFI)
220 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
221 if (I->getOpcode() == Mips::RDDSP)
222 addDSPCtrlRegOperands(false, *I, MF);
223 else if (I->getOpcode() == Mips::WRDSP)
224 addDSPCtrlRegOperands(true, *I, MF);
225 else
226 replaceUsesWithZeroReg(MRI, *I);
227 }
228 }
229
selectAddESubE(unsigned MOp,SDValue InFlag,SDValue CmpLHS,SDLoc DL,SDNode * Node) const230 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
231 SDValue CmpLHS, SDLoc DL,
232 SDNode *Node) const {
233 unsigned Opc = InFlag.getOpcode(); (void)Opc;
234
235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
236 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
237 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
238
239 unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
240 if (Subtarget->isGP64bit()) {
241 SLTuOp = Mips::SLTu64;
242 ADDuOp = Mips::DADDu;
243 }
244
245 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
246 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
247 EVT VT = LHS.getValueType();
248
249 SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
250
251 if (Subtarget->isGP64bit()) {
252 // On 64-bit targets, sltu produces an i64 but our backend currently says
253 // that SLTu64 produces an i32. We need to fix this in the long run but for
254 // now, just make the DAG type-correct by asserting the upper bits are zero.
255 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
256 CurDAG->getTargetConstant(0, VT),
257 SDValue(Carry, 0),
258 CurDAG->getTargetConstant(Mips::sub_32, VT));
259 }
260
261 // Generate a second addition only if we know that RHS is not a
262 // constant-zero node.
263 SDNode *AddCarry = Carry;
264 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
265 if (!C || C->getZExtValue())
266 AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
267
268 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
269 SDValue(AddCarry, 0));
270 }
271
272 /// Match frameindex
selectAddrFrameIndex(SDValue Addr,SDValue & Base,SDValue & Offset) const273 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
274 SDValue &Offset) const {
275 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
276 EVT ValTy = Addr.getValueType();
277
278 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
279 Offset = CurDAG->getTargetConstant(0, ValTy);
280 return true;
281 }
282 return false;
283 }
284
285 /// Match frameindex+offset and frameindex|offset
selectAddrFrameIndexOffset(SDValue Addr,SDValue & Base,SDValue & Offset,unsigned OffsetBits) const286 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
287 SDValue &Offset,
288 unsigned OffsetBits) const {
289 if (CurDAG->isBaseWithConstantOffset(Addr)) {
290 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
291 if (isIntN(OffsetBits, CN->getSExtValue())) {
292 EVT ValTy = Addr.getValueType();
293
294 // If the first operand is a FI, get the TargetFI Node
295 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
296 (Addr.getOperand(0)))
297 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
298 else
299 Base = Addr.getOperand(0);
300
301 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
302 return true;
303 }
304 }
305 return false;
306 }
307
308 /// ComplexPattern used on MipsInstrInfo
309 /// Used on Mips Load/Store instructions
selectAddrRegImm(SDValue Addr,SDValue & Base,SDValue & Offset) const310 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
311 SDValue &Offset) const {
312 // if Address is FI, get the TargetFrameIndex.
313 if (selectAddrFrameIndex(Addr, Base, Offset))
314 return true;
315
316 // on PIC code Load GA
317 if (Addr.getOpcode() == MipsISD::Wrapper) {
318 Base = Addr.getOperand(0);
319 Offset = Addr.getOperand(1);
320 return true;
321 }
322
323 if (TM.getRelocationModel() != Reloc::PIC_) {
324 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
325 Addr.getOpcode() == ISD::TargetGlobalAddress))
326 return false;
327 }
328
329 // Addresses of the form FI+const or FI|const
330 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
331 return true;
332
333 // Operand is a result from an ADD.
334 if (Addr.getOpcode() == ISD::ADD) {
335 // When loading from constant pools, load the lower address part in
336 // the instruction itself. Example, instead of:
337 // lui $2, %hi($CPI1_0)
338 // addiu $2, $2, %lo($CPI1_0)
339 // lwc1 $f0, 0($2)
340 // Generate:
341 // lui $2, %hi($CPI1_0)
342 // lwc1 $f0, %lo($CPI1_0)($2)
343 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
344 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
345 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
346 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
347 isa<JumpTableSDNode>(Opnd0)) {
348 Base = Addr.getOperand(0);
349 Offset = Opnd0;
350 return true;
351 }
352 }
353 }
354
355 return false;
356 }
357
358 /// ComplexPattern used on MipsInstrInfo
359 /// Used on Mips Load/Store instructions
selectAddrRegReg(SDValue Addr,SDValue & Base,SDValue & Offset) const360 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
361 SDValue &Offset) const {
362 // Operand is a result from an ADD.
363 if (Addr.getOpcode() == ISD::ADD) {
364 Base = Addr.getOperand(0);
365 Offset = Addr.getOperand(1);
366 return true;
367 }
368
369 return false;
370 }
371
selectAddrDefault(SDValue Addr,SDValue & Base,SDValue & Offset) const372 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
373 SDValue &Offset) const {
374 Base = Addr;
375 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
376 return true;
377 }
378
selectIntAddr(SDValue Addr,SDValue & Base,SDValue & Offset) const379 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
380 SDValue &Offset) const {
381 return selectAddrRegImm(Addr, Base, Offset) ||
382 selectAddrDefault(Addr, Base, Offset);
383 }
384
selectAddrRegImm10(SDValue Addr,SDValue & Base,SDValue & Offset) const385 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
386 SDValue &Offset) const {
387 if (selectAddrFrameIndex(Addr, Base, Offset))
388 return true;
389
390 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
391 return true;
392
393 return false;
394 }
395
396 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
selectAddrRegImm12(SDValue Addr,SDValue & Base,SDValue & Offset) const397 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
398 SDValue &Offset) const {
399 if (selectAddrFrameIndex(Addr, Base, Offset))
400 return true;
401
402 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
403 return true;
404
405 return false;
406 }
407
selectIntAddrMM(SDValue Addr,SDValue & Base,SDValue & Offset) const408 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
409 SDValue &Offset) const {
410 return selectAddrRegImm12(Addr, Base, Offset) ||
411 selectAddrDefault(Addr, Base, Offset);
412 }
413
selectIntAddrMSA(SDValue Addr,SDValue & Base,SDValue & Offset) const414 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
415 SDValue &Offset) const {
416 if (selectAddrRegImm10(Addr, Base, Offset))
417 return true;
418
419 if (selectAddrDefault(Addr, Base, Offset))
420 return true;
421
422 return false;
423 }
424
425 // Select constant vector splats.
426 //
427 // Returns true and sets Imm if:
428 // * MSA is enabled
429 // * N is a ISD::BUILD_VECTOR representing a constant splat
selectVSplat(SDNode * N,APInt & Imm) const430 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
431 if (!Subtarget->hasMSA())
432 return false;
433
434 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
435
436 if (!Node)
437 return false;
438
439 APInt SplatValue, SplatUndef;
440 unsigned SplatBitSize;
441 bool HasAnyUndefs;
442
443 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
444 HasAnyUndefs, 8,
445 !Subtarget->isLittle()))
446 return false;
447
448 Imm = SplatValue;
449
450 return true;
451 }
452
453 // Select constant vector splats.
454 //
455 // In addition to the requirements of selectVSplat(), this function returns
456 // true and sets Imm if:
457 // * The splat value is the same width as the elements of the vector
458 // * The splat value fits in an integer with the specified signed-ness and
459 // width.
460 //
461 // This function looks through ISD::BITCAST nodes.
462 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
463 // sometimes a shuffle in big-endian mode.
464 //
465 // It's worth noting that this function is not used as part of the selection
466 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
467 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
468 // MipsSEDAGToDAGISel::selectNode.
469 bool MipsSEDAGToDAGISel::
selectVSplatCommon(SDValue N,SDValue & Imm,bool Signed,unsigned ImmBitSize) const470 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
471 unsigned ImmBitSize) const {
472 APInt ImmValue;
473 EVT EltTy = N->getValueType(0).getVectorElementType();
474
475 if (N->getOpcode() == ISD::BITCAST)
476 N = N->getOperand(0);
477
478 if (selectVSplat (N.getNode(), ImmValue) &&
479 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
480 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
481 (!Signed && ImmValue.isIntN(ImmBitSize))) {
482 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
483 return true;
484 }
485 }
486
487 return false;
488 }
489
490 // Select constant vector splats.
491 bool MipsSEDAGToDAGISel::
selectVSplatUimm1(SDValue N,SDValue & Imm) const492 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
493 return selectVSplatCommon(N, Imm, false, 1);
494 }
495
496 bool MipsSEDAGToDAGISel::
selectVSplatUimm2(SDValue N,SDValue & Imm) const497 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
498 return selectVSplatCommon(N, Imm, false, 2);
499 }
500
501 bool MipsSEDAGToDAGISel::
selectVSplatUimm3(SDValue N,SDValue & Imm) const502 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
503 return selectVSplatCommon(N, Imm, false, 3);
504 }
505
506 // Select constant vector splats.
507 bool MipsSEDAGToDAGISel::
selectVSplatUimm4(SDValue N,SDValue & Imm) const508 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
509 return selectVSplatCommon(N, Imm, false, 4);
510 }
511
512 // Select constant vector splats.
513 bool MipsSEDAGToDAGISel::
selectVSplatUimm5(SDValue N,SDValue & Imm) const514 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
515 return selectVSplatCommon(N, Imm, false, 5);
516 }
517
518 // Select constant vector splats.
519 bool MipsSEDAGToDAGISel::
selectVSplatUimm6(SDValue N,SDValue & Imm) const520 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
521 return selectVSplatCommon(N, Imm, false, 6);
522 }
523
524 // Select constant vector splats.
525 bool MipsSEDAGToDAGISel::
selectVSplatUimm8(SDValue N,SDValue & Imm) const526 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
527 return selectVSplatCommon(N, Imm, false, 8);
528 }
529
530 // Select constant vector splats.
531 bool MipsSEDAGToDAGISel::
selectVSplatSimm5(SDValue N,SDValue & Imm) const532 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
533 return selectVSplatCommon(N, Imm, true, 5);
534 }
535
536 // Select constant vector splats whose value is a power of 2.
537 //
538 // In addition to the requirements of selectVSplat(), this function returns
539 // true and sets Imm if:
540 // * The splat value is the same width as the elements of the vector
541 // * The splat value is a power of two.
542 //
543 // This function looks through ISD::BITCAST nodes.
544 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
545 // sometimes a shuffle in big-endian mode.
selectVSplatUimmPow2(SDValue N,SDValue & Imm) const546 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
547 APInt ImmValue;
548 EVT EltTy = N->getValueType(0).getVectorElementType();
549
550 if (N->getOpcode() == ISD::BITCAST)
551 N = N->getOperand(0);
552
553 if (selectVSplat (N.getNode(), ImmValue) &&
554 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
555 int32_t Log2 = ImmValue.exactLogBase2();
556
557 if (Log2 != -1) {
558 Imm = CurDAG->getTargetConstant(Log2, EltTy);
559 return true;
560 }
561 }
562
563 return false;
564 }
565
566 // Select constant vector splats whose value only has a consecutive sequence
567 // of left-most bits set (e.g. 0b11...1100...00).
568 //
569 // In addition to the requirements of selectVSplat(), this function returns
570 // true and sets Imm if:
571 // * The splat value is the same width as the elements of the vector
572 // * The splat value is a consecutive sequence of left-most bits.
573 //
574 // This function looks through ISD::BITCAST nodes.
575 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
576 // sometimes a shuffle in big-endian mode.
selectVSplatMaskL(SDValue N,SDValue & Imm) const577 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
578 APInt ImmValue;
579 EVT EltTy = N->getValueType(0).getVectorElementType();
580
581 if (N->getOpcode() == ISD::BITCAST)
582 N = N->getOperand(0);
583
584 if (selectVSplat(N.getNode(), ImmValue) &&
585 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
586 // Extract the run of set bits starting with bit zero from the bitwise
587 // inverse of ImmValue, and test that the inverse of this is the same
588 // as the original value.
589 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
590
591 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
592 return true;
593 }
594 }
595
596 return false;
597 }
598
599 // Select constant vector splats whose value only has a consecutive sequence
600 // of right-most bits set (e.g. 0b00...0011...11).
601 //
602 // In addition to the requirements of selectVSplat(), this function returns
603 // true and sets Imm if:
604 // * The splat value is the same width as the elements of the vector
605 // * The splat value is a consecutive sequence of right-most bits.
606 //
607 // This function looks through ISD::BITCAST nodes.
608 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
609 // sometimes a shuffle in big-endian mode.
selectVSplatMaskR(SDValue N,SDValue & Imm) const610 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
611 APInt ImmValue;
612 EVT EltTy = N->getValueType(0).getVectorElementType();
613
614 if (N->getOpcode() == ISD::BITCAST)
615 N = N->getOperand(0);
616
617 if (selectVSplat(N.getNode(), ImmValue) &&
618 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
619 // Extract the run of set bits starting with bit zero, and test that the
620 // result is the same as the original value
621 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
622 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
623 return true;
624 }
625 }
626
627 return false;
628 }
629
selectVSplatUimmInvPow2(SDValue N,SDValue & Imm) const630 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
631 SDValue &Imm) const {
632 APInt ImmValue;
633 EVT EltTy = N->getValueType(0).getVectorElementType();
634
635 if (N->getOpcode() == ISD::BITCAST)
636 N = N->getOperand(0);
637
638 if (selectVSplat(N.getNode(), ImmValue) &&
639 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
640 int32_t Log2 = (~ImmValue).exactLogBase2();
641
642 if (Log2 != -1) {
643 Imm = CurDAG->getTargetConstant(Log2, EltTy);
644 return true;
645 }
646 }
647
648 return false;
649 }
650
selectNode(SDNode * Node)651 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
652 unsigned Opcode = Node->getOpcode();
653 SDLoc DL(Node);
654
655 ///
656 // Instruction Selection not handled by the auto-generated
657 // tablegen selection should be handled here.
658 ///
659 SDNode *Result;
660
661 switch(Opcode) {
662 default: break;
663
664 case ISD::SUBE: {
665 SDValue InFlag = Node->getOperand(2);
666 unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
667 Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
668 return std::make_pair(true, Result);
669 }
670
671 case ISD::ADDE: {
672 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
673 break;
674 SDValue InFlag = Node->getOperand(2);
675 unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
676 Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
677 return std::make_pair(true, Result);
678 }
679
680 case ISD::ConstantFP: {
681 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
682 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
683 if (Subtarget->isGP64bit()) {
684 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
685 Mips::ZERO_64, MVT::i64);
686 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
687 } else if (Subtarget->isFP64bit()) {
688 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
689 Mips::ZERO, MVT::i32);
690 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
691 Zero, Zero);
692 } else {
693 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
694 Mips::ZERO, MVT::i32);
695 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
696 Zero);
697 }
698
699 return std::make_pair(true, Result);
700 }
701 break;
702 }
703
704 case ISD::Constant: {
705 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
706 unsigned Size = CN->getValueSizeInBits(0);
707
708 if (Size == 32)
709 break;
710
711 MipsAnalyzeImmediate AnalyzeImm;
712 int64_t Imm = CN->getSExtValue();
713
714 const MipsAnalyzeImmediate::InstSeq &Seq =
715 AnalyzeImm.Analyze(Imm, Size, false);
716
717 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
718 SDLoc DL(CN);
719 SDNode *RegOpnd;
720 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
721 MVT::i64);
722
723 // The first instruction can be a LUi which is different from other
724 // instructions (ADDiu, ORI and SLL) in that it does not have a register
725 // operand.
726 if (Inst->Opc == Mips::LUi64)
727 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
728 else
729 RegOpnd =
730 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
731 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
732 ImmOpnd);
733
734 // The remaining instructions in the sequence are handled here.
735 for (++Inst; Inst != Seq.end(); ++Inst) {
736 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
737 MVT::i64);
738 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
739 SDValue(RegOpnd, 0), ImmOpnd);
740 }
741
742 return std::make_pair(true, RegOpnd);
743 }
744
745 case ISD::INTRINSIC_W_CHAIN: {
746 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
747 default:
748 break;
749
750 case Intrinsic::mips_cfcmsa: {
751 SDValue ChainIn = Node->getOperand(0);
752 SDValue RegIdx = Node->getOperand(2);
753 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
754 getMSACtrlReg(RegIdx), MVT::i32);
755 return std::make_pair(true, Reg.getNode());
756 }
757 }
758 break;
759 }
760
761 case ISD::INTRINSIC_WO_CHAIN: {
762 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
763 default:
764 break;
765
766 case Intrinsic::mips_move_v:
767 // Like an assignment but will always produce a move.v even if
768 // unnecessary.
769 return std::make_pair(true,
770 CurDAG->getMachineNode(Mips::MOVE_V, DL,
771 Node->getValueType(0),
772 Node->getOperand(1)));
773 }
774 break;
775 }
776
777 case ISD::INTRINSIC_VOID: {
778 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
779 default:
780 break;
781
782 case Intrinsic::mips_ctcmsa: {
783 SDValue ChainIn = Node->getOperand(0);
784 SDValue RegIdx = Node->getOperand(2);
785 SDValue Value = Node->getOperand(3);
786 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
787 getMSACtrlReg(RegIdx), Value);
788 return std::make_pair(true, ChainOut.getNode());
789 }
790 }
791 break;
792 }
793
794 case MipsISD::ThreadPointer: {
795 EVT PtrVT = getTargetLowering()->getPointerTy();
796 unsigned RdhwrOpc, DestReg;
797
798 if (PtrVT == MVT::i32) {
799 RdhwrOpc = Mips::RDHWR;
800 DestReg = Mips::V1;
801 } else {
802 RdhwrOpc = Mips::RDHWR64;
803 DestReg = Mips::V1_64;
804 }
805
806 SDNode *Rdhwr =
807 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
808 Node->getValueType(0),
809 CurDAG->getRegister(Mips::HWR29, MVT::i32));
810 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
811 SDValue(Rdhwr, 0));
812 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
813 ReplaceUses(SDValue(Node, 0), ResNode);
814 return std::make_pair(true, ResNode.getNode());
815 }
816
817 case ISD::BUILD_VECTOR: {
818 // Select appropriate ldi.[bhwd] instructions for constant splats of
819 // 128-bit when MSA is enabled. Fixup any register class mismatches that
820 // occur as a result.
821 //
822 // This allows the compiler to use a wider range of immediates than would
823 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
824 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
825 // 0x01010101 } without using a constant pool. This would be sub-optimal
826 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
827 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
828 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
829
830 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
831 APInt SplatValue, SplatUndef;
832 unsigned SplatBitSize;
833 bool HasAnyUndefs;
834 unsigned LdiOp;
835 EVT ResVecTy = BVN->getValueType(0);
836 EVT ViaVecTy;
837
838 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
839 return std::make_pair(false, nullptr);
840
841 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
842 HasAnyUndefs, 8,
843 !Subtarget->isLittle()))
844 return std::make_pair(false, nullptr);
845
846 switch (SplatBitSize) {
847 default:
848 return std::make_pair(false, nullptr);
849 case 8:
850 LdiOp = Mips::LDI_B;
851 ViaVecTy = MVT::v16i8;
852 break;
853 case 16:
854 LdiOp = Mips::LDI_H;
855 ViaVecTy = MVT::v8i16;
856 break;
857 case 32:
858 LdiOp = Mips::LDI_W;
859 ViaVecTy = MVT::v4i32;
860 break;
861 case 64:
862 LdiOp = Mips::LDI_D;
863 ViaVecTy = MVT::v2i64;
864 break;
865 }
866
867 if (!SplatValue.isSignedIntN(10))
868 return std::make_pair(false, nullptr);
869
870 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
871 ViaVecTy.getVectorElementType());
872
873 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
874
875 if (ResVecTy != ViaVecTy) {
876 // If LdiOp is writing to a different register class to ResVecTy, then
877 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
878 // since the source and destination register sets contain the same
879 // registers.
880 const TargetLowering *TLI = getTargetLowering();
881 MVT ResVecTySimple = ResVecTy.getSimpleVT();
882 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
883 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
884 ResVecTy, SDValue(Res, 0),
885 CurDAG->getTargetConstant(RC->getID(),
886 MVT::i32));
887 }
888
889 return std::make_pair(true, Res);
890 }
891
892 }
893
894 return std::make_pair(false, nullptr);
895 }
896
createMipsSEISelDag(MipsTargetMachine & TM)897 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
898 return new MipsSEDAGToDAGISel(TM);
899 }
900