1f4a2713aSLionel Sambuc //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===// 2f4a2713aSLionel Sambuc // 3f4a2713aSLionel Sambuc // The LLVM Compiler Infrastructure 4f4a2713aSLionel Sambuc // 5f4a2713aSLionel Sambuc // This file is distributed under the University of Illinois Open Source 6f4a2713aSLionel Sambuc // License. See LICENSE.TXT for details. 7f4a2713aSLionel Sambuc // 8f4a2713aSLionel Sambuc //===----------------------------------------------------------------------===// 9f4a2713aSLionel Sambuc // 10f4a2713aSLionel Sambuc // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11f4a2713aSLionel Sambuc // 12f4a2713aSLionel Sambuc //===----------------------------------------------------------------------===// 13f4a2713aSLionel Sambuc 14*0a6a1f1dSLionel Sambuc #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H 15*0a6a1f1dSLionel Sambuc #define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H 16f4a2713aSLionel Sambuc 17f4a2713aSLionel Sambuc #include "MipsInstrInfo.h" 18f4a2713aSLionel Sambuc #include "MipsSERegisterInfo.h" 19f4a2713aSLionel Sambuc 20f4a2713aSLionel Sambuc namespace llvm { 21f4a2713aSLionel Sambuc 22f4a2713aSLionel Sambuc class MipsSEInstrInfo : public MipsInstrInfo { 23f4a2713aSLionel Sambuc const MipsSERegisterInfo RI; 24f4a2713aSLionel Sambuc 25f4a2713aSLionel Sambuc public: 26*0a6a1f1dSLionel Sambuc explicit MipsSEInstrInfo(const MipsSubtarget &STI); 27f4a2713aSLionel Sambuc 28*0a6a1f1dSLionel Sambuc const MipsRegisterInfo &getRegisterInfo() const override; 29f4a2713aSLionel Sambuc 30f4a2713aSLionel Sambuc /// isLoadFromStackSlot - If the specified machine instruction is a direct 31f4a2713aSLionel Sambuc /// load from a stack slot, return the virtual or physical register number of 32f4a2713aSLionel Sambuc /// the destination along with the FrameIndex of the loaded stack slot. If 33f4a2713aSLionel Sambuc /// not, return 0. This predicate must return 0 if the instruction has 34f4a2713aSLionel Sambuc /// any side effects other than loading from the stack slot. 35*0a6a1f1dSLionel Sambuc unsigned isLoadFromStackSlot(const MachineInstr *MI, 36*0a6a1f1dSLionel Sambuc int &FrameIndex) const override; 37f4a2713aSLionel Sambuc 38f4a2713aSLionel Sambuc /// isStoreToStackSlot - If the specified machine instruction is a direct 39f4a2713aSLionel Sambuc /// store to a stack slot, return the virtual or physical register number of 40f4a2713aSLionel Sambuc /// the source reg along with the FrameIndex of the loaded stack slot. If 41f4a2713aSLionel Sambuc /// not, return 0. This predicate must return 0 if the instruction has 42f4a2713aSLionel Sambuc /// any side effects other than storing to the stack slot. 43*0a6a1f1dSLionel Sambuc unsigned isStoreToStackSlot(const MachineInstr *MI, 44*0a6a1f1dSLionel Sambuc int &FrameIndex) const override; 45f4a2713aSLionel Sambuc 46*0a6a1f1dSLionel Sambuc void copyPhysReg(MachineBasicBlock &MBB, 47f4a2713aSLionel Sambuc MachineBasicBlock::iterator MI, DebugLoc DL, 48f4a2713aSLionel Sambuc unsigned DestReg, unsigned SrcReg, 49*0a6a1f1dSLionel Sambuc bool KillSrc) const override; 50f4a2713aSLionel Sambuc 51*0a6a1f1dSLionel Sambuc void storeRegToStack(MachineBasicBlock &MBB, 52f4a2713aSLionel Sambuc MachineBasicBlock::iterator MI, 53f4a2713aSLionel Sambuc unsigned SrcReg, bool isKill, int FrameIndex, 54f4a2713aSLionel Sambuc const TargetRegisterClass *RC, 55f4a2713aSLionel Sambuc const TargetRegisterInfo *TRI, 56*0a6a1f1dSLionel Sambuc int64_t Offset) const override; 57f4a2713aSLionel Sambuc 58*0a6a1f1dSLionel Sambuc void loadRegFromStack(MachineBasicBlock &MBB, 59f4a2713aSLionel Sambuc MachineBasicBlock::iterator MI, 60f4a2713aSLionel Sambuc unsigned DestReg, int FrameIndex, 61f4a2713aSLionel Sambuc const TargetRegisterClass *RC, 62f4a2713aSLionel Sambuc const TargetRegisterInfo *TRI, 63*0a6a1f1dSLionel Sambuc int64_t Offset) const override; 64f4a2713aSLionel Sambuc 65*0a6a1f1dSLionel Sambuc bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 66f4a2713aSLionel Sambuc 67*0a6a1f1dSLionel Sambuc unsigned getOppositeBranchOpc(unsigned Opc) const override; 68f4a2713aSLionel Sambuc 69f4a2713aSLionel Sambuc /// Adjust SP by Amount bytes. 70f4a2713aSLionel Sambuc void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, 71f4a2713aSLionel Sambuc MachineBasicBlock::iterator I) const; 72f4a2713aSLionel Sambuc 73f4a2713aSLionel Sambuc /// Emit a series of instructions to load an immediate. If NewImm is a 74f4a2713aSLionel Sambuc /// non-NULL parameter, the last instruction is not emitted, but instead 75f4a2713aSLionel Sambuc /// its immediate operand is returned in NewImm. 76f4a2713aSLionel Sambuc unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 77f4a2713aSLionel Sambuc MachineBasicBlock::iterator II, DebugLoc DL, 78f4a2713aSLionel Sambuc unsigned *NewImm) const; 79f4a2713aSLionel Sambuc 80f4a2713aSLionel Sambuc private: 81*0a6a1f1dSLionel Sambuc unsigned getAnalyzableBrOpc(unsigned Opc) const override; 82f4a2713aSLionel Sambuc 83*0a6a1f1dSLionel Sambuc void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; 84f4a2713aSLionel Sambuc 85f4a2713aSLionel Sambuc std::pair<bool, bool> compareOpndSize(unsigned Opc, 86f4a2713aSLionel Sambuc const MachineFunction &MF) const; 87f4a2713aSLionel Sambuc 88f4a2713aSLionel Sambuc void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 89f4a2713aSLionel Sambuc unsigned NewOpc) const; 90f4a2713aSLionel Sambuc 91f4a2713aSLionel Sambuc void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 92f4a2713aSLionel Sambuc unsigned LoOpc, unsigned HiOpc, 93f4a2713aSLionel Sambuc bool HasExplicitDef) const; 94f4a2713aSLionel Sambuc 95f4a2713aSLionel Sambuc /// Expand pseudo Int-to-FP conversion instructions. 96f4a2713aSLionel Sambuc /// 97f4a2713aSLionel Sambuc /// For example, the following pseudo instruction 98f4a2713aSLionel Sambuc /// PseudoCVT_D32_W D2, A5 99f4a2713aSLionel Sambuc /// gets expanded into these two instructions: 100f4a2713aSLionel Sambuc /// MTC1 F4, A5 101f4a2713aSLionel Sambuc /// CVT_D32_W D2, F4 102f4a2713aSLionel Sambuc /// 103f4a2713aSLionel Sambuc /// We do this expansion post-RA to avoid inserting a floating point copy 104f4a2713aSLionel Sambuc /// instruction between MTC1 and CVT_D32_W. 105f4a2713aSLionel Sambuc void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 106f4a2713aSLionel Sambuc unsigned CvtOpc, unsigned MovOpc, bool IsI64) const; 107f4a2713aSLionel Sambuc 108f4a2713aSLionel Sambuc void expandExtractElementF64(MachineBasicBlock &MBB, 109f4a2713aSLionel Sambuc MachineBasicBlock::iterator I, bool FP64) const; 110f4a2713aSLionel Sambuc void expandBuildPairF64(MachineBasicBlock &MBB, 111f4a2713aSLionel Sambuc MachineBasicBlock::iterator I, bool FP64) const; 112f4a2713aSLionel Sambuc void expandEhReturn(MachineBasicBlock &MBB, 113f4a2713aSLionel Sambuc MachineBasicBlock::iterator I) const; 114f4a2713aSLionel Sambuc }; 115f4a2713aSLionel Sambuc 116f4a2713aSLionel Sambuc } 117f4a2713aSLionel Sambuc 118f4a2713aSLionel Sambuc #endif 119