1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Mips target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsTargetMachine.h" 15 #include "Mips.h" 16 #include "MipsFrameLowering.h" 17 #include "MipsInstrInfo.h" 18 #include "MipsModuleISelDAGToDAG.h" 19 #include "MipsOs16.h" 20 #include "MipsSEFrameLowering.h" 21 #include "MipsSEInstrInfo.h" 22 #include "MipsSEISelLowering.h" 23 #include "MipsSEISelDAGToDAG.h" 24 #include "Mips16FrameLowering.h" 25 #include "Mips16HardFloat.h" 26 #include "Mips16InstrInfo.h" 27 #include "Mips16ISelDAGToDAG.h" 28 #include "Mips16ISelLowering.h" 29 #include "llvm/Analysis/TargetTransformInfo.h" 30 #include "llvm/CodeGen/Passes.h" 31 #include "llvm/PassManager.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/raw_ostream.h" 34 #include "llvm/Support/TargetRegistry.h" 35 #include "llvm/Transforms/Scalar.h" 36 using namespace llvm; 37 38 39 40 extern "C" void LLVMInitializeMipsTarget() { 41 // Register the target. 42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget); 43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget); 44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target); 45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget); 46 } 47 48 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment 49 // The stack is always 8 byte aligned 50 // On function prologue, the stack is created by decrementing 51 // its pointer. Once decremented, all references are done with positive 52 // offset from the stack/frame pointer, using StackGrowsUp enables 53 // an easier handling. 54 // Using CodeModel::Large enables different CALL behavior. 55 MipsTargetMachine:: 56 MipsTargetMachine(const Target &T, StringRef TT, 57 StringRef CPU, StringRef FS, const TargetOptions &Options, 58 Reloc::Model RM, CodeModel::Model CM, 59 CodeGenOpt::Level OL, 60 bool isLittle) 61 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 62 Subtarget(TT, CPU, FS, isLittle, RM, this), 63 DL(isLittle ? 64 (Subtarget.isABI_N64() ? 65 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-" 66 "n32:64-S128" : 67 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64") : 68 (Subtarget.isABI_N64() ? 69 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-" 70 "n32:64-S128" : 71 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64")), 72 InstrInfo(MipsInstrInfo::create(*this)), 73 FrameLowering(MipsFrameLowering::create(*this, Subtarget)), 74 TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this), 75 InstrItins(Subtarget.getInstrItineraryData()), JITInfo() { 76 initAsmInfo(); 77 } 78 79 80 void MipsTargetMachine::setHelperClassesMips16() { 81 InstrInfoSE.swap(InstrInfo); 82 FrameLoweringSE.swap(FrameLowering); 83 TLInfoSE.swap(TLInfo); 84 if (!InstrInfo16) { 85 InstrInfo.reset(MipsInstrInfo::create(*this)); 86 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget)); 87 TLInfo.reset(MipsTargetLowering::create(*this)); 88 } else { 89 InstrInfo16.swap(InstrInfo); 90 FrameLowering16.swap(FrameLowering); 91 TLInfo16.swap(TLInfo); 92 } 93 assert(TLInfo && "null target lowering 16"); 94 assert(InstrInfo && "null instr info 16"); 95 assert(FrameLowering && "null frame lowering 16"); 96 } 97 98 void MipsTargetMachine::setHelperClassesMipsSE() { 99 InstrInfo16.swap(InstrInfo); 100 FrameLowering16.swap(FrameLowering); 101 TLInfo16.swap(TLInfo); 102 if (!InstrInfoSE) { 103 InstrInfo.reset(MipsInstrInfo::create(*this)); 104 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget)); 105 TLInfo.reset(MipsTargetLowering::create(*this)); 106 } else { 107 InstrInfoSE.swap(InstrInfo); 108 FrameLoweringSE.swap(FrameLowering); 109 TLInfoSE.swap(TLInfo); 110 } 111 assert(TLInfo && "null target lowering in SE"); 112 assert(InstrInfo && "null instr info SE"); 113 assert(FrameLowering && "null frame lowering SE"); 114 } 115 void MipsebTargetMachine::anchor() { } 116 117 MipsebTargetMachine:: 118 MipsebTargetMachine(const Target &T, StringRef TT, 119 StringRef CPU, StringRef FS, const TargetOptions &Options, 120 Reloc::Model RM, CodeModel::Model CM, 121 CodeGenOpt::Level OL) 122 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 123 124 void MipselTargetMachine::anchor() { } 125 126 MipselTargetMachine:: 127 MipselTargetMachine(const Target &T, StringRef TT, 128 StringRef CPU, StringRef FS, const TargetOptions &Options, 129 Reloc::Model RM, CodeModel::Model CM, 130 CodeGenOpt::Level OL) 131 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 132 133 namespace { 134 /// Mips Code Generator Pass Configuration Options. 135 class MipsPassConfig : public TargetPassConfig { 136 public: 137 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM) 138 : TargetPassConfig(TM, PM) { 139 // The current implementation of long branch pass requires a scratch 140 // register ($at) to be available before branch instructions. Tail merging 141 // can break this requirement, so disable it when long branch pass is 142 // enabled. 143 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); 144 } 145 146 MipsTargetMachine &getMipsTargetMachine() const { 147 return getTM<MipsTargetMachine>(); 148 } 149 150 const MipsSubtarget &getMipsSubtarget() const { 151 return *getMipsTargetMachine().getSubtargetImpl(); 152 } 153 154 virtual void addIRPasses(); 155 virtual bool addInstSelector(); 156 virtual bool addPreEmitPass(); 157 }; 158 } // namespace 159 160 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 161 return new MipsPassConfig(this, PM); 162 } 163 164 void MipsPassConfig::addIRPasses() { 165 TargetPassConfig::addIRPasses(); 166 if (getMipsSubtarget().os16()) 167 addPass(createMipsOs16(getMipsTargetMachine())); 168 if (getMipsSubtarget().inMips16HardFloat()) 169 addPass(createMips16HardFloat(getMipsTargetMachine())); 170 addPass(createPartiallyInlineLibCallsPass()); 171 } 172 // Install an instruction selector pass using 173 // the ISelDag to gen Mips code. 174 bool MipsPassConfig::addInstSelector() { 175 if (getMipsSubtarget().allowMixed16_32()) { 176 addPass(createMipsModuleISelDag(getMipsTargetMachine())); 177 addPass(createMips16ISelDag(getMipsTargetMachine())); 178 addPass(createMipsSEISelDag(getMipsTargetMachine())); 179 } else { 180 addPass(createMipsISelDag(getMipsTargetMachine())); 181 } 182 return false; 183 } 184 185 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) { 186 if (Subtarget.allowMixed16_32()) { 187 DEBUG(errs() << "No "); 188 //FIXME: The Basic Target Transform Info 189 // pass needs to become a function pass instead of 190 // being an immutable pass and then this method as it exists now 191 // would be unnecessary. 192 PM.add(createNoTargetTransformInfoPass()); 193 } else 194 LLVMTargetMachine::addAnalysisPasses(PM); 195 DEBUG(errs() << "Target Transform Info Pass Added\n"); 196 } 197 198 // Implemented by targets that want to run passes immediately before 199 // machine code is emitted. return true if -print-machineinstrs should 200 // print out the code after the passes. 201 bool MipsPassConfig::addPreEmitPass() { 202 MipsTargetMachine &TM = getMipsTargetMachine(); 203 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); 204 addPass(createMipsDelaySlotFillerPass(TM)); 205 206 if (Subtarget.enableLongBranchPass()) 207 addPass(createMipsLongBranchPass(TM)); 208 if (Subtarget.inMips16Mode() || 209 Subtarget.allowMixed16_32()) 210 addPass(createMipsConstantIslandPass(TM)); 211 212 return true; 213 } 214 215 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM, 216 JITCodeEmitter &JCE) { 217 // Machine code emitter pass for Mips. 218 PM.add(createMipsJITCodeEmitterPass(*this, JCE)); 219 return false; 220 } 221