1 //===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines an instruction selector for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
16 
17 #include "NVPTX.h"
18 #include "NVPTXISelLowering.h"
19 #include "NVPTXRegisterInfo.h"
20 #include "NVPTXTargetMachine.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/IR/Intrinsics.h"
23 #include "llvm/Support/Compiler.h"
24 using namespace llvm;
25 
26 namespace {
27 
28 class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
29 
30   // If true, generate mul.wide from sext and mul
31   bool doMulWide;
32 
33   int getDivF32Level() const;
34   bool usePrecSqrtF32() const;
35   bool useF32FTZ() const;
36   bool allowFMA() const;
37 
38 public:
39   explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
40                              CodeGenOpt::Level   OptLevel);
41 
42   // Pass Name
43   const char *getPassName() const override {
44     return "NVPTX DAG->DAG Pattern Instruction Selection";
45   }
46 
47   const NVPTXSubtarget &Subtarget;
48 
49   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
50                                     char ConstraintCode,
51                                     std::vector<SDValue> &OutOps) override;
52 private:
53 // Include the pieces autogenerated from the target description.
54 #include "NVPTXGenDAGISel.inc"
55 
56   SDNode *Select(SDNode *N) override;
57   SDNode *SelectIntrinsicNoChain(SDNode *N);
58   SDNode *SelectIntrinsicChain(SDNode *N);
59   SDNode *SelectTexSurfHandle(SDNode *N);
60   SDNode *SelectLoad(SDNode *N);
61   SDNode *SelectLoadVector(SDNode *N);
62   SDNode *SelectLDGLDU(SDNode *N);
63   SDNode *SelectStore(SDNode *N);
64   SDNode *SelectStoreVector(SDNode *N);
65   SDNode *SelectLoadParam(SDNode *N);
66   SDNode *SelectStoreRetval(SDNode *N);
67   SDNode *SelectStoreParam(SDNode *N);
68   SDNode *SelectAddrSpaceCast(SDNode *N);
69   SDNode *SelectTextureIntrinsic(SDNode *N);
70   SDNode *SelectSurfaceIntrinsic(SDNode *N);
71   SDNode *SelectBFE(SDNode *N);
72 
73   inline SDValue getI32Imm(unsigned Imm) {
74     return CurDAG->getTargetConstant(Imm, MVT::i32);
75   }
76 
77   // Match direct address complex pattern.
78   bool SelectDirectAddr(SDValue N, SDValue &Address);
79 
80   bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
81                         SDValue &Offset, MVT mvt);
82   bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
83                     SDValue &Offset);
84   bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
85                       SDValue &Offset);
86 
87   bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
88                         SDValue &Offset, MVT mvt);
89   bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
90                     SDValue &Offset);
91   bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
92                       SDValue &Offset);
93 
94   bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
95 
96 };
97 }
98 
99 #endif
100