1f4a2713aSLionel Sambuc //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2f4a2713aSLionel Sambuc //
3f4a2713aSLionel Sambuc // The LLVM Compiler Infrastructure
4f4a2713aSLionel Sambuc //
5f4a2713aSLionel Sambuc // This file is distributed under the University of Illinois Open Source
6f4a2713aSLionel Sambuc // License. See LICENSE.TXT for details.
7f4a2713aSLionel Sambuc //
8f4a2713aSLionel Sambuc //===----------------------------------------------------------------------===//
9f4a2713aSLionel Sambuc //
10f4a2713aSLionel Sambuc // This file contains the PPC implementation of TargetFrameLowering class.
11f4a2713aSLionel Sambuc //
12f4a2713aSLionel Sambuc //===----------------------------------------------------------------------===//
13f4a2713aSLionel Sambuc
14f4a2713aSLionel Sambuc #include "PPCFrameLowering.h"
15f4a2713aSLionel Sambuc #include "PPCInstrBuilder.h"
16f4a2713aSLionel Sambuc #include "PPCInstrInfo.h"
17f4a2713aSLionel Sambuc #include "PPCMachineFunctionInfo.h"
18*0a6a1f1dSLionel Sambuc #include "PPCSubtarget.h"
19f4a2713aSLionel Sambuc #include "llvm/CodeGen/MachineFrameInfo.h"
20f4a2713aSLionel Sambuc #include "llvm/CodeGen/MachineFunction.h"
21f4a2713aSLionel Sambuc #include "llvm/CodeGen/MachineInstrBuilder.h"
22f4a2713aSLionel Sambuc #include "llvm/CodeGen/MachineModuleInfo.h"
23f4a2713aSLionel Sambuc #include "llvm/CodeGen/MachineRegisterInfo.h"
24f4a2713aSLionel Sambuc #include "llvm/CodeGen/RegisterScavenging.h"
25f4a2713aSLionel Sambuc #include "llvm/IR/Function.h"
26f4a2713aSLionel Sambuc #include "llvm/Target/TargetOptions.h"
27f4a2713aSLionel Sambuc
28f4a2713aSLionel Sambuc using namespace llvm;
29f4a2713aSLionel Sambuc
30f4a2713aSLionel Sambuc /// VRRegNo - Map from a numbered VR register to its enum value.
31f4a2713aSLionel Sambuc ///
32f4a2713aSLionel Sambuc static const uint16_t VRRegNo[] = {
33f4a2713aSLionel Sambuc PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34f4a2713aSLionel Sambuc PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35f4a2713aSLionel Sambuc PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36f4a2713aSLionel Sambuc PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
37f4a2713aSLionel Sambuc };
38f4a2713aSLionel Sambuc
PPCFrameLowering(const PPCSubtarget & STI)39*0a6a1f1dSLionel Sambuc PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
40*0a6a1f1dSLionel Sambuc : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
41*0a6a1f1dSLionel Sambuc (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
42*0a6a1f1dSLionel Sambuc Subtarget(STI) {}
43*0a6a1f1dSLionel Sambuc
44*0a6a1f1dSLionel Sambuc // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
getCalleeSavedSpillSlots(unsigned & NumEntries) const45*0a6a1f1dSLionel Sambuc const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
46*0a6a1f1dSLionel Sambuc unsigned &NumEntries) const {
47*0a6a1f1dSLionel Sambuc if (Subtarget.isDarwinABI()) {
48*0a6a1f1dSLionel Sambuc NumEntries = 1;
49*0a6a1f1dSLionel Sambuc if (Subtarget.isPPC64()) {
50*0a6a1f1dSLionel Sambuc static const SpillSlot darwin64Offsets = {PPC::X31, -8};
51*0a6a1f1dSLionel Sambuc return &darwin64Offsets;
52*0a6a1f1dSLionel Sambuc } else {
53*0a6a1f1dSLionel Sambuc static const SpillSlot darwinOffsets = {PPC::R31, -4};
54*0a6a1f1dSLionel Sambuc return &darwinOffsets;
55*0a6a1f1dSLionel Sambuc }
56*0a6a1f1dSLionel Sambuc }
57*0a6a1f1dSLionel Sambuc
58*0a6a1f1dSLionel Sambuc // Early exit if not using the SVR4 ABI.
59*0a6a1f1dSLionel Sambuc if (!Subtarget.isSVR4ABI()) {
60*0a6a1f1dSLionel Sambuc NumEntries = 0;
61*0a6a1f1dSLionel Sambuc return nullptr;
62*0a6a1f1dSLionel Sambuc }
63*0a6a1f1dSLionel Sambuc
64*0a6a1f1dSLionel Sambuc // Note that the offsets here overlap, but this is fixed up in
65*0a6a1f1dSLionel Sambuc // processFunctionBeforeFrameFinalized.
66*0a6a1f1dSLionel Sambuc
67*0a6a1f1dSLionel Sambuc static const SpillSlot Offsets[] = {
68*0a6a1f1dSLionel Sambuc // Floating-point register save area offsets.
69*0a6a1f1dSLionel Sambuc {PPC::F31, -8},
70*0a6a1f1dSLionel Sambuc {PPC::F30, -16},
71*0a6a1f1dSLionel Sambuc {PPC::F29, -24},
72*0a6a1f1dSLionel Sambuc {PPC::F28, -32},
73*0a6a1f1dSLionel Sambuc {PPC::F27, -40},
74*0a6a1f1dSLionel Sambuc {PPC::F26, -48},
75*0a6a1f1dSLionel Sambuc {PPC::F25, -56},
76*0a6a1f1dSLionel Sambuc {PPC::F24, -64},
77*0a6a1f1dSLionel Sambuc {PPC::F23, -72},
78*0a6a1f1dSLionel Sambuc {PPC::F22, -80},
79*0a6a1f1dSLionel Sambuc {PPC::F21, -88},
80*0a6a1f1dSLionel Sambuc {PPC::F20, -96},
81*0a6a1f1dSLionel Sambuc {PPC::F19, -104},
82*0a6a1f1dSLionel Sambuc {PPC::F18, -112},
83*0a6a1f1dSLionel Sambuc {PPC::F17, -120},
84*0a6a1f1dSLionel Sambuc {PPC::F16, -128},
85*0a6a1f1dSLionel Sambuc {PPC::F15, -136},
86*0a6a1f1dSLionel Sambuc {PPC::F14, -144},
87*0a6a1f1dSLionel Sambuc
88*0a6a1f1dSLionel Sambuc // General register save area offsets.
89*0a6a1f1dSLionel Sambuc {PPC::R31, -4},
90*0a6a1f1dSLionel Sambuc {PPC::R30, -8},
91*0a6a1f1dSLionel Sambuc {PPC::R29, -12},
92*0a6a1f1dSLionel Sambuc {PPC::R28, -16},
93*0a6a1f1dSLionel Sambuc {PPC::R27, -20},
94*0a6a1f1dSLionel Sambuc {PPC::R26, -24},
95*0a6a1f1dSLionel Sambuc {PPC::R25, -28},
96*0a6a1f1dSLionel Sambuc {PPC::R24, -32},
97*0a6a1f1dSLionel Sambuc {PPC::R23, -36},
98*0a6a1f1dSLionel Sambuc {PPC::R22, -40},
99*0a6a1f1dSLionel Sambuc {PPC::R21, -44},
100*0a6a1f1dSLionel Sambuc {PPC::R20, -48},
101*0a6a1f1dSLionel Sambuc {PPC::R19, -52},
102*0a6a1f1dSLionel Sambuc {PPC::R18, -56},
103*0a6a1f1dSLionel Sambuc {PPC::R17, -60},
104*0a6a1f1dSLionel Sambuc {PPC::R16, -64},
105*0a6a1f1dSLionel Sambuc {PPC::R15, -68},
106*0a6a1f1dSLionel Sambuc {PPC::R14, -72},
107*0a6a1f1dSLionel Sambuc
108*0a6a1f1dSLionel Sambuc // CR save area offset. We map each of the nonvolatile CR fields
109*0a6a1f1dSLionel Sambuc // to the slot for CR2, which is the first of the nonvolatile CR
110*0a6a1f1dSLionel Sambuc // fields to be assigned, so that we only allocate one save slot.
111*0a6a1f1dSLionel Sambuc // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
112*0a6a1f1dSLionel Sambuc {PPC::CR2, -4},
113*0a6a1f1dSLionel Sambuc
114*0a6a1f1dSLionel Sambuc // VRSAVE save area offset.
115*0a6a1f1dSLionel Sambuc {PPC::VRSAVE, -4},
116*0a6a1f1dSLionel Sambuc
117*0a6a1f1dSLionel Sambuc // Vector register save area
118*0a6a1f1dSLionel Sambuc {PPC::V31, -16},
119*0a6a1f1dSLionel Sambuc {PPC::V30, -32},
120*0a6a1f1dSLionel Sambuc {PPC::V29, -48},
121*0a6a1f1dSLionel Sambuc {PPC::V28, -64},
122*0a6a1f1dSLionel Sambuc {PPC::V27, -80},
123*0a6a1f1dSLionel Sambuc {PPC::V26, -96},
124*0a6a1f1dSLionel Sambuc {PPC::V25, -112},
125*0a6a1f1dSLionel Sambuc {PPC::V24, -128},
126*0a6a1f1dSLionel Sambuc {PPC::V23, -144},
127*0a6a1f1dSLionel Sambuc {PPC::V22, -160},
128*0a6a1f1dSLionel Sambuc {PPC::V21, -176},
129*0a6a1f1dSLionel Sambuc {PPC::V20, -192}};
130*0a6a1f1dSLionel Sambuc
131*0a6a1f1dSLionel Sambuc static const SpillSlot Offsets64[] = {
132*0a6a1f1dSLionel Sambuc // Floating-point register save area offsets.
133*0a6a1f1dSLionel Sambuc {PPC::F31, -8},
134*0a6a1f1dSLionel Sambuc {PPC::F30, -16},
135*0a6a1f1dSLionel Sambuc {PPC::F29, -24},
136*0a6a1f1dSLionel Sambuc {PPC::F28, -32},
137*0a6a1f1dSLionel Sambuc {PPC::F27, -40},
138*0a6a1f1dSLionel Sambuc {PPC::F26, -48},
139*0a6a1f1dSLionel Sambuc {PPC::F25, -56},
140*0a6a1f1dSLionel Sambuc {PPC::F24, -64},
141*0a6a1f1dSLionel Sambuc {PPC::F23, -72},
142*0a6a1f1dSLionel Sambuc {PPC::F22, -80},
143*0a6a1f1dSLionel Sambuc {PPC::F21, -88},
144*0a6a1f1dSLionel Sambuc {PPC::F20, -96},
145*0a6a1f1dSLionel Sambuc {PPC::F19, -104},
146*0a6a1f1dSLionel Sambuc {PPC::F18, -112},
147*0a6a1f1dSLionel Sambuc {PPC::F17, -120},
148*0a6a1f1dSLionel Sambuc {PPC::F16, -128},
149*0a6a1f1dSLionel Sambuc {PPC::F15, -136},
150*0a6a1f1dSLionel Sambuc {PPC::F14, -144},
151*0a6a1f1dSLionel Sambuc
152*0a6a1f1dSLionel Sambuc // General register save area offsets.
153*0a6a1f1dSLionel Sambuc {PPC::X31, -8},
154*0a6a1f1dSLionel Sambuc {PPC::X30, -16},
155*0a6a1f1dSLionel Sambuc {PPC::X29, -24},
156*0a6a1f1dSLionel Sambuc {PPC::X28, -32},
157*0a6a1f1dSLionel Sambuc {PPC::X27, -40},
158*0a6a1f1dSLionel Sambuc {PPC::X26, -48},
159*0a6a1f1dSLionel Sambuc {PPC::X25, -56},
160*0a6a1f1dSLionel Sambuc {PPC::X24, -64},
161*0a6a1f1dSLionel Sambuc {PPC::X23, -72},
162*0a6a1f1dSLionel Sambuc {PPC::X22, -80},
163*0a6a1f1dSLionel Sambuc {PPC::X21, -88},
164*0a6a1f1dSLionel Sambuc {PPC::X20, -96},
165*0a6a1f1dSLionel Sambuc {PPC::X19, -104},
166*0a6a1f1dSLionel Sambuc {PPC::X18, -112},
167*0a6a1f1dSLionel Sambuc {PPC::X17, -120},
168*0a6a1f1dSLionel Sambuc {PPC::X16, -128},
169*0a6a1f1dSLionel Sambuc {PPC::X15, -136},
170*0a6a1f1dSLionel Sambuc {PPC::X14, -144},
171*0a6a1f1dSLionel Sambuc
172*0a6a1f1dSLionel Sambuc // VRSAVE save area offset.
173*0a6a1f1dSLionel Sambuc {PPC::VRSAVE, -4},
174*0a6a1f1dSLionel Sambuc
175*0a6a1f1dSLionel Sambuc // Vector register save area
176*0a6a1f1dSLionel Sambuc {PPC::V31, -16},
177*0a6a1f1dSLionel Sambuc {PPC::V30, -32},
178*0a6a1f1dSLionel Sambuc {PPC::V29, -48},
179*0a6a1f1dSLionel Sambuc {PPC::V28, -64},
180*0a6a1f1dSLionel Sambuc {PPC::V27, -80},
181*0a6a1f1dSLionel Sambuc {PPC::V26, -96},
182*0a6a1f1dSLionel Sambuc {PPC::V25, -112},
183*0a6a1f1dSLionel Sambuc {PPC::V24, -128},
184*0a6a1f1dSLionel Sambuc {PPC::V23, -144},
185*0a6a1f1dSLionel Sambuc {PPC::V22, -160},
186*0a6a1f1dSLionel Sambuc {PPC::V21, -176},
187*0a6a1f1dSLionel Sambuc {PPC::V20, -192}};
188*0a6a1f1dSLionel Sambuc
189*0a6a1f1dSLionel Sambuc if (Subtarget.isPPC64()) {
190*0a6a1f1dSLionel Sambuc NumEntries = array_lengthof(Offsets64);
191*0a6a1f1dSLionel Sambuc
192*0a6a1f1dSLionel Sambuc return Offsets64;
193*0a6a1f1dSLionel Sambuc } else {
194*0a6a1f1dSLionel Sambuc NumEntries = array_lengthof(Offsets);
195*0a6a1f1dSLionel Sambuc
196*0a6a1f1dSLionel Sambuc return Offsets;
197*0a6a1f1dSLionel Sambuc }
198*0a6a1f1dSLionel Sambuc }
199*0a6a1f1dSLionel Sambuc
200f4a2713aSLionel Sambuc /// RemoveVRSaveCode - We have found that this function does not need any code
201f4a2713aSLionel Sambuc /// to manipulate the VRSAVE register, even though it uses vector registers.
202f4a2713aSLionel Sambuc /// This can happen when the only registers used are known to be live in or out
203f4a2713aSLionel Sambuc /// of the function. Remove all of the VRSAVE related code from the function.
204f4a2713aSLionel Sambuc /// FIXME: The removal of the code results in a compile failure at -O0 when the
205f4a2713aSLionel Sambuc /// function contains a function call, as the GPR containing original VRSAVE
206f4a2713aSLionel Sambuc /// contents is spilled and reloaded around the call. Without the prolog code,
207f4a2713aSLionel Sambuc /// the spill instruction refers to an undefined register. This code needs
208f4a2713aSLionel Sambuc /// to account for all uses of that GPR.
RemoveVRSaveCode(MachineInstr * MI)209f4a2713aSLionel Sambuc static void RemoveVRSaveCode(MachineInstr *MI) {
210f4a2713aSLionel Sambuc MachineBasicBlock *Entry = MI->getParent();
211f4a2713aSLionel Sambuc MachineFunction *MF = Entry->getParent();
212f4a2713aSLionel Sambuc
213f4a2713aSLionel Sambuc // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
214f4a2713aSLionel Sambuc MachineBasicBlock::iterator MBBI = MI;
215f4a2713aSLionel Sambuc ++MBBI;
216f4a2713aSLionel Sambuc assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
217f4a2713aSLionel Sambuc MBBI->eraseFromParent();
218f4a2713aSLionel Sambuc
219f4a2713aSLionel Sambuc bool RemovedAllMTVRSAVEs = true;
220f4a2713aSLionel Sambuc // See if we can find and remove the MTVRSAVE instruction from all of the
221f4a2713aSLionel Sambuc // epilog blocks.
222f4a2713aSLionel Sambuc for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
223f4a2713aSLionel Sambuc // If last instruction is a return instruction, add an epilogue
224f4a2713aSLionel Sambuc if (!I->empty() && I->back().isReturn()) {
225f4a2713aSLionel Sambuc bool FoundIt = false;
226f4a2713aSLionel Sambuc for (MBBI = I->end(); MBBI != I->begin(); ) {
227f4a2713aSLionel Sambuc --MBBI;
228f4a2713aSLionel Sambuc if (MBBI->getOpcode() == PPC::MTVRSAVE) {
229f4a2713aSLionel Sambuc MBBI->eraseFromParent(); // remove it.
230f4a2713aSLionel Sambuc FoundIt = true;
231f4a2713aSLionel Sambuc break;
232f4a2713aSLionel Sambuc }
233f4a2713aSLionel Sambuc }
234f4a2713aSLionel Sambuc RemovedAllMTVRSAVEs &= FoundIt;
235f4a2713aSLionel Sambuc }
236f4a2713aSLionel Sambuc }
237f4a2713aSLionel Sambuc
238f4a2713aSLionel Sambuc // If we found and removed all MTVRSAVE instructions, remove the read of
239f4a2713aSLionel Sambuc // VRSAVE as well.
240f4a2713aSLionel Sambuc if (RemovedAllMTVRSAVEs) {
241f4a2713aSLionel Sambuc MBBI = MI;
242f4a2713aSLionel Sambuc assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
243f4a2713aSLionel Sambuc --MBBI;
244f4a2713aSLionel Sambuc assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
245f4a2713aSLionel Sambuc MBBI->eraseFromParent();
246f4a2713aSLionel Sambuc }
247f4a2713aSLionel Sambuc
248f4a2713aSLionel Sambuc // Finally, nuke the UPDATE_VRSAVE.
249f4a2713aSLionel Sambuc MI->eraseFromParent();
250f4a2713aSLionel Sambuc }
251f4a2713aSLionel Sambuc
252f4a2713aSLionel Sambuc // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
253f4a2713aSLionel Sambuc // instruction selector. Based on the vector registers that have been used,
254f4a2713aSLionel Sambuc // transform this into the appropriate ORI instruction.
HandleVRSaveUpdate(MachineInstr * MI,const TargetInstrInfo & TII)255f4a2713aSLionel Sambuc static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
256f4a2713aSLionel Sambuc MachineFunction *MF = MI->getParent()->getParent();
257*0a6a1f1dSLionel Sambuc const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
258f4a2713aSLionel Sambuc DebugLoc dl = MI->getDebugLoc();
259f4a2713aSLionel Sambuc
260f4a2713aSLionel Sambuc unsigned UsedRegMask = 0;
261f4a2713aSLionel Sambuc for (unsigned i = 0; i != 32; ++i)
262f4a2713aSLionel Sambuc if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
263f4a2713aSLionel Sambuc UsedRegMask |= 1 << (31-i);
264f4a2713aSLionel Sambuc
265f4a2713aSLionel Sambuc // Live in and live out values already must be in the mask, so don't bother
266f4a2713aSLionel Sambuc // marking them.
267f4a2713aSLionel Sambuc for (MachineRegisterInfo::livein_iterator
268f4a2713aSLionel Sambuc I = MF->getRegInfo().livein_begin(),
269f4a2713aSLionel Sambuc E = MF->getRegInfo().livein_end(); I != E; ++I) {
270f4a2713aSLionel Sambuc unsigned RegNo = TRI->getEncodingValue(I->first);
271f4a2713aSLionel Sambuc if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272f4a2713aSLionel Sambuc UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
273f4a2713aSLionel Sambuc }
274f4a2713aSLionel Sambuc
275f4a2713aSLionel Sambuc // Live out registers appear as use operands on return instructions.
276f4a2713aSLionel Sambuc for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
277f4a2713aSLionel Sambuc UsedRegMask != 0 && BI != BE; ++BI) {
278f4a2713aSLionel Sambuc const MachineBasicBlock &MBB = *BI;
279f4a2713aSLionel Sambuc if (MBB.empty() || !MBB.back().isReturn())
280f4a2713aSLionel Sambuc continue;
281f4a2713aSLionel Sambuc const MachineInstr &Ret = MBB.back();
282f4a2713aSLionel Sambuc for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
283f4a2713aSLionel Sambuc const MachineOperand &MO = Ret.getOperand(I);
284f4a2713aSLionel Sambuc if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
285f4a2713aSLionel Sambuc continue;
286f4a2713aSLionel Sambuc unsigned RegNo = TRI->getEncodingValue(MO.getReg());
287f4a2713aSLionel Sambuc UsedRegMask &= ~(1 << (31-RegNo));
288f4a2713aSLionel Sambuc }
289f4a2713aSLionel Sambuc }
290f4a2713aSLionel Sambuc
291f4a2713aSLionel Sambuc // If no registers are used, turn this into a copy.
292f4a2713aSLionel Sambuc if (UsedRegMask == 0) {
293f4a2713aSLionel Sambuc // Remove all VRSAVE code.
294f4a2713aSLionel Sambuc RemoveVRSaveCode(MI);
295f4a2713aSLionel Sambuc return;
296f4a2713aSLionel Sambuc }
297f4a2713aSLionel Sambuc
298f4a2713aSLionel Sambuc unsigned SrcReg = MI->getOperand(1).getReg();
299f4a2713aSLionel Sambuc unsigned DstReg = MI->getOperand(0).getReg();
300f4a2713aSLionel Sambuc
301f4a2713aSLionel Sambuc if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
302f4a2713aSLionel Sambuc if (DstReg != SrcReg)
303f4a2713aSLionel Sambuc BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
304f4a2713aSLionel Sambuc .addReg(SrcReg)
305f4a2713aSLionel Sambuc .addImm(UsedRegMask);
306f4a2713aSLionel Sambuc else
307f4a2713aSLionel Sambuc BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
308f4a2713aSLionel Sambuc .addReg(SrcReg, RegState::Kill)
309f4a2713aSLionel Sambuc .addImm(UsedRegMask);
310f4a2713aSLionel Sambuc } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
311f4a2713aSLionel Sambuc if (DstReg != SrcReg)
312f4a2713aSLionel Sambuc BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
313f4a2713aSLionel Sambuc .addReg(SrcReg)
314f4a2713aSLionel Sambuc .addImm(UsedRegMask >> 16);
315f4a2713aSLionel Sambuc else
316f4a2713aSLionel Sambuc BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
317f4a2713aSLionel Sambuc .addReg(SrcReg, RegState::Kill)
318f4a2713aSLionel Sambuc .addImm(UsedRegMask >> 16);
319f4a2713aSLionel Sambuc } else {
320f4a2713aSLionel Sambuc if (DstReg != SrcReg)
321f4a2713aSLionel Sambuc BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
322f4a2713aSLionel Sambuc .addReg(SrcReg)
323f4a2713aSLionel Sambuc .addImm(UsedRegMask >> 16);
324f4a2713aSLionel Sambuc else
325f4a2713aSLionel Sambuc BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
326f4a2713aSLionel Sambuc .addReg(SrcReg, RegState::Kill)
327f4a2713aSLionel Sambuc .addImm(UsedRegMask >> 16);
328f4a2713aSLionel Sambuc
329f4a2713aSLionel Sambuc BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
330f4a2713aSLionel Sambuc .addReg(DstReg, RegState::Kill)
331f4a2713aSLionel Sambuc .addImm(UsedRegMask & 0xFFFF);
332f4a2713aSLionel Sambuc }
333f4a2713aSLionel Sambuc
334f4a2713aSLionel Sambuc // Remove the old UPDATE_VRSAVE instruction.
335f4a2713aSLionel Sambuc MI->eraseFromParent();
336f4a2713aSLionel Sambuc }
337f4a2713aSLionel Sambuc
spillsCR(const MachineFunction & MF)338f4a2713aSLionel Sambuc static bool spillsCR(const MachineFunction &MF) {
339f4a2713aSLionel Sambuc const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340f4a2713aSLionel Sambuc return FuncInfo->isCRSpilled();
341f4a2713aSLionel Sambuc }
342f4a2713aSLionel Sambuc
spillsVRSAVE(const MachineFunction & MF)343f4a2713aSLionel Sambuc static bool spillsVRSAVE(const MachineFunction &MF) {
344f4a2713aSLionel Sambuc const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
345f4a2713aSLionel Sambuc return FuncInfo->isVRSAVESpilled();
346f4a2713aSLionel Sambuc }
347f4a2713aSLionel Sambuc
hasSpills(const MachineFunction & MF)348f4a2713aSLionel Sambuc static bool hasSpills(const MachineFunction &MF) {
349f4a2713aSLionel Sambuc const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350f4a2713aSLionel Sambuc return FuncInfo->hasSpills();
351f4a2713aSLionel Sambuc }
352f4a2713aSLionel Sambuc
hasNonRISpills(const MachineFunction & MF)353f4a2713aSLionel Sambuc static bool hasNonRISpills(const MachineFunction &MF) {
354f4a2713aSLionel Sambuc const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
355f4a2713aSLionel Sambuc return FuncInfo->hasNonRISpills();
356f4a2713aSLionel Sambuc }
357f4a2713aSLionel Sambuc
358f4a2713aSLionel Sambuc /// determineFrameLayout - Determine the size of the frame and maximum call
359f4a2713aSLionel Sambuc /// frame size.
determineFrameLayout(MachineFunction & MF,bool UpdateMF,bool UseEstimate) const360f4a2713aSLionel Sambuc unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
361f4a2713aSLionel Sambuc bool UpdateMF,
362f4a2713aSLionel Sambuc bool UseEstimate) const {
363f4a2713aSLionel Sambuc MachineFrameInfo *MFI = MF.getFrameInfo();
364f4a2713aSLionel Sambuc
365f4a2713aSLionel Sambuc // Get the number of bytes to allocate from the FrameInfo
366f4a2713aSLionel Sambuc unsigned FrameSize =
367f4a2713aSLionel Sambuc UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
368f4a2713aSLionel Sambuc
369f4a2713aSLionel Sambuc // Get stack alignments. The frame must be aligned to the greatest of these:
370f4a2713aSLionel Sambuc unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
371f4a2713aSLionel Sambuc unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
372f4a2713aSLionel Sambuc unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
373f4a2713aSLionel Sambuc
374f4a2713aSLionel Sambuc const PPCRegisterInfo *RegInfo =
375*0a6a1f1dSLionel Sambuc static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
376f4a2713aSLionel Sambuc
377f4a2713aSLionel Sambuc // If we are a leaf function, and use up to 224 bytes of stack space,
378f4a2713aSLionel Sambuc // don't have a frame pointer, calls, or dynamic alloca then we do not need
379f4a2713aSLionel Sambuc // to adjust the stack pointer (we fit in the Red Zone).
380f4a2713aSLionel Sambuc // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
381f4a2713aSLionel Sambuc // stackless code if all local vars are reg-allocated.
382f4a2713aSLionel Sambuc bool DisableRedZone = MF.getFunction()->getAttributes().
383f4a2713aSLionel Sambuc hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
384f4a2713aSLionel Sambuc if (!DisableRedZone &&
385f4a2713aSLionel Sambuc (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
386f4a2713aSLionel Sambuc !Subtarget.isSVR4ABI() || // allocated locals.
387f4a2713aSLionel Sambuc FrameSize == 0) &&
388f4a2713aSLionel Sambuc FrameSize <= 224 && // Fits in red zone.
389f4a2713aSLionel Sambuc !MFI->hasVarSizedObjects() && // No dynamic alloca.
390f4a2713aSLionel Sambuc !MFI->adjustsStack() && // No calls.
391f4a2713aSLionel Sambuc !RegInfo->hasBasePointer(MF)) { // No special alignment.
392f4a2713aSLionel Sambuc // No need for frame
393f4a2713aSLionel Sambuc if (UpdateMF)
394f4a2713aSLionel Sambuc MFI->setStackSize(0);
395f4a2713aSLionel Sambuc return 0;
396f4a2713aSLionel Sambuc }
397f4a2713aSLionel Sambuc
398f4a2713aSLionel Sambuc // Get the maximum call frame size of all the calls.
399f4a2713aSLionel Sambuc unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
400f4a2713aSLionel Sambuc
401*0a6a1f1dSLionel Sambuc // Maximum call frame needs to be at least big enough for linkage area.
402*0a6a1f1dSLionel Sambuc unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
403*0a6a1f1dSLionel Sambuc Subtarget.isDarwinABI(),
404*0a6a1f1dSLionel Sambuc Subtarget.isELFv2ABI());
405f4a2713aSLionel Sambuc maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
406f4a2713aSLionel Sambuc
407f4a2713aSLionel Sambuc // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
408f4a2713aSLionel Sambuc // that allocations will be aligned.
409f4a2713aSLionel Sambuc if (MFI->hasVarSizedObjects())
410f4a2713aSLionel Sambuc maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
411f4a2713aSLionel Sambuc
412f4a2713aSLionel Sambuc // Update maximum call frame size.
413f4a2713aSLionel Sambuc if (UpdateMF)
414f4a2713aSLionel Sambuc MFI->setMaxCallFrameSize(maxCallFrameSize);
415f4a2713aSLionel Sambuc
416f4a2713aSLionel Sambuc // Include call frame size in total.
417f4a2713aSLionel Sambuc FrameSize += maxCallFrameSize;
418f4a2713aSLionel Sambuc
419f4a2713aSLionel Sambuc // Make sure the frame is aligned.
420f4a2713aSLionel Sambuc FrameSize = (FrameSize + AlignMask) & ~AlignMask;
421f4a2713aSLionel Sambuc
422f4a2713aSLionel Sambuc // Update frame info.
423f4a2713aSLionel Sambuc if (UpdateMF)
424f4a2713aSLionel Sambuc MFI->setStackSize(FrameSize);
425f4a2713aSLionel Sambuc
426f4a2713aSLionel Sambuc return FrameSize;
427f4a2713aSLionel Sambuc }
428f4a2713aSLionel Sambuc
429f4a2713aSLionel Sambuc // hasFP - Return true if the specified function actually has a dedicated frame
430f4a2713aSLionel Sambuc // pointer register.
hasFP(const MachineFunction & MF) const431f4a2713aSLionel Sambuc bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
432f4a2713aSLionel Sambuc const MachineFrameInfo *MFI = MF.getFrameInfo();
433f4a2713aSLionel Sambuc // FIXME: This is pretty much broken by design: hasFP() might be called really
434f4a2713aSLionel Sambuc // early, before the stack layout was calculated and thus hasFP() might return
435f4a2713aSLionel Sambuc // true or false here depending on the time of call.
436f4a2713aSLionel Sambuc return (MFI->getStackSize()) && needsFP(MF);
437f4a2713aSLionel Sambuc }
438f4a2713aSLionel Sambuc
439f4a2713aSLionel Sambuc // needsFP - Return true if the specified function should have a dedicated frame
440f4a2713aSLionel Sambuc // pointer register. This is true if the function has variable sized allocas or
441f4a2713aSLionel Sambuc // if frame pointer elimination is disabled.
needsFP(const MachineFunction & MF) const442f4a2713aSLionel Sambuc bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
443f4a2713aSLionel Sambuc const MachineFrameInfo *MFI = MF.getFrameInfo();
444f4a2713aSLionel Sambuc
445f4a2713aSLionel Sambuc // Naked functions have no stack frame pushed, so we don't have a frame
446f4a2713aSLionel Sambuc // pointer.
447*0a6a1f1dSLionel Sambuc if (MF.getFunction()->getAttributes().hasAttribute(
448*0a6a1f1dSLionel Sambuc AttributeSet::FunctionIndex, Attribute::Naked))
449f4a2713aSLionel Sambuc return false;
450f4a2713aSLionel Sambuc
451f4a2713aSLionel Sambuc return MF.getTarget().Options.DisableFramePointerElim(MF) ||
452f4a2713aSLionel Sambuc MFI->hasVarSizedObjects() ||
453*0a6a1f1dSLionel Sambuc MFI->hasStackMap() || MFI->hasPatchPoint() ||
454f4a2713aSLionel Sambuc (MF.getTarget().Options.GuaranteedTailCallOpt &&
455f4a2713aSLionel Sambuc MF.getInfo<PPCFunctionInfo>()->hasFastCall());
456f4a2713aSLionel Sambuc }
457f4a2713aSLionel Sambuc
replaceFPWithRealFP(MachineFunction & MF) const458f4a2713aSLionel Sambuc void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
459f4a2713aSLionel Sambuc bool is31 = needsFP(MF);
460f4a2713aSLionel Sambuc unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
461f4a2713aSLionel Sambuc unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
462f4a2713aSLionel Sambuc
463f4a2713aSLionel Sambuc const PPCRegisterInfo *RegInfo =
464*0a6a1f1dSLionel Sambuc static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
465f4a2713aSLionel Sambuc bool HasBP = RegInfo->hasBasePointer(MF);
466*0a6a1f1dSLionel Sambuc unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
467f4a2713aSLionel Sambuc unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
468f4a2713aSLionel Sambuc
469f4a2713aSLionel Sambuc for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
470f4a2713aSLionel Sambuc BI != BE; ++BI)
471f4a2713aSLionel Sambuc for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
472f4a2713aSLionel Sambuc --MBBI;
473f4a2713aSLionel Sambuc for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
474f4a2713aSLionel Sambuc MachineOperand &MO = MBBI->getOperand(I);
475f4a2713aSLionel Sambuc if (!MO.isReg())
476f4a2713aSLionel Sambuc continue;
477f4a2713aSLionel Sambuc
478f4a2713aSLionel Sambuc switch (MO.getReg()) {
479f4a2713aSLionel Sambuc case PPC::FP:
480f4a2713aSLionel Sambuc MO.setReg(FPReg);
481f4a2713aSLionel Sambuc break;
482f4a2713aSLionel Sambuc case PPC::FP8:
483f4a2713aSLionel Sambuc MO.setReg(FP8Reg);
484f4a2713aSLionel Sambuc break;
485f4a2713aSLionel Sambuc case PPC::BP:
486f4a2713aSLionel Sambuc MO.setReg(BPReg);
487f4a2713aSLionel Sambuc break;
488f4a2713aSLionel Sambuc case PPC::BP8:
489f4a2713aSLionel Sambuc MO.setReg(BP8Reg);
490f4a2713aSLionel Sambuc break;
491f4a2713aSLionel Sambuc
492f4a2713aSLionel Sambuc }
493f4a2713aSLionel Sambuc }
494f4a2713aSLionel Sambuc }
495f4a2713aSLionel Sambuc }
496f4a2713aSLionel Sambuc
emitPrologue(MachineFunction & MF) const497f4a2713aSLionel Sambuc void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
498f4a2713aSLionel Sambuc MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
499f4a2713aSLionel Sambuc MachineBasicBlock::iterator MBBI = MBB.begin();
500f4a2713aSLionel Sambuc MachineFrameInfo *MFI = MF.getFrameInfo();
501f4a2713aSLionel Sambuc const PPCInstrInfo &TII =
502*0a6a1f1dSLionel Sambuc *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
503f4a2713aSLionel Sambuc const PPCRegisterInfo *RegInfo =
504*0a6a1f1dSLionel Sambuc static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
505f4a2713aSLionel Sambuc
506f4a2713aSLionel Sambuc MachineModuleInfo &MMI = MF.getMMI();
507f4a2713aSLionel Sambuc const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
508f4a2713aSLionel Sambuc DebugLoc dl;
509*0a6a1f1dSLionel Sambuc bool needsCFI = MMI.hasDebugInfo() ||
510f4a2713aSLionel Sambuc MF.getFunction()->needsUnwindTableEntry();
511*0a6a1f1dSLionel Sambuc bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
512f4a2713aSLionel Sambuc
513f4a2713aSLionel Sambuc // Get processor type.
514f4a2713aSLionel Sambuc bool isPPC64 = Subtarget.isPPC64();
515f4a2713aSLionel Sambuc // Get the ABI.
516f4a2713aSLionel Sambuc bool isDarwinABI = Subtarget.isDarwinABI();
517f4a2713aSLionel Sambuc bool isSVR4ABI = Subtarget.isSVR4ABI();
518*0a6a1f1dSLionel Sambuc bool isELFv2ABI = Subtarget.isELFv2ABI();
519f4a2713aSLionel Sambuc assert((isDarwinABI || isSVR4ABI) &&
520f4a2713aSLionel Sambuc "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
521f4a2713aSLionel Sambuc
522f4a2713aSLionel Sambuc // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
523f4a2713aSLionel Sambuc // process it.
524f4a2713aSLionel Sambuc if (!isSVR4ABI)
525f4a2713aSLionel Sambuc for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
526f4a2713aSLionel Sambuc if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
527f4a2713aSLionel Sambuc HandleVRSaveUpdate(MBBI, TII);
528f4a2713aSLionel Sambuc break;
529f4a2713aSLionel Sambuc }
530f4a2713aSLionel Sambuc }
531f4a2713aSLionel Sambuc
532f4a2713aSLionel Sambuc // Move MBBI back to the beginning of the function.
533f4a2713aSLionel Sambuc MBBI = MBB.begin();
534f4a2713aSLionel Sambuc
535f4a2713aSLionel Sambuc // Work out frame sizes.
536f4a2713aSLionel Sambuc unsigned FrameSize = determineFrameLayout(MF);
537f4a2713aSLionel Sambuc int NegFrameSize = -FrameSize;
538f4a2713aSLionel Sambuc if (!isInt<32>(NegFrameSize))
539f4a2713aSLionel Sambuc llvm_unreachable("Unhandled stack size!");
540f4a2713aSLionel Sambuc
541f4a2713aSLionel Sambuc if (MFI->isFrameAddressTaken())
542f4a2713aSLionel Sambuc replaceFPWithRealFP(MF);
543f4a2713aSLionel Sambuc
544f4a2713aSLionel Sambuc // Check if the link register (LR) must be saved.
545f4a2713aSLionel Sambuc PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
546f4a2713aSLionel Sambuc bool MustSaveLR = FI->mustSaveLR();
547f4a2713aSLionel Sambuc const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
548f4a2713aSLionel Sambuc // Do we have a frame pointer and/or base pointer for this function?
549f4a2713aSLionel Sambuc bool HasFP = hasFP(MF);
550f4a2713aSLionel Sambuc bool HasBP = RegInfo->hasBasePointer(MF);
551f4a2713aSLionel Sambuc
552f4a2713aSLionel Sambuc unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
553*0a6a1f1dSLionel Sambuc unsigned BPReg = RegInfo->getBaseRegister(MF);
554f4a2713aSLionel Sambuc unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
555f4a2713aSLionel Sambuc unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
556f4a2713aSLionel Sambuc unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
557f4a2713aSLionel Sambuc unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
558f4a2713aSLionel Sambuc // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
559f4a2713aSLionel Sambuc const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
560f4a2713aSLionel Sambuc : PPC::MFLR );
561f4a2713aSLionel Sambuc const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
562f4a2713aSLionel Sambuc : PPC::STW );
563f4a2713aSLionel Sambuc const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
564f4a2713aSLionel Sambuc : PPC::STWU );
565f4a2713aSLionel Sambuc const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
566f4a2713aSLionel Sambuc : PPC::STWUX);
567f4a2713aSLionel Sambuc const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
568f4a2713aSLionel Sambuc : PPC::LIS );
569f4a2713aSLionel Sambuc const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
570f4a2713aSLionel Sambuc : PPC::ORI );
571f4a2713aSLionel Sambuc const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
572f4a2713aSLionel Sambuc : PPC::OR );
573f4a2713aSLionel Sambuc const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
574f4a2713aSLionel Sambuc : PPC::SUBFC);
575f4a2713aSLionel Sambuc const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
576f4a2713aSLionel Sambuc : PPC::SUBFIC);
577f4a2713aSLionel Sambuc
578f4a2713aSLionel Sambuc // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
579f4a2713aSLionel Sambuc // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
580f4a2713aSLionel Sambuc // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
581f4a2713aSLionel Sambuc // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
582f4a2713aSLionel Sambuc assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
583f4a2713aSLionel Sambuc "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
584f4a2713aSLionel Sambuc
585f4a2713aSLionel Sambuc int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
586f4a2713aSLionel Sambuc
587f4a2713aSLionel Sambuc int FPOffset = 0;
588f4a2713aSLionel Sambuc if (HasFP) {
589f4a2713aSLionel Sambuc if (isSVR4ABI) {
590f4a2713aSLionel Sambuc MachineFrameInfo *FFI = MF.getFrameInfo();
591f4a2713aSLionel Sambuc int FPIndex = FI->getFramePointerSaveIndex();
592f4a2713aSLionel Sambuc assert(FPIndex && "No Frame Pointer Save Slot!");
593f4a2713aSLionel Sambuc FPOffset = FFI->getObjectOffset(FPIndex);
594f4a2713aSLionel Sambuc } else {
595*0a6a1f1dSLionel Sambuc FPOffset =
596*0a6a1f1dSLionel Sambuc PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
597f4a2713aSLionel Sambuc }
598f4a2713aSLionel Sambuc }
599f4a2713aSLionel Sambuc
600f4a2713aSLionel Sambuc int BPOffset = 0;
601f4a2713aSLionel Sambuc if (HasBP) {
602f4a2713aSLionel Sambuc if (isSVR4ABI) {
603f4a2713aSLionel Sambuc MachineFrameInfo *FFI = MF.getFrameInfo();
604f4a2713aSLionel Sambuc int BPIndex = FI->getBasePointerSaveIndex();
605f4a2713aSLionel Sambuc assert(BPIndex && "No Base Pointer Save Slot!");
606f4a2713aSLionel Sambuc BPOffset = FFI->getObjectOffset(BPIndex);
607f4a2713aSLionel Sambuc } else {
608f4a2713aSLionel Sambuc BPOffset =
609*0a6a1f1dSLionel Sambuc PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
610*0a6a1f1dSLionel Sambuc isDarwinABI,
611*0a6a1f1dSLionel Sambuc isPIC);
612f4a2713aSLionel Sambuc }
613f4a2713aSLionel Sambuc }
614f4a2713aSLionel Sambuc
615*0a6a1f1dSLionel Sambuc int PBPOffset = 0;
616*0a6a1f1dSLionel Sambuc if (FI->usesPICBase()) {
617*0a6a1f1dSLionel Sambuc MachineFrameInfo *FFI = MF.getFrameInfo();
618*0a6a1f1dSLionel Sambuc int PBPIndex = FI->getPICBasePointerSaveIndex();
619*0a6a1f1dSLionel Sambuc assert(PBPIndex && "No PIC Base Pointer Save Slot!");
620*0a6a1f1dSLionel Sambuc PBPOffset = FFI->getObjectOffset(PBPIndex);
621*0a6a1f1dSLionel Sambuc }
622*0a6a1f1dSLionel Sambuc
623f4a2713aSLionel Sambuc // Get stack alignments.
624f4a2713aSLionel Sambuc unsigned MaxAlign = MFI->getMaxAlignment();
625f4a2713aSLionel Sambuc if (HasBP && MaxAlign > 1)
626f4a2713aSLionel Sambuc assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
627f4a2713aSLionel Sambuc "Invalid alignment!");
628f4a2713aSLionel Sambuc
629f4a2713aSLionel Sambuc // Frames of 32KB & larger require special handling because they cannot be
630f4a2713aSLionel Sambuc // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
631f4a2713aSLionel Sambuc bool isLargeFrame = !isInt<16>(NegFrameSize);
632f4a2713aSLionel Sambuc
633f4a2713aSLionel Sambuc if (MustSaveLR)
634f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
635f4a2713aSLionel Sambuc
636f4a2713aSLionel Sambuc assert((isPPC64 || MustSaveCRs.empty()) &&
637f4a2713aSLionel Sambuc "Prologue CR saving supported only in 64-bit mode");
638f4a2713aSLionel Sambuc
639f4a2713aSLionel Sambuc if (!MustSaveCRs.empty()) { // will only occur for PPC64
640*0a6a1f1dSLionel Sambuc // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
641*0a6a1f1dSLionel Sambuc // If only one or two CR fields are clobbered, it could be more
642*0a6a1f1dSLionel Sambuc // efficient to use mfocrf to selectively save just those fields.
643f4a2713aSLionel Sambuc MachineInstrBuilder MIB =
644f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
645f4a2713aSLionel Sambuc for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
646f4a2713aSLionel Sambuc MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
647f4a2713aSLionel Sambuc }
648f4a2713aSLionel Sambuc
649f4a2713aSLionel Sambuc if (HasFP)
650f4a2713aSLionel Sambuc // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
651f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, StoreInst)
652f4a2713aSLionel Sambuc .addReg(FPReg)
653f4a2713aSLionel Sambuc .addImm(FPOffset)
654f4a2713aSLionel Sambuc .addReg(SPReg);
655f4a2713aSLionel Sambuc
656*0a6a1f1dSLionel Sambuc if (FI->usesPICBase())
657*0a6a1f1dSLionel Sambuc // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
658*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, StoreInst)
659*0a6a1f1dSLionel Sambuc .addReg(PPC::R30)
660*0a6a1f1dSLionel Sambuc .addImm(PBPOffset)
661*0a6a1f1dSLionel Sambuc .addReg(SPReg);
662*0a6a1f1dSLionel Sambuc
663f4a2713aSLionel Sambuc if (HasBP)
664f4a2713aSLionel Sambuc // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
665f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, StoreInst)
666f4a2713aSLionel Sambuc .addReg(BPReg)
667f4a2713aSLionel Sambuc .addImm(BPOffset)
668f4a2713aSLionel Sambuc .addReg(SPReg);
669f4a2713aSLionel Sambuc
670f4a2713aSLionel Sambuc if (MustSaveLR)
671f4a2713aSLionel Sambuc // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
672f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, StoreInst)
673f4a2713aSLionel Sambuc .addReg(ScratchReg)
674f4a2713aSLionel Sambuc .addImm(LROffset)
675f4a2713aSLionel Sambuc .addReg(SPReg);
676f4a2713aSLionel Sambuc
677f4a2713aSLionel Sambuc if (!MustSaveCRs.empty()) // will only occur for PPC64
678f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
679f4a2713aSLionel Sambuc .addReg(TempReg, getKillRegState(true))
680f4a2713aSLionel Sambuc .addImm(8)
681f4a2713aSLionel Sambuc .addReg(SPReg);
682f4a2713aSLionel Sambuc
683f4a2713aSLionel Sambuc // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
684f4a2713aSLionel Sambuc if (!FrameSize) return;
685f4a2713aSLionel Sambuc
686f4a2713aSLionel Sambuc // Adjust stack pointer: r1 += NegFrameSize.
687f4a2713aSLionel Sambuc // If there is a preferred stack alignment, align R1 now
688f4a2713aSLionel Sambuc
689f4a2713aSLionel Sambuc if (HasBP) {
690f4a2713aSLionel Sambuc // Save a copy of r1 as the base pointer.
691f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, OrInst, BPReg)
692f4a2713aSLionel Sambuc .addReg(SPReg)
693f4a2713aSLionel Sambuc .addReg(SPReg);
694f4a2713aSLionel Sambuc }
695f4a2713aSLionel Sambuc
696f4a2713aSLionel Sambuc if (HasBP && MaxAlign > 1) {
697f4a2713aSLionel Sambuc if (isPPC64)
698f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
699f4a2713aSLionel Sambuc .addReg(SPReg)
700f4a2713aSLionel Sambuc .addImm(0)
701f4a2713aSLionel Sambuc .addImm(64 - Log2_32(MaxAlign));
702f4a2713aSLionel Sambuc else // PPC32...
703f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
704f4a2713aSLionel Sambuc .addReg(SPReg)
705f4a2713aSLionel Sambuc .addImm(0)
706f4a2713aSLionel Sambuc .addImm(32 - Log2_32(MaxAlign))
707f4a2713aSLionel Sambuc .addImm(31);
708f4a2713aSLionel Sambuc if (!isLargeFrame) {
709f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
710f4a2713aSLionel Sambuc .addReg(ScratchReg, RegState::Kill)
711f4a2713aSLionel Sambuc .addImm(NegFrameSize);
712f4a2713aSLionel Sambuc } else {
713f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
714f4a2713aSLionel Sambuc .addImm(NegFrameSize >> 16);
715f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
716f4a2713aSLionel Sambuc .addReg(TempReg, RegState::Kill)
717f4a2713aSLionel Sambuc .addImm(NegFrameSize & 0xFFFF);
718f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
719f4a2713aSLionel Sambuc .addReg(ScratchReg, RegState::Kill)
720f4a2713aSLionel Sambuc .addReg(TempReg, RegState::Kill);
721f4a2713aSLionel Sambuc }
722f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
723f4a2713aSLionel Sambuc .addReg(SPReg, RegState::Kill)
724f4a2713aSLionel Sambuc .addReg(SPReg)
725f4a2713aSLionel Sambuc .addReg(ScratchReg);
726f4a2713aSLionel Sambuc
727f4a2713aSLionel Sambuc } else if (!isLargeFrame) {
728f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
729f4a2713aSLionel Sambuc .addReg(SPReg)
730f4a2713aSLionel Sambuc .addImm(NegFrameSize)
731f4a2713aSLionel Sambuc .addReg(SPReg);
732f4a2713aSLionel Sambuc
733f4a2713aSLionel Sambuc } else {
734f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
735f4a2713aSLionel Sambuc .addImm(NegFrameSize >> 16);
736f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
737f4a2713aSLionel Sambuc .addReg(ScratchReg, RegState::Kill)
738f4a2713aSLionel Sambuc .addImm(NegFrameSize & 0xFFFF);
739f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
740f4a2713aSLionel Sambuc .addReg(SPReg, RegState::Kill)
741f4a2713aSLionel Sambuc .addReg(SPReg)
742f4a2713aSLionel Sambuc .addReg(ScratchReg);
743f4a2713aSLionel Sambuc }
744f4a2713aSLionel Sambuc
745*0a6a1f1dSLionel Sambuc // Add Call Frame Information for the instructions we generated above.
746*0a6a1f1dSLionel Sambuc if (needsCFI) {
747*0a6a1f1dSLionel Sambuc unsigned CFIIndex;
748f4a2713aSLionel Sambuc
749*0a6a1f1dSLionel Sambuc if (HasBP) {
750*0a6a1f1dSLionel Sambuc // Define CFA in terms of BP. Do this in preference to using FP/SP,
751*0a6a1f1dSLionel Sambuc // because if the stack needed aligning then CFA won't be at a fixed
752*0a6a1f1dSLionel Sambuc // offset from FP/SP.
753*0a6a1f1dSLionel Sambuc unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
754*0a6a1f1dSLionel Sambuc CFIIndex = MMI.addFrameInst(
755*0a6a1f1dSLionel Sambuc MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
756*0a6a1f1dSLionel Sambuc } else {
757*0a6a1f1dSLionel Sambuc // Adjust the definition of CFA to account for the change in SP.
758f4a2713aSLionel Sambuc assert(NegFrameSize);
759*0a6a1f1dSLionel Sambuc CFIIndex = MMI.addFrameInst(
760*0a6a1f1dSLionel Sambuc MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
761*0a6a1f1dSLionel Sambuc }
762*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
763*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
764f4a2713aSLionel Sambuc
765f4a2713aSLionel Sambuc if (HasFP) {
766*0a6a1f1dSLionel Sambuc // Describe where FP was saved, at a fixed offset from CFA.
767f4a2713aSLionel Sambuc unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
768*0a6a1f1dSLionel Sambuc CFIIndex = MMI.addFrameInst(
769*0a6a1f1dSLionel Sambuc MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
770*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
771*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
772*0a6a1f1dSLionel Sambuc }
773*0a6a1f1dSLionel Sambuc
774*0a6a1f1dSLionel Sambuc if (FI->usesPICBase()) {
775*0a6a1f1dSLionel Sambuc // Describe where FP was saved, at a fixed offset from CFA.
776*0a6a1f1dSLionel Sambuc unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
777*0a6a1f1dSLionel Sambuc CFIIndex = MMI.addFrameInst(
778*0a6a1f1dSLionel Sambuc MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
779*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
780*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
781f4a2713aSLionel Sambuc }
782f4a2713aSLionel Sambuc
783f4a2713aSLionel Sambuc if (HasBP) {
784*0a6a1f1dSLionel Sambuc // Describe where BP was saved, at a fixed offset from CFA.
785f4a2713aSLionel Sambuc unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
786*0a6a1f1dSLionel Sambuc CFIIndex = MMI.addFrameInst(
787*0a6a1f1dSLionel Sambuc MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
788*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
789*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
790f4a2713aSLionel Sambuc }
791f4a2713aSLionel Sambuc
792f4a2713aSLionel Sambuc if (MustSaveLR) {
793*0a6a1f1dSLionel Sambuc // Describe where LR was saved, at a fixed offset from CFA.
794f4a2713aSLionel Sambuc unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
795*0a6a1f1dSLionel Sambuc CFIIndex = MMI.addFrameInst(
796*0a6a1f1dSLionel Sambuc MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
797*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
798*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
799f4a2713aSLionel Sambuc }
800f4a2713aSLionel Sambuc }
801f4a2713aSLionel Sambuc
802f4a2713aSLionel Sambuc // If there is a frame pointer, copy R1 into R31
803f4a2713aSLionel Sambuc if (HasFP) {
804f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, OrInst, FPReg)
805f4a2713aSLionel Sambuc .addReg(SPReg)
806f4a2713aSLionel Sambuc .addReg(SPReg);
807f4a2713aSLionel Sambuc
808*0a6a1f1dSLionel Sambuc if (!HasBP && needsCFI) {
809*0a6a1f1dSLionel Sambuc // Change the definition of CFA from SP+offset to FP+offset, because SP
810*0a6a1f1dSLionel Sambuc // will change at every alloca.
811f4a2713aSLionel Sambuc unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
812*0a6a1f1dSLionel Sambuc unsigned CFIIndex = MMI.addFrameInst(
813*0a6a1f1dSLionel Sambuc MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
814*0a6a1f1dSLionel Sambuc
815*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
816*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
817f4a2713aSLionel Sambuc }
818f4a2713aSLionel Sambuc }
819f4a2713aSLionel Sambuc
820*0a6a1f1dSLionel Sambuc if (needsCFI) {
821*0a6a1f1dSLionel Sambuc // Describe where callee saved registers were saved, at fixed offsets from
822*0a6a1f1dSLionel Sambuc // CFA.
823f4a2713aSLionel Sambuc const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
824f4a2713aSLionel Sambuc for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
825f4a2713aSLionel Sambuc unsigned Reg = CSI[I].getReg();
826f4a2713aSLionel Sambuc if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
827f4a2713aSLionel Sambuc
828f4a2713aSLionel Sambuc // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
829f4a2713aSLionel Sambuc // subregisters of CR2. We just need to emit a move of CR2.
830f4a2713aSLionel Sambuc if (PPC::CRBITRCRegClass.contains(Reg))
831f4a2713aSLionel Sambuc continue;
832f4a2713aSLionel Sambuc
833f4a2713aSLionel Sambuc // For SVR4, don't emit a move for the CR spill slot if we haven't
834f4a2713aSLionel Sambuc // spilled CRs.
835f4a2713aSLionel Sambuc if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
836f4a2713aSLionel Sambuc && MustSaveCRs.empty())
837f4a2713aSLionel Sambuc continue;
838f4a2713aSLionel Sambuc
839f4a2713aSLionel Sambuc // For 64-bit SVR4 when we have spilled CRs, the spill location
840f4a2713aSLionel Sambuc // is SP+8, not a frame-relative slot.
841f4a2713aSLionel Sambuc if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
842*0a6a1f1dSLionel Sambuc // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
843*0a6a1f1dSLionel Sambuc // the whole CR word. In the ELFv2 ABI, every CR that was
844*0a6a1f1dSLionel Sambuc // actually saved gets its own CFI record.
845*0a6a1f1dSLionel Sambuc unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
846*0a6a1f1dSLionel Sambuc unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
847*0a6a1f1dSLionel Sambuc nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
848*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
849*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
850f4a2713aSLionel Sambuc continue;
851f4a2713aSLionel Sambuc }
852f4a2713aSLionel Sambuc
853f4a2713aSLionel Sambuc int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
854*0a6a1f1dSLionel Sambuc unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
855*0a6a1f1dSLionel Sambuc nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
856*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
857*0a6a1f1dSLionel Sambuc .addCFIIndex(CFIIndex);
858f4a2713aSLionel Sambuc }
859f4a2713aSLionel Sambuc }
860f4a2713aSLionel Sambuc }
861f4a2713aSLionel Sambuc
emitEpilogue(MachineFunction & MF,MachineBasicBlock & MBB) const862f4a2713aSLionel Sambuc void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
863f4a2713aSLionel Sambuc MachineBasicBlock &MBB) const {
864f4a2713aSLionel Sambuc MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
865f4a2713aSLionel Sambuc assert(MBBI != MBB.end() && "Returning block has no terminator");
866f4a2713aSLionel Sambuc const PPCInstrInfo &TII =
867*0a6a1f1dSLionel Sambuc *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
868f4a2713aSLionel Sambuc const PPCRegisterInfo *RegInfo =
869*0a6a1f1dSLionel Sambuc static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
870f4a2713aSLionel Sambuc
871f4a2713aSLionel Sambuc unsigned RetOpcode = MBBI->getOpcode();
872f4a2713aSLionel Sambuc DebugLoc dl;
873f4a2713aSLionel Sambuc
874f4a2713aSLionel Sambuc assert((RetOpcode == PPC::BLR ||
875*0a6a1f1dSLionel Sambuc RetOpcode == PPC::BLR8 ||
876f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNri ||
877f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNdi ||
878f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNai ||
879f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNri8 ||
880f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNdi8 ||
881f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNai8) &&
882f4a2713aSLionel Sambuc "Can only insert epilog into returning blocks");
883f4a2713aSLionel Sambuc
884f4a2713aSLionel Sambuc // Get alignment info so we know how to restore the SP.
885f4a2713aSLionel Sambuc const MachineFrameInfo *MFI = MF.getFrameInfo();
886f4a2713aSLionel Sambuc
887f4a2713aSLionel Sambuc // Get the number of bytes allocated from the FrameInfo.
888f4a2713aSLionel Sambuc int FrameSize = MFI->getStackSize();
889f4a2713aSLionel Sambuc
890f4a2713aSLionel Sambuc // Get processor type.
891f4a2713aSLionel Sambuc bool isPPC64 = Subtarget.isPPC64();
892f4a2713aSLionel Sambuc // Get the ABI.
893f4a2713aSLionel Sambuc bool isDarwinABI = Subtarget.isDarwinABI();
894f4a2713aSLionel Sambuc bool isSVR4ABI = Subtarget.isSVR4ABI();
895*0a6a1f1dSLionel Sambuc bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
896f4a2713aSLionel Sambuc
897f4a2713aSLionel Sambuc // Check if the link register (LR) has been saved.
898f4a2713aSLionel Sambuc PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
899f4a2713aSLionel Sambuc bool MustSaveLR = FI->mustSaveLR();
900f4a2713aSLionel Sambuc const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
901f4a2713aSLionel Sambuc // Do we have a frame pointer and/or base pointer for this function?
902f4a2713aSLionel Sambuc bool HasFP = hasFP(MF);
903f4a2713aSLionel Sambuc bool HasBP = RegInfo->hasBasePointer(MF);
904f4a2713aSLionel Sambuc
905f4a2713aSLionel Sambuc unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
906*0a6a1f1dSLionel Sambuc unsigned BPReg = RegInfo->getBaseRegister(MF);
907f4a2713aSLionel Sambuc unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
908f4a2713aSLionel Sambuc unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
909f4a2713aSLionel Sambuc unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
910f4a2713aSLionel Sambuc const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
911f4a2713aSLionel Sambuc : PPC::MTLR );
912f4a2713aSLionel Sambuc const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
913f4a2713aSLionel Sambuc : PPC::LWZ );
914f4a2713aSLionel Sambuc const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
915f4a2713aSLionel Sambuc : PPC::LIS );
916f4a2713aSLionel Sambuc const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
917f4a2713aSLionel Sambuc : PPC::ORI );
918f4a2713aSLionel Sambuc const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
919f4a2713aSLionel Sambuc : PPC::ADDI );
920f4a2713aSLionel Sambuc const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
921f4a2713aSLionel Sambuc : PPC::ADD4 );
922f4a2713aSLionel Sambuc
923f4a2713aSLionel Sambuc int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
924f4a2713aSLionel Sambuc
925f4a2713aSLionel Sambuc int FPOffset = 0;
926f4a2713aSLionel Sambuc if (HasFP) {
927f4a2713aSLionel Sambuc if (isSVR4ABI) {
928f4a2713aSLionel Sambuc MachineFrameInfo *FFI = MF.getFrameInfo();
929f4a2713aSLionel Sambuc int FPIndex = FI->getFramePointerSaveIndex();
930f4a2713aSLionel Sambuc assert(FPIndex && "No Frame Pointer Save Slot!");
931f4a2713aSLionel Sambuc FPOffset = FFI->getObjectOffset(FPIndex);
932f4a2713aSLionel Sambuc } else {
933*0a6a1f1dSLionel Sambuc FPOffset =
934*0a6a1f1dSLionel Sambuc PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
935f4a2713aSLionel Sambuc }
936f4a2713aSLionel Sambuc }
937f4a2713aSLionel Sambuc
938f4a2713aSLionel Sambuc int BPOffset = 0;
939f4a2713aSLionel Sambuc if (HasBP) {
940f4a2713aSLionel Sambuc if (isSVR4ABI) {
941f4a2713aSLionel Sambuc MachineFrameInfo *FFI = MF.getFrameInfo();
942f4a2713aSLionel Sambuc int BPIndex = FI->getBasePointerSaveIndex();
943f4a2713aSLionel Sambuc assert(BPIndex && "No Base Pointer Save Slot!");
944f4a2713aSLionel Sambuc BPOffset = FFI->getObjectOffset(BPIndex);
945f4a2713aSLionel Sambuc } else {
946f4a2713aSLionel Sambuc BPOffset =
947*0a6a1f1dSLionel Sambuc PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
948*0a6a1f1dSLionel Sambuc isDarwinABI,
949*0a6a1f1dSLionel Sambuc isPIC);
950f4a2713aSLionel Sambuc }
951f4a2713aSLionel Sambuc }
952f4a2713aSLionel Sambuc
953*0a6a1f1dSLionel Sambuc int PBPOffset = 0;
954*0a6a1f1dSLionel Sambuc if (FI->usesPICBase()) {
955*0a6a1f1dSLionel Sambuc MachineFrameInfo *FFI = MF.getFrameInfo();
956*0a6a1f1dSLionel Sambuc int PBPIndex = FI->getPICBasePointerSaveIndex();
957*0a6a1f1dSLionel Sambuc assert(PBPIndex && "No PIC Base Pointer Save Slot!");
958*0a6a1f1dSLionel Sambuc PBPOffset = FFI->getObjectOffset(PBPIndex);
959*0a6a1f1dSLionel Sambuc }
960*0a6a1f1dSLionel Sambuc
961f4a2713aSLionel Sambuc bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
962f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNdi ||
963f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNai ||
964f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNri8 ||
965f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNdi8 ||
966f4a2713aSLionel Sambuc RetOpcode == PPC::TCRETURNai8;
967f4a2713aSLionel Sambuc
968f4a2713aSLionel Sambuc if (UsesTCRet) {
969f4a2713aSLionel Sambuc int MaxTCRetDelta = FI->getTailCallSPDelta();
970f4a2713aSLionel Sambuc MachineOperand &StackAdjust = MBBI->getOperand(1);
971f4a2713aSLionel Sambuc assert(StackAdjust.isImm() && "Expecting immediate value.");
972f4a2713aSLionel Sambuc // Adjust stack pointer.
973f4a2713aSLionel Sambuc int StackAdj = StackAdjust.getImm();
974f4a2713aSLionel Sambuc int Delta = StackAdj - MaxTCRetDelta;
975f4a2713aSLionel Sambuc assert((Delta >= 0) && "Delta must be positive");
976f4a2713aSLionel Sambuc if (MaxTCRetDelta>0)
977f4a2713aSLionel Sambuc FrameSize += (StackAdj +Delta);
978f4a2713aSLionel Sambuc else
979f4a2713aSLionel Sambuc FrameSize += StackAdj;
980f4a2713aSLionel Sambuc }
981f4a2713aSLionel Sambuc
982f4a2713aSLionel Sambuc // Frames of 32KB & larger require special handling because they cannot be
983f4a2713aSLionel Sambuc // indexed into with a simple LD/LWZ immediate offset operand.
984f4a2713aSLionel Sambuc bool isLargeFrame = !isInt<16>(FrameSize);
985f4a2713aSLionel Sambuc
986f4a2713aSLionel Sambuc if (FrameSize) {
987f4a2713aSLionel Sambuc // In the prologue, the loaded (or persistent) stack pointer value is offset
988f4a2713aSLionel Sambuc // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
989f4a2713aSLionel Sambuc
990f4a2713aSLionel Sambuc // If this function contained a fastcc call and GuaranteedTailCallOpt is
991f4a2713aSLionel Sambuc // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
992f4a2713aSLionel Sambuc // call which invalidates the stack pointer value in SP(0). So we use the
993f4a2713aSLionel Sambuc // value of R31 in this case.
994f4a2713aSLionel Sambuc if (FI->hasFastCall()) {
995f4a2713aSLionel Sambuc assert(HasFP && "Expecting a valid frame pointer.");
996f4a2713aSLionel Sambuc if (!isLargeFrame) {
997f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
998f4a2713aSLionel Sambuc .addReg(FPReg).addImm(FrameSize);
999f4a2713aSLionel Sambuc } else {
1000f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1001f4a2713aSLionel Sambuc .addImm(FrameSize >> 16);
1002f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1003f4a2713aSLionel Sambuc .addReg(ScratchReg, RegState::Kill)
1004f4a2713aSLionel Sambuc .addImm(FrameSize & 0xFFFF);
1005f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, AddInst)
1006f4a2713aSLionel Sambuc .addReg(SPReg)
1007f4a2713aSLionel Sambuc .addReg(FPReg)
1008f4a2713aSLionel Sambuc .addReg(ScratchReg);
1009f4a2713aSLionel Sambuc }
1010f4a2713aSLionel Sambuc } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1011f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1012f4a2713aSLionel Sambuc .addReg(SPReg)
1013f4a2713aSLionel Sambuc .addImm(FrameSize);
1014f4a2713aSLionel Sambuc } else {
1015f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1016f4a2713aSLionel Sambuc .addImm(0)
1017f4a2713aSLionel Sambuc .addReg(SPReg);
1018f4a2713aSLionel Sambuc }
1019f4a2713aSLionel Sambuc
1020f4a2713aSLionel Sambuc }
1021f4a2713aSLionel Sambuc
1022f4a2713aSLionel Sambuc if (MustSaveLR)
1023f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1024f4a2713aSLionel Sambuc .addImm(LROffset)
1025f4a2713aSLionel Sambuc .addReg(SPReg);
1026f4a2713aSLionel Sambuc
1027f4a2713aSLionel Sambuc assert((isPPC64 || MustSaveCRs.empty()) &&
1028f4a2713aSLionel Sambuc "Epilogue CR restoring supported only in 64-bit mode");
1029f4a2713aSLionel Sambuc
1030f4a2713aSLionel Sambuc if (!MustSaveCRs.empty()) // will only occur for PPC64
1031f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1032f4a2713aSLionel Sambuc .addImm(8)
1033f4a2713aSLionel Sambuc .addReg(SPReg);
1034f4a2713aSLionel Sambuc
1035f4a2713aSLionel Sambuc if (HasFP)
1036f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1037f4a2713aSLionel Sambuc .addImm(FPOffset)
1038f4a2713aSLionel Sambuc .addReg(SPReg);
1039f4a2713aSLionel Sambuc
1040*0a6a1f1dSLionel Sambuc if (FI->usesPICBase())
1041*0a6a1f1dSLionel Sambuc // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1042*0a6a1f1dSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadInst)
1043*0a6a1f1dSLionel Sambuc .addReg(PPC::R30)
1044*0a6a1f1dSLionel Sambuc .addImm(PBPOffset)
1045*0a6a1f1dSLionel Sambuc .addReg(SPReg);
1046*0a6a1f1dSLionel Sambuc
1047f4a2713aSLionel Sambuc if (HasBP)
1048f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1049f4a2713aSLionel Sambuc .addImm(BPOffset)
1050f4a2713aSLionel Sambuc .addReg(SPReg);
1051f4a2713aSLionel Sambuc
1052f4a2713aSLionel Sambuc if (!MustSaveCRs.empty()) // will only occur for PPC64
1053f4a2713aSLionel Sambuc for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1054f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1055f4a2713aSLionel Sambuc .addReg(TempReg, getKillRegState(i == e-1));
1056f4a2713aSLionel Sambuc
1057f4a2713aSLionel Sambuc if (MustSaveLR)
1058f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1059f4a2713aSLionel Sambuc
1060f4a2713aSLionel Sambuc // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1061f4a2713aSLionel Sambuc // call optimization
1062*0a6a1f1dSLionel Sambuc if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1063*0a6a1f1dSLionel Sambuc (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1064f4a2713aSLionel Sambuc MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1065f4a2713aSLionel Sambuc PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1066f4a2713aSLionel Sambuc unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1067f4a2713aSLionel Sambuc
1068f4a2713aSLionel Sambuc if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1069f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1070f4a2713aSLionel Sambuc .addReg(SPReg).addImm(CallerAllocatedAmt);
1071f4a2713aSLionel Sambuc } else {
1072f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1073f4a2713aSLionel Sambuc .addImm(CallerAllocatedAmt >> 16);
1074f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1075f4a2713aSLionel Sambuc .addReg(ScratchReg, RegState::Kill)
1076f4a2713aSLionel Sambuc .addImm(CallerAllocatedAmt & 0xFFFF);
1077f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, AddInst)
1078f4a2713aSLionel Sambuc .addReg(SPReg)
1079f4a2713aSLionel Sambuc .addReg(FPReg)
1080f4a2713aSLionel Sambuc .addReg(ScratchReg);
1081f4a2713aSLionel Sambuc }
1082f4a2713aSLionel Sambuc } else if (RetOpcode == PPC::TCRETURNdi) {
1083f4a2713aSLionel Sambuc MBBI = MBB.getLastNonDebugInstr();
1084f4a2713aSLionel Sambuc MachineOperand &JumpTarget = MBBI->getOperand(0);
1085f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1086f4a2713aSLionel Sambuc addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1087f4a2713aSLionel Sambuc } else if (RetOpcode == PPC::TCRETURNri) {
1088f4a2713aSLionel Sambuc MBBI = MBB.getLastNonDebugInstr();
1089f4a2713aSLionel Sambuc assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1090f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1091f4a2713aSLionel Sambuc } else if (RetOpcode == PPC::TCRETURNai) {
1092f4a2713aSLionel Sambuc MBBI = MBB.getLastNonDebugInstr();
1093f4a2713aSLionel Sambuc MachineOperand &JumpTarget = MBBI->getOperand(0);
1094f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1095f4a2713aSLionel Sambuc } else if (RetOpcode == PPC::TCRETURNdi8) {
1096f4a2713aSLionel Sambuc MBBI = MBB.getLastNonDebugInstr();
1097f4a2713aSLionel Sambuc MachineOperand &JumpTarget = MBBI->getOperand(0);
1098f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1099f4a2713aSLionel Sambuc addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1100f4a2713aSLionel Sambuc } else if (RetOpcode == PPC::TCRETURNri8) {
1101f4a2713aSLionel Sambuc MBBI = MBB.getLastNonDebugInstr();
1102f4a2713aSLionel Sambuc assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1103f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1104f4a2713aSLionel Sambuc } else if (RetOpcode == PPC::TCRETURNai8) {
1105f4a2713aSLionel Sambuc MBBI = MBB.getLastNonDebugInstr();
1106f4a2713aSLionel Sambuc MachineOperand &JumpTarget = MBBI->getOperand(0);
1107f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1108f4a2713aSLionel Sambuc }
1109f4a2713aSLionel Sambuc }
1110f4a2713aSLionel Sambuc
1111f4a2713aSLionel Sambuc /// MustSaveLR - Return true if this function requires that we save the LR
1112f4a2713aSLionel Sambuc /// register onto the stack in the prolog and restore it in the epilog of the
1113f4a2713aSLionel Sambuc /// function.
MustSaveLR(const MachineFunction & MF,unsigned LR)1114f4a2713aSLionel Sambuc static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
1115f4a2713aSLionel Sambuc const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
1116f4a2713aSLionel Sambuc
1117f4a2713aSLionel Sambuc // We need a save/restore of LR if there is any def of LR (which is
1118f4a2713aSLionel Sambuc // defined by calls, including the PIC setup sequence), or if there is
1119f4a2713aSLionel Sambuc // some use of the LR stack slot (e.g. for builtin_return_address).
1120f4a2713aSLionel Sambuc // (LR comes in 32 and 64 bit versions.)
1121f4a2713aSLionel Sambuc MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
1122f4a2713aSLionel Sambuc return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
1123f4a2713aSLionel Sambuc }
1124f4a2713aSLionel Sambuc
1125f4a2713aSLionel Sambuc void
processFunctionBeforeCalleeSavedScan(MachineFunction & MF,RegScavenger *) const1126f4a2713aSLionel Sambuc PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1127f4a2713aSLionel Sambuc RegScavenger *) const {
1128f4a2713aSLionel Sambuc const PPCRegisterInfo *RegInfo =
1129*0a6a1f1dSLionel Sambuc static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1130f4a2713aSLionel Sambuc
1131f4a2713aSLionel Sambuc // Save and clear the LR state.
1132f4a2713aSLionel Sambuc PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1133f4a2713aSLionel Sambuc unsigned LR = RegInfo->getRARegister();
1134f4a2713aSLionel Sambuc FI->setMustSaveLR(MustSaveLR(MF, LR));
1135f4a2713aSLionel Sambuc MachineRegisterInfo &MRI = MF.getRegInfo();
1136f4a2713aSLionel Sambuc MRI.setPhysRegUnused(LR);
1137f4a2713aSLionel Sambuc
1138f4a2713aSLionel Sambuc // Save R31 if necessary
1139f4a2713aSLionel Sambuc int FPSI = FI->getFramePointerSaveIndex();
1140f4a2713aSLionel Sambuc bool isPPC64 = Subtarget.isPPC64();
1141f4a2713aSLionel Sambuc bool isDarwinABI = Subtarget.isDarwinABI();
1142*0a6a1f1dSLionel Sambuc bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
1143f4a2713aSLionel Sambuc MachineFrameInfo *MFI = MF.getFrameInfo();
1144f4a2713aSLionel Sambuc
1145f4a2713aSLionel Sambuc // If the frame pointer save index hasn't been defined yet.
1146f4a2713aSLionel Sambuc if (!FPSI && needsFP(MF)) {
1147f4a2713aSLionel Sambuc // Find out what the fix offset of the frame pointer save area.
1148f4a2713aSLionel Sambuc int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
1149f4a2713aSLionel Sambuc // Allocate the frame index for frame pointer save area.
1150f4a2713aSLionel Sambuc FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1151f4a2713aSLionel Sambuc // Save the result.
1152f4a2713aSLionel Sambuc FI->setFramePointerSaveIndex(FPSI);
1153f4a2713aSLionel Sambuc }
1154f4a2713aSLionel Sambuc
1155f4a2713aSLionel Sambuc int BPSI = FI->getBasePointerSaveIndex();
1156f4a2713aSLionel Sambuc if (!BPSI && RegInfo->hasBasePointer(MF)) {
1157*0a6a1f1dSLionel Sambuc int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
1158f4a2713aSLionel Sambuc // Allocate the frame index for the base pointer save area.
1159f4a2713aSLionel Sambuc BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1160f4a2713aSLionel Sambuc // Save the result.
1161f4a2713aSLionel Sambuc FI->setBasePointerSaveIndex(BPSI);
1162f4a2713aSLionel Sambuc }
1163f4a2713aSLionel Sambuc
1164*0a6a1f1dSLionel Sambuc // Reserve stack space for the PIC Base register (R30).
1165*0a6a1f1dSLionel Sambuc // Only used in SVR4 32-bit.
1166*0a6a1f1dSLionel Sambuc if (FI->usesPICBase()) {
1167*0a6a1f1dSLionel Sambuc int PBPSI = FI->getPICBasePointerSaveIndex();
1168*0a6a1f1dSLionel Sambuc PBPSI = MFI->CreateFixedObject(4, -8, true);
1169*0a6a1f1dSLionel Sambuc FI->setPICBasePointerSaveIndex(PBPSI);
1170*0a6a1f1dSLionel Sambuc }
1171*0a6a1f1dSLionel Sambuc
1172f4a2713aSLionel Sambuc // Reserve stack space to move the linkage area to in case of a tail call.
1173f4a2713aSLionel Sambuc int TCSPDelta = 0;
1174f4a2713aSLionel Sambuc if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1175f4a2713aSLionel Sambuc (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1176f4a2713aSLionel Sambuc MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1177f4a2713aSLionel Sambuc }
1178f4a2713aSLionel Sambuc
1179f4a2713aSLionel Sambuc // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1180f4a2713aSLionel Sambuc // function uses CR 2, 3, or 4.
1181f4a2713aSLionel Sambuc if (!isPPC64 && !isDarwinABI &&
1182f4a2713aSLionel Sambuc (MRI.isPhysRegUsed(PPC::CR2) ||
1183f4a2713aSLionel Sambuc MRI.isPhysRegUsed(PPC::CR3) ||
1184f4a2713aSLionel Sambuc MRI.isPhysRegUsed(PPC::CR4))) {
1185f4a2713aSLionel Sambuc int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1186f4a2713aSLionel Sambuc FI->setCRSpillFrameIndex(FrameIdx);
1187f4a2713aSLionel Sambuc }
1188f4a2713aSLionel Sambuc }
1189f4a2713aSLionel Sambuc
processFunctionBeforeFrameFinalized(MachineFunction & MF,RegScavenger * RS) const1190f4a2713aSLionel Sambuc void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1191f4a2713aSLionel Sambuc RegScavenger *RS) const {
1192f4a2713aSLionel Sambuc // Early exit if not using the SVR4 ABI.
1193f4a2713aSLionel Sambuc if (!Subtarget.isSVR4ABI()) {
1194f4a2713aSLionel Sambuc addScavengingSpillSlot(MF, RS);
1195f4a2713aSLionel Sambuc return;
1196f4a2713aSLionel Sambuc }
1197f4a2713aSLionel Sambuc
1198f4a2713aSLionel Sambuc // Get callee saved register information.
1199f4a2713aSLionel Sambuc MachineFrameInfo *FFI = MF.getFrameInfo();
1200f4a2713aSLionel Sambuc const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1201f4a2713aSLionel Sambuc
1202f4a2713aSLionel Sambuc // Early exit if no callee saved registers are modified!
1203f4a2713aSLionel Sambuc if (CSI.empty() && !needsFP(MF)) {
1204f4a2713aSLionel Sambuc addScavengingSpillSlot(MF, RS);
1205f4a2713aSLionel Sambuc return;
1206f4a2713aSLionel Sambuc }
1207f4a2713aSLionel Sambuc
1208f4a2713aSLionel Sambuc unsigned MinGPR = PPC::R31;
1209f4a2713aSLionel Sambuc unsigned MinG8R = PPC::X31;
1210f4a2713aSLionel Sambuc unsigned MinFPR = PPC::F31;
1211f4a2713aSLionel Sambuc unsigned MinVR = PPC::V31;
1212f4a2713aSLionel Sambuc
1213f4a2713aSLionel Sambuc bool HasGPSaveArea = false;
1214f4a2713aSLionel Sambuc bool HasG8SaveArea = false;
1215f4a2713aSLionel Sambuc bool HasFPSaveArea = false;
1216f4a2713aSLionel Sambuc bool HasVRSAVESaveArea = false;
1217f4a2713aSLionel Sambuc bool HasVRSaveArea = false;
1218f4a2713aSLionel Sambuc
1219f4a2713aSLionel Sambuc SmallVector<CalleeSavedInfo, 18> GPRegs;
1220f4a2713aSLionel Sambuc SmallVector<CalleeSavedInfo, 18> G8Regs;
1221f4a2713aSLionel Sambuc SmallVector<CalleeSavedInfo, 18> FPRegs;
1222f4a2713aSLionel Sambuc SmallVector<CalleeSavedInfo, 18> VRegs;
1223f4a2713aSLionel Sambuc
1224f4a2713aSLionel Sambuc for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1225f4a2713aSLionel Sambuc unsigned Reg = CSI[i].getReg();
1226f4a2713aSLionel Sambuc if (PPC::GPRCRegClass.contains(Reg)) {
1227f4a2713aSLionel Sambuc HasGPSaveArea = true;
1228f4a2713aSLionel Sambuc
1229f4a2713aSLionel Sambuc GPRegs.push_back(CSI[i]);
1230f4a2713aSLionel Sambuc
1231f4a2713aSLionel Sambuc if (Reg < MinGPR) {
1232f4a2713aSLionel Sambuc MinGPR = Reg;
1233f4a2713aSLionel Sambuc }
1234f4a2713aSLionel Sambuc } else if (PPC::G8RCRegClass.contains(Reg)) {
1235f4a2713aSLionel Sambuc HasG8SaveArea = true;
1236f4a2713aSLionel Sambuc
1237f4a2713aSLionel Sambuc G8Regs.push_back(CSI[i]);
1238f4a2713aSLionel Sambuc
1239f4a2713aSLionel Sambuc if (Reg < MinG8R) {
1240f4a2713aSLionel Sambuc MinG8R = Reg;
1241f4a2713aSLionel Sambuc }
1242f4a2713aSLionel Sambuc } else if (PPC::F8RCRegClass.contains(Reg)) {
1243f4a2713aSLionel Sambuc HasFPSaveArea = true;
1244f4a2713aSLionel Sambuc
1245f4a2713aSLionel Sambuc FPRegs.push_back(CSI[i]);
1246f4a2713aSLionel Sambuc
1247f4a2713aSLionel Sambuc if (Reg < MinFPR) {
1248f4a2713aSLionel Sambuc MinFPR = Reg;
1249f4a2713aSLionel Sambuc }
1250f4a2713aSLionel Sambuc } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1251f4a2713aSLionel Sambuc PPC::CRRCRegClass.contains(Reg)) {
1252f4a2713aSLionel Sambuc ; // do nothing, as we already know whether CRs are spilled
1253f4a2713aSLionel Sambuc } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1254f4a2713aSLionel Sambuc HasVRSAVESaveArea = true;
1255f4a2713aSLionel Sambuc } else if (PPC::VRRCRegClass.contains(Reg)) {
1256f4a2713aSLionel Sambuc HasVRSaveArea = true;
1257f4a2713aSLionel Sambuc
1258f4a2713aSLionel Sambuc VRegs.push_back(CSI[i]);
1259f4a2713aSLionel Sambuc
1260f4a2713aSLionel Sambuc if (Reg < MinVR) {
1261f4a2713aSLionel Sambuc MinVR = Reg;
1262f4a2713aSLionel Sambuc }
1263f4a2713aSLionel Sambuc } else {
1264f4a2713aSLionel Sambuc llvm_unreachable("Unknown RegisterClass!");
1265f4a2713aSLionel Sambuc }
1266f4a2713aSLionel Sambuc }
1267f4a2713aSLionel Sambuc
1268f4a2713aSLionel Sambuc PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1269*0a6a1f1dSLionel Sambuc const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1270f4a2713aSLionel Sambuc
1271f4a2713aSLionel Sambuc int64_t LowerBound = 0;
1272f4a2713aSLionel Sambuc
1273f4a2713aSLionel Sambuc // Take into account stack space reserved for tail calls.
1274f4a2713aSLionel Sambuc int TCSPDelta = 0;
1275f4a2713aSLionel Sambuc if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1276f4a2713aSLionel Sambuc (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1277f4a2713aSLionel Sambuc LowerBound = TCSPDelta;
1278f4a2713aSLionel Sambuc }
1279f4a2713aSLionel Sambuc
1280f4a2713aSLionel Sambuc // The Floating-point register save area is right below the back chain word
1281f4a2713aSLionel Sambuc // of the previous stack frame.
1282f4a2713aSLionel Sambuc if (HasFPSaveArea) {
1283f4a2713aSLionel Sambuc for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1284f4a2713aSLionel Sambuc int FI = FPRegs[i].getFrameIdx();
1285f4a2713aSLionel Sambuc
1286f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1287f4a2713aSLionel Sambuc }
1288f4a2713aSLionel Sambuc
1289f4a2713aSLionel Sambuc LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1290f4a2713aSLionel Sambuc }
1291f4a2713aSLionel Sambuc
1292f4a2713aSLionel Sambuc // Check whether the frame pointer register is allocated. If so, make sure it
1293f4a2713aSLionel Sambuc // is spilled to the correct offset.
1294f4a2713aSLionel Sambuc if (needsFP(MF)) {
1295f4a2713aSLionel Sambuc HasGPSaveArea = true;
1296f4a2713aSLionel Sambuc
1297f4a2713aSLionel Sambuc int FI = PFI->getFramePointerSaveIndex();
1298f4a2713aSLionel Sambuc assert(FI && "No Frame Pointer Save Slot!");
1299f4a2713aSLionel Sambuc
1300f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1301f4a2713aSLionel Sambuc }
1302f4a2713aSLionel Sambuc
1303*0a6a1f1dSLionel Sambuc if (PFI->usesPICBase()) {
1304*0a6a1f1dSLionel Sambuc HasGPSaveArea = true;
1305*0a6a1f1dSLionel Sambuc
1306*0a6a1f1dSLionel Sambuc int FI = PFI->getPICBasePointerSaveIndex();
1307*0a6a1f1dSLionel Sambuc assert(FI && "No PIC Base Pointer Save Slot!");
1308*0a6a1f1dSLionel Sambuc
1309*0a6a1f1dSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1310*0a6a1f1dSLionel Sambuc }
1311*0a6a1f1dSLionel Sambuc
1312f4a2713aSLionel Sambuc const PPCRegisterInfo *RegInfo =
1313*0a6a1f1dSLionel Sambuc static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1314f4a2713aSLionel Sambuc if (RegInfo->hasBasePointer(MF)) {
1315f4a2713aSLionel Sambuc HasGPSaveArea = true;
1316f4a2713aSLionel Sambuc
1317f4a2713aSLionel Sambuc int FI = PFI->getBasePointerSaveIndex();
1318f4a2713aSLionel Sambuc assert(FI && "No Base Pointer Save Slot!");
1319f4a2713aSLionel Sambuc
1320f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1321f4a2713aSLionel Sambuc }
1322f4a2713aSLionel Sambuc
1323f4a2713aSLionel Sambuc // General register save area starts right below the Floating-point
1324f4a2713aSLionel Sambuc // register save area.
1325f4a2713aSLionel Sambuc if (HasGPSaveArea || HasG8SaveArea) {
1326f4a2713aSLionel Sambuc // Move general register save area spill slots down, taking into account
1327f4a2713aSLionel Sambuc // the size of the Floating-point register save area.
1328f4a2713aSLionel Sambuc for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1329f4a2713aSLionel Sambuc int FI = GPRegs[i].getFrameIdx();
1330f4a2713aSLionel Sambuc
1331f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1332f4a2713aSLionel Sambuc }
1333f4a2713aSLionel Sambuc
1334f4a2713aSLionel Sambuc // Move general register save area spill slots down, taking into account
1335f4a2713aSLionel Sambuc // the size of the Floating-point register save area.
1336f4a2713aSLionel Sambuc for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1337f4a2713aSLionel Sambuc int FI = G8Regs[i].getFrameIdx();
1338f4a2713aSLionel Sambuc
1339f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1340f4a2713aSLionel Sambuc }
1341f4a2713aSLionel Sambuc
1342f4a2713aSLionel Sambuc unsigned MinReg =
1343f4a2713aSLionel Sambuc std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1344f4a2713aSLionel Sambuc TRI->getEncodingValue(MinG8R));
1345f4a2713aSLionel Sambuc
1346f4a2713aSLionel Sambuc if (Subtarget.isPPC64()) {
1347f4a2713aSLionel Sambuc LowerBound -= (31 - MinReg + 1) * 8;
1348f4a2713aSLionel Sambuc } else {
1349f4a2713aSLionel Sambuc LowerBound -= (31 - MinReg + 1) * 4;
1350f4a2713aSLionel Sambuc }
1351f4a2713aSLionel Sambuc }
1352f4a2713aSLionel Sambuc
1353f4a2713aSLionel Sambuc // For 32-bit only, the CR save area is below the general register
1354f4a2713aSLionel Sambuc // save area. For 64-bit SVR4, the CR save area is addressed relative
1355f4a2713aSLionel Sambuc // to the stack pointer and hence does not need an adjustment here.
1356f4a2713aSLionel Sambuc // Only CR2 (the first nonvolatile spilled) has an associated frame
1357f4a2713aSLionel Sambuc // index so that we have a single uniform save area.
1358f4a2713aSLionel Sambuc if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1359f4a2713aSLionel Sambuc // Adjust the frame index of the CR spill slot.
1360f4a2713aSLionel Sambuc for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1361f4a2713aSLionel Sambuc unsigned Reg = CSI[i].getReg();
1362f4a2713aSLionel Sambuc
1363f4a2713aSLionel Sambuc if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1364f4a2713aSLionel Sambuc // Leave Darwin logic as-is.
1365f4a2713aSLionel Sambuc || (!Subtarget.isSVR4ABI() &&
1366f4a2713aSLionel Sambuc (PPC::CRBITRCRegClass.contains(Reg) ||
1367f4a2713aSLionel Sambuc PPC::CRRCRegClass.contains(Reg)))) {
1368f4a2713aSLionel Sambuc int FI = CSI[i].getFrameIdx();
1369f4a2713aSLionel Sambuc
1370f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1371f4a2713aSLionel Sambuc }
1372f4a2713aSLionel Sambuc }
1373f4a2713aSLionel Sambuc
1374f4a2713aSLionel Sambuc LowerBound -= 4; // The CR save area is always 4 bytes long.
1375f4a2713aSLionel Sambuc }
1376f4a2713aSLionel Sambuc
1377f4a2713aSLionel Sambuc if (HasVRSAVESaveArea) {
1378f4a2713aSLionel Sambuc // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1379f4a2713aSLionel Sambuc // which have the VRSAVE register class?
1380f4a2713aSLionel Sambuc // Adjust the frame index of the VRSAVE spill slot.
1381f4a2713aSLionel Sambuc for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1382f4a2713aSLionel Sambuc unsigned Reg = CSI[i].getReg();
1383f4a2713aSLionel Sambuc
1384f4a2713aSLionel Sambuc if (PPC::VRSAVERCRegClass.contains(Reg)) {
1385f4a2713aSLionel Sambuc int FI = CSI[i].getFrameIdx();
1386f4a2713aSLionel Sambuc
1387f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1388f4a2713aSLionel Sambuc }
1389f4a2713aSLionel Sambuc }
1390f4a2713aSLionel Sambuc
1391f4a2713aSLionel Sambuc LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1392f4a2713aSLionel Sambuc }
1393f4a2713aSLionel Sambuc
1394f4a2713aSLionel Sambuc if (HasVRSaveArea) {
1395f4a2713aSLionel Sambuc // Insert alignment padding, we need 16-byte alignment.
1396f4a2713aSLionel Sambuc LowerBound = (LowerBound - 15) & ~(15);
1397f4a2713aSLionel Sambuc
1398f4a2713aSLionel Sambuc for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1399f4a2713aSLionel Sambuc int FI = VRegs[i].getFrameIdx();
1400f4a2713aSLionel Sambuc
1401f4a2713aSLionel Sambuc FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1402f4a2713aSLionel Sambuc }
1403f4a2713aSLionel Sambuc }
1404f4a2713aSLionel Sambuc
1405f4a2713aSLionel Sambuc addScavengingSpillSlot(MF, RS);
1406f4a2713aSLionel Sambuc }
1407f4a2713aSLionel Sambuc
1408f4a2713aSLionel Sambuc void
addScavengingSpillSlot(MachineFunction & MF,RegScavenger * RS) const1409f4a2713aSLionel Sambuc PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1410f4a2713aSLionel Sambuc RegScavenger *RS) const {
1411f4a2713aSLionel Sambuc // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1412f4a2713aSLionel Sambuc // a large stack, which will require scavenging a register to materialize a
1413f4a2713aSLionel Sambuc // large offset.
1414f4a2713aSLionel Sambuc
1415f4a2713aSLionel Sambuc // We need to have a scavenger spill slot for spills if the frame size is
1416f4a2713aSLionel Sambuc // large. In case there is no free register for large-offset addressing,
1417f4a2713aSLionel Sambuc // this slot is used for the necessary emergency spill. Also, we need the
1418f4a2713aSLionel Sambuc // slot for dynamic stack allocations.
1419f4a2713aSLionel Sambuc
1420f4a2713aSLionel Sambuc // The scavenger might be invoked if the frame offset does not fit into
1421f4a2713aSLionel Sambuc // the 16-bit immediate. We don't know the complete frame size here
1422f4a2713aSLionel Sambuc // because we've not yet computed callee-saved register spills or the
1423f4a2713aSLionel Sambuc // needed alignment padding.
1424f4a2713aSLionel Sambuc unsigned StackSize = determineFrameLayout(MF, false, true);
1425f4a2713aSLionel Sambuc MachineFrameInfo *MFI = MF.getFrameInfo();
1426f4a2713aSLionel Sambuc if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1427f4a2713aSLionel Sambuc hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1428f4a2713aSLionel Sambuc const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1429f4a2713aSLionel Sambuc const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1430f4a2713aSLionel Sambuc const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1431f4a2713aSLionel Sambuc RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1432f4a2713aSLionel Sambuc RC->getAlignment(),
1433f4a2713aSLionel Sambuc false));
1434f4a2713aSLionel Sambuc
1435f4a2713aSLionel Sambuc // Might we have over-aligned allocas?
1436f4a2713aSLionel Sambuc bool HasAlVars = MFI->hasVarSizedObjects() &&
1437f4a2713aSLionel Sambuc MFI->getMaxAlignment() > getStackAlignment();
1438f4a2713aSLionel Sambuc
1439f4a2713aSLionel Sambuc // These kinds of spills might need two registers.
1440f4a2713aSLionel Sambuc if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1441f4a2713aSLionel Sambuc RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1442f4a2713aSLionel Sambuc RC->getAlignment(),
1443f4a2713aSLionel Sambuc false));
1444f4a2713aSLionel Sambuc
1445f4a2713aSLionel Sambuc }
1446f4a2713aSLionel Sambuc }
1447f4a2713aSLionel Sambuc
1448f4a2713aSLionel Sambuc bool
spillCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const1449f4a2713aSLionel Sambuc PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1450f4a2713aSLionel Sambuc MachineBasicBlock::iterator MI,
1451f4a2713aSLionel Sambuc const std::vector<CalleeSavedInfo> &CSI,
1452f4a2713aSLionel Sambuc const TargetRegisterInfo *TRI) const {
1453f4a2713aSLionel Sambuc
1454f4a2713aSLionel Sambuc // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1455f4a2713aSLionel Sambuc // Return false otherwise to maintain pre-existing behavior.
1456f4a2713aSLionel Sambuc if (!Subtarget.isSVR4ABI())
1457f4a2713aSLionel Sambuc return false;
1458f4a2713aSLionel Sambuc
1459f4a2713aSLionel Sambuc MachineFunction *MF = MBB.getParent();
1460f4a2713aSLionel Sambuc const PPCInstrInfo &TII =
1461*0a6a1f1dSLionel Sambuc *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1462f4a2713aSLionel Sambuc DebugLoc DL;
1463f4a2713aSLionel Sambuc bool CRSpilled = false;
1464f4a2713aSLionel Sambuc MachineInstrBuilder CRMIB;
1465f4a2713aSLionel Sambuc
1466f4a2713aSLionel Sambuc for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1467f4a2713aSLionel Sambuc unsigned Reg = CSI[i].getReg();
1468f4a2713aSLionel Sambuc // Only Darwin actually uses the VRSAVE register, but it can still appear
1469f4a2713aSLionel Sambuc // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1470f4a2713aSLionel Sambuc // Darwin, ignore it.
1471f4a2713aSLionel Sambuc if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1472f4a2713aSLionel Sambuc continue;
1473f4a2713aSLionel Sambuc
1474f4a2713aSLionel Sambuc // CR2 through CR4 are the nonvolatile CR fields.
1475f4a2713aSLionel Sambuc bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1476f4a2713aSLionel Sambuc
1477f4a2713aSLionel Sambuc // Add the callee-saved register as live-in; it's killed at the spill.
1478f4a2713aSLionel Sambuc MBB.addLiveIn(Reg);
1479f4a2713aSLionel Sambuc
1480f4a2713aSLionel Sambuc if (CRSpilled && IsCRField) {
1481f4a2713aSLionel Sambuc CRMIB.addReg(Reg, RegState::ImplicitKill);
1482f4a2713aSLionel Sambuc continue;
1483f4a2713aSLionel Sambuc }
1484f4a2713aSLionel Sambuc
1485f4a2713aSLionel Sambuc // Insert the spill to the stack frame.
1486f4a2713aSLionel Sambuc if (IsCRField) {
1487f4a2713aSLionel Sambuc PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1488f4a2713aSLionel Sambuc if (Subtarget.isPPC64()) {
1489f4a2713aSLionel Sambuc // The actual spill will happen at the start of the prologue.
1490f4a2713aSLionel Sambuc FuncInfo->addMustSaveCR(Reg);
1491f4a2713aSLionel Sambuc } else {
1492f4a2713aSLionel Sambuc CRSpilled = true;
1493f4a2713aSLionel Sambuc FuncInfo->setSpillsCR();
1494f4a2713aSLionel Sambuc
1495f4a2713aSLionel Sambuc // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1496f4a2713aSLionel Sambuc // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1497f4a2713aSLionel Sambuc CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1498f4a2713aSLionel Sambuc .addReg(Reg, RegState::ImplicitKill);
1499f4a2713aSLionel Sambuc
1500f4a2713aSLionel Sambuc MBB.insert(MI, CRMIB);
1501f4a2713aSLionel Sambuc MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1502f4a2713aSLionel Sambuc .addReg(PPC::R12,
1503f4a2713aSLionel Sambuc getKillRegState(true)),
1504f4a2713aSLionel Sambuc CSI[i].getFrameIdx()));
1505f4a2713aSLionel Sambuc }
1506f4a2713aSLionel Sambuc } else {
1507f4a2713aSLionel Sambuc const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1508f4a2713aSLionel Sambuc TII.storeRegToStackSlot(MBB, MI, Reg, true,
1509f4a2713aSLionel Sambuc CSI[i].getFrameIdx(), RC, TRI);
1510f4a2713aSLionel Sambuc }
1511f4a2713aSLionel Sambuc }
1512f4a2713aSLionel Sambuc return true;
1513f4a2713aSLionel Sambuc }
1514f4a2713aSLionel Sambuc
1515f4a2713aSLionel Sambuc static void
restoreCRs(bool isPPC64,bool is31,bool CR2Spilled,bool CR3Spilled,bool CR4Spilled,MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,unsigned CSIIndex)1516f4a2713aSLionel Sambuc restoreCRs(bool isPPC64, bool is31,
1517f4a2713aSLionel Sambuc bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1518f4a2713aSLionel Sambuc MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1519f4a2713aSLionel Sambuc const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1520f4a2713aSLionel Sambuc
1521f4a2713aSLionel Sambuc MachineFunction *MF = MBB.getParent();
1522f4a2713aSLionel Sambuc const PPCInstrInfo &TII =
1523*0a6a1f1dSLionel Sambuc *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1524f4a2713aSLionel Sambuc DebugLoc DL;
1525f4a2713aSLionel Sambuc unsigned RestoreOp, MoveReg;
1526f4a2713aSLionel Sambuc
1527f4a2713aSLionel Sambuc if (isPPC64)
1528f4a2713aSLionel Sambuc // This is handled during epilogue generation.
1529f4a2713aSLionel Sambuc return;
1530f4a2713aSLionel Sambuc else {
1531f4a2713aSLionel Sambuc // 32-bit: FP-relative
1532f4a2713aSLionel Sambuc MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1533f4a2713aSLionel Sambuc PPC::R12),
1534f4a2713aSLionel Sambuc CSI[CSIIndex].getFrameIdx()));
1535f4a2713aSLionel Sambuc RestoreOp = PPC::MTOCRF;
1536f4a2713aSLionel Sambuc MoveReg = PPC::R12;
1537f4a2713aSLionel Sambuc }
1538f4a2713aSLionel Sambuc
1539f4a2713aSLionel Sambuc if (CR2Spilled)
1540f4a2713aSLionel Sambuc MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1541f4a2713aSLionel Sambuc .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1542f4a2713aSLionel Sambuc
1543f4a2713aSLionel Sambuc if (CR3Spilled)
1544f4a2713aSLionel Sambuc MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1545f4a2713aSLionel Sambuc .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1546f4a2713aSLionel Sambuc
1547f4a2713aSLionel Sambuc if (CR4Spilled)
1548f4a2713aSLionel Sambuc MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1549f4a2713aSLionel Sambuc .addReg(MoveReg, getKillRegState(true)));
1550f4a2713aSLionel Sambuc }
1551f4a2713aSLionel Sambuc
1552f4a2713aSLionel Sambuc void PPCFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const1553f4a2713aSLionel Sambuc eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1554f4a2713aSLionel Sambuc MachineBasicBlock::iterator I) const {
1555f4a2713aSLionel Sambuc const PPCInstrInfo &TII =
1556*0a6a1f1dSLionel Sambuc *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
1557f4a2713aSLionel Sambuc if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1558f4a2713aSLionel Sambuc I->getOpcode() == PPC::ADJCALLSTACKUP) {
1559f4a2713aSLionel Sambuc // Add (actually subtract) back the amount the callee popped on return.
1560f4a2713aSLionel Sambuc if (int CalleeAmt = I->getOperand(1).getImm()) {
1561f4a2713aSLionel Sambuc bool is64Bit = Subtarget.isPPC64();
1562f4a2713aSLionel Sambuc CalleeAmt *= -1;
1563f4a2713aSLionel Sambuc unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1564f4a2713aSLionel Sambuc unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1565f4a2713aSLionel Sambuc unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1566f4a2713aSLionel Sambuc unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1567f4a2713aSLionel Sambuc unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1568f4a2713aSLionel Sambuc unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1569f4a2713aSLionel Sambuc MachineInstr *MI = I;
1570f4a2713aSLionel Sambuc DebugLoc dl = MI->getDebugLoc();
1571f4a2713aSLionel Sambuc
1572f4a2713aSLionel Sambuc if (isInt<16>(CalleeAmt)) {
1573f4a2713aSLionel Sambuc BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1574f4a2713aSLionel Sambuc .addReg(StackReg, RegState::Kill)
1575f4a2713aSLionel Sambuc .addImm(CalleeAmt);
1576f4a2713aSLionel Sambuc } else {
1577f4a2713aSLionel Sambuc MachineBasicBlock::iterator MBBI = I;
1578f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1579f4a2713aSLionel Sambuc .addImm(CalleeAmt >> 16);
1580f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1581f4a2713aSLionel Sambuc .addReg(TmpReg, RegState::Kill)
1582f4a2713aSLionel Sambuc .addImm(CalleeAmt & 0xFFFF);
1583f4a2713aSLionel Sambuc BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1584f4a2713aSLionel Sambuc .addReg(StackReg, RegState::Kill)
1585f4a2713aSLionel Sambuc .addReg(TmpReg);
1586f4a2713aSLionel Sambuc }
1587f4a2713aSLionel Sambuc }
1588f4a2713aSLionel Sambuc }
1589f4a2713aSLionel Sambuc // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1590f4a2713aSLionel Sambuc MBB.erase(I);
1591f4a2713aSLionel Sambuc }
1592f4a2713aSLionel Sambuc
1593f4a2713aSLionel Sambuc bool
restoreCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const1594f4a2713aSLionel Sambuc PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1595f4a2713aSLionel Sambuc MachineBasicBlock::iterator MI,
1596f4a2713aSLionel Sambuc const std::vector<CalleeSavedInfo> &CSI,
1597f4a2713aSLionel Sambuc const TargetRegisterInfo *TRI) const {
1598f4a2713aSLionel Sambuc
1599f4a2713aSLionel Sambuc // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1600f4a2713aSLionel Sambuc // Return false otherwise to maintain pre-existing behavior.
1601f4a2713aSLionel Sambuc if (!Subtarget.isSVR4ABI())
1602f4a2713aSLionel Sambuc return false;
1603f4a2713aSLionel Sambuc
1604f4a2713aSLionel Sambuc MachineFunction *MF = MBB.getParent();
1605f4a2713aSLionel Sambuc const PPCInstrInfo &TII =
1606*0a6a1f1dSLionel Sambuc *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1607f4a2713aSLionel Sambuc bool CR2Spilled = false;
1608f4a2713aSLionel Sambuc bool CR3Spilled = false;
1609f4a2713aSLionel Sambuc bool CR4Spilled = false;
1610f4a2713aSLionel Sambuc unsigned CSIIndex = 0;
1611f4a2713aSLionel Sambuc
1612f4a2713aSLionel Sambuc // Initialize insertion-point logic; we will be restoring in reverse
1613f4a2713aSLionel Sambuc // order of spill.
1614f4a2713aSLionel Sambuc MachineBasicBlock::iterator I = MI, BeforeI = I;
1615f4a2713aSLionel Sambuc bool AtStart = I == MBB.begin();
1616f4a2713aSLionel Sambuc
1617f4a2713aSLionel Sambuc if (!AtStart)
1618f4a2713aSLionel Sambuc --BeforeI;
1619f4a2713aSLionel Sambuc
1620f4a2713aSLionel Sambuc for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1621f4a2713aSLionel Sambuc unsigned Reg = CSI[i].getReg();
1622f4a2713aSLionel Sambuc
1623f4a2713aSLionel Sambuc // Only Darwin actually uses the VRSAVE register, but it can still appear
1624f4a2713aSLionel Sambuc // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1625f4a2713aSLionel Sambuc // Darwin, ignore it.
1626f4a2713aSLionel Sambuc if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1627f4a2713aSLionel Sambuc continue;
1628f4a2713aSLionel Sambuc
1629f4a2713aSLionel Sambuc if (Reg == PPC::CR2) {
1630f4a2713aSLionel Sambuc CR2Spilled = true;
1631f4a2713aSLionel Sambuc // The spill slot is associated only with CR2, which is the
1632f4a2713aSLionel Sambuc // first nonvolatile spilled. Save it here.
1633f4a2713aSLionel Sambuc CSIIndex = i;
1634f4a2713aSLionel Sambuc continue;
1635f4a2713aSLionel Sambuc } else if (Reg == PPC::CR3) {
1636f4a2713aSLionel Sambuc CR3Spilled = true;
1637f4a2713aSLionel Sambuc continue;
1638f4a2713aSLionel Sambuc } else if (Reg == PPC::CR4) {
1639f4a2713aSLionel Sambuc CR4Spilled = true;
1640f4a2713aSLionel Sambuc continue;
1641f4a2713aSLionel Sambuc } else {
1642f4a2713aSLionel Sambuc // When we first encounter a non-CR register after seeing at
1643f4a2713aSLionel Sambuc // least one CR register, restore all spilled CRs together.
1644f4a2713aSLionel Sambuc if ((CR2Spilled || CR3Spilled || CR4Spilled)
1645f4a2713aSLionel Sambuc && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1646f4a2713aSLionel Sambuc bool is31 = needsFP(*MF);
1647f4a2713aSLionel Sambuc restoreCRs(Subtarget.isPPC64(), is31,
1648f4a2713aSLionel Sambuc CR2Spilled, CR3Spilled, CR4Spilled,
1649f4a2713aSLionel Sambuc MBB, I, CSI, CSIIndex);
1650f4a2713aSLionel Sambuc CR2Spilled = CR3Spilled = CR4Spilled = false;
1651f4a2713aSLionel Sambuc }
1652f4a2713aSLionel Sambuc
1653f4a2713aSLionel Sambuc // Default behavior for non-CR saves.
1654f4a2713aSLionel Sambuc const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1655f4a2713aSLionel Sambuc TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1656f4a2713aSLionel Sambuc RC, TRI);
1657f4a2713aSLionel Sambuc assert(I != MBB.begin() &&
1658f4a2713aSLionel Sambuc "loadRegFromStackSlot didn't insert any code!");
1659f4a2713aSLionel Sambuc }
1660f4a2713aSLionel Sambuc
1661f4a2713aSLionel Sambuc // Insert in reverse order.
1662f4a2713aSLionel Sambuc if (AtStart)
1663f4a2713aSLionel Sambuc I = MBB.begin();
1664f4a2713aSLionel Sambuc else {
1665f4a2713aSLionel Sambuc I = BeforeI;
1666f4a2713aSLionel Sambuc ++I;
1667f4a2713aSLionel Sambuc }
1668f4a2713aSLionel Sambuc }
1669f4a2713aSLionel Sambuc
1670f4a2713aSLionel Sambuc // If we haven't yet spilled the CRs, do so now.
1671f4a2713aSLionel Sambuc if (CR2Spilled || CR3Spilled || CR4Spilled) {
1672f4a2713aSLionel Sambuc bool is31 = needsFP(*MF);
1673f4a2713aSLionel Sambuc restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1674f4a2713aSLionel Sambuc MBB, I, CSI, CSIIndex);
1675f4a2713aSLionel Sambuc }
1676f4a2713aSLionel Sambuc
1677f4a2713aSLionel Sambuc return true;
1678f4a2713aSLionel Sambuc }
1679