1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PPC implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Target/TargetOptions.h"
27
28 using namespace llvm;
29
30 /// VRRegNo - Map from a numbered VR register to its enum value.
31 ///
32 static const uint16_t VRRegNo[] = {
33 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
37 };
38
PPCFrameLowering(const PPCSubtarget & STI)39 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
40 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
42 Subtarget(STI) {}
43
44 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
getCalleeSavedSpillSlots(unsigned & NumEntries) const45 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
46 unsigned &NumEntries) const {
47 if (Subtarget.isDarwinABI()) {
48 NumEntries = 1;
49 if (Subtarget.isPPC64()) {
50 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
51 return &darwin64Offsets;
52 } else {
53 static const SpillSlot darwinOffsets = {PPC::R31, -4};
54 return &darwinOffsets;
55 }
56 }
57
58 // Early exit if not using the SVR4 ABI.
59 if (!Subtarget.isSVR4ABI()) {
60 NumEntries = 0;
61 return nullptr;
62 }
63
64 // Note that the offsets here overlap, but this is fixed up in
65 // processFunctionBeforeFrameFinalized.
66
67 static const SpillSlot Offsets[] = {
68 // Floating-point register save area offsets.
69 {PPC::F31, -8},
70 {PPC::F30, -16},
71 {PPC::F29, -24},
72 {PPC::F28, -32},
73 {PPC::F27, -40},
74 {PPC::F26, -48},
75 {PPC::F25, -56},
76 {PPC::F24, -64},
77 {PPC::F23, -72},
78 {PPC::F22, -80},
79 {PPC::F21, -88},
80 {PPC::F20, -96},
81 {PPC::F19, -104},
82 {PPC::F18, -112},
83 {PPC::F17, -120},
84 {PPC::F16, -128},
85 {PPC::F15, -136},
86 {PPC::F14, -144},
87
88 // General register save area offsets.
89 {PPC::R31, -4},
90 {PPC::R30, -8},
91 {PPC::R29, -12},
92 {PPC::R28, -16},
93 {PPC::R27, -20},
94 {PPC::R26, -24},
95 {PPC::R25, -28},
96 {PPC::R24, -32},
97 {PPC::R23, -36},
98 {PPC::R22, -40},
99 {PPC::R21, -44},
100 {PPC::R20, -48},
101 {PPC::R19, -52},
102 {PPC::R18, -56},
103 {PPC::R17, -60},
104 {PPC::R16, -64},
105 {PPC::R15, -68},
106 {PPC::R14, -72},
107
108 // CR save area offset. We map each of the nonvolatile CR fields
109 // to the slot for CR2, which is the first of the nonvolatile CR
110 // fields to be assigned, so that we only allocate one save slot.
111 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
112 {PPC::CR2, -4},
113
114 // VRSAVE save area offset.
115 {PPC::VRSAVE, -4},
116
117 // Vector register save area
118 {PPC::V31, -16},
119 {PPC::V30, -32},
120 {PPC::V29, -48},
121 {PPC::V28, -64},
122 {PPC::V27, -80},
123 {PPC::V26, -96},
124 {PPC::V25, -112},
125 {PPC::V24, -128},
126 {PPC::V23, -144},
127 {PPC::V22, -160},
128 {PPC::V21, -176},
129 {PPC::V20, -192}};
130
131 static const SpillSlot Offsets64[] = {
132 // Floating-point register save area offsets.
133 {PPC::F31, -8},
134 {PPC::F30, -16},
135 {PPC::F29, -24},
136 {PPC::F28, -32},
137 {PPC::F27, -40},
138 {PPC::F26, -48},
139 {PPC::F25, -56},
140 {PPC::F24, -64},
141 {PPC::F23, -72},
142 {PPC::F22, -80},
143 {PPC::F21, -88},
144 {PPC::F20, -96},
145 {PPC::F19, -104},
146 {PPC::F18, -112},
147 {PPC::F17, -120},
148 {PPC::F16, -128},
149 {PPC::F15, -136},
150 {PPC::F14, -144},
151
152 // General register save area offsets.
153 {PPC::X31, -8},
154 {PPC::X30, -16},
155 {PPC::X29, -24},
156 {PPC::X28, -32},
157 {PPC::X27, -40},
158 {PPC::X26, -48},
159 {PPC::X25, -56},
160 {PPC::X24, -64},
161 {PPC::X23, -72},
162 {PPC::X22, -80},
163 {PPC::X21, -88},
164 {PPC::X20, -96},
165 {PPC::X19, -104},
166 {PPC::X18, -112},
167 {PPC::X17, -120},
168 {PPC::X16, -128},
169 {PPC::X15, -136},
170 {PPC::X14, -144},
171
172 // VRSAVE save area offset.
173 {PPC::VRSAVE, -4},
174
175 // Vector register save area
176 {PPC::V31, -16},
177 {PPC::V30, -32},
178 {PPC::V29, -48},
179 {PPC::V28, -64},
180 {PPC::V27, -80},
181 {PPC::V26, -96},
182 {PPC::V25, -112},
183 {PPC::V24, -128},
184 {PPC::V23, -144},
185 {PPC::V22, -160},
186 {PPC::V21, -176},
187 {PPC::V20, -192}};
188
189 if (Subtarget.isPPC64()) {
190 NumEntries = array_lengthof(Offsets64);
191
192 return Offsets64;
193 } else {
194 NumEntries = array_lengthof(Offsets);
195
196 return Offsets;
197 }
198 }
199
200 /// RemoveVRSaveCode - We have found that this function does not need any code
201 /// to manipulate the VRSAVE register, even though it uses vector registers.
202 /// This can happen when the only registers used are known to be live in or out
203 /// of the function. Remove all of the VRSAVE related code from the function.
204 /// FIXME: The removal of the code results in a compile failure at -O0 when the
205 /// function contains a function call, as the GPR containing original VRSAVE
206 /// contents is spilled and reloaded around the call. Without the prolog code,
207 /// the spill instruction refers to an undefined register. This code needs
208 /// to account for all uses of that GPR.
RemoveVRSaveCode(MachineInstr * MI)209 static void RemoveVRSaveCode(MachineInstr *MI) {
210 MachineBasicBlock *Entry = MI->getParent();
211 MachineFunction *MF = Entry->getParent();
212
213 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
214 MachineBasicBlock::iterator MBBI = MI;
215 ++MBBI;
216 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
217 MBBI->eraseFromParent();
218
219 bool RemovedAllMTVRSAVEs = true;
220 // See if we can find and remove the MTVRSAVE instruction from all of the
221 // epilog blocks.
222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
223 // If last instruction is a return instruction, add an epilogue
224 if (!I->empty() && I->back().isReturn()) {
225 bool FoundIt = false;
226 for (MBBI = I->end(); MBBI != I->begin(); ) {
227 --MBBI;
228 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
229 MBBI->eraseFromParent(); // remove it.
230 FoundIt = true;
231 break;
232 }
233 }
234 RemovedAllMTVRSAVEs &= FoundIt;
235 }
236 }
237
238 // If we found and removed all MTVRSAVE instructions, remove the read of
239 // VRSAVE as well.
240 if (RemovedAllMTVRSAVEs) {
241 MBBI = MI;
242 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
243 --MBBI;
244 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
245 MBBI->eraseFromParent();
246 }
247
248 // Finally, nuke the UPDATE_VRSAVE.
249 MI->eraseFromParent();
250 }
251
252 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
253 // instruction selector. Based on the vector registers that have been used,
254 // transform this into the appropriate ORI instruction.
HandleVRSaveUpdate(MachineInstr * MI,const TargetInstrInfo & TII)255 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
256 MachineFunction *MF = MI->getParent()->getParent();
257 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
258 DebugLoc dl = MI->getDebugLoc();
259
260 unsigned UsedRegMask = 0;
261 for (unsigned i = 0; i != 32; ++i)
262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
263 UsedRegMask |= 1 << (31-i);
264
265 // Live in and live out values already must be in the mask, so don't bother
266 // marking them.
267 for (MachineRegisterInfo::livein_iterator
268 I = MF->getRegInfo().livein_begin(),
269 E = MF->getRegInfo().livein_end(); I != E; ++I) {
270 unsigned RegNo = TRI->getEncodingValue(I->first);
271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
273 }
274
275 // Live out registers appear as use operands on return instructions.
276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
277 UsedRegMask != 0 && BI != BE; ++BI) {
278 const MachineBasicBlock &MBB = *BI;
279 if (MBB.empty() || !MBB.back().isReturn())
280 continue;
281 const MachineInstr &Ret = MBB.back();
282 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
283 const MachineOperand &MO = Ret.getOperand(I);
284 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
285 continue;
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
287 UsedRegMask &= ~(1 << (31-RegNo));
288 }
289 }
290
291 // If no registers are used, turn this into a copy.
292 if (UsedRegMask == 0) {
293 // Remove all VRSAVE code.
294 RemoveVRSaveCode(MI);
295 return;
296 }
297
298 unsigned SrcReg = MI->getOperand(1).getReg();
299 unsigned DstReg = MI->getOperand(0).getReg();
300
301 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
302 if (DstReg != SrcReg)
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
304 .addReg(SrcReg)
305 .addImm(UsedRegMask);
306 else
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
308 .addReg(SrcReg, RegState::Kill)
309 .addImm(UsedRegMask);
310 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
311 if (DstReg != SrcReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
313 .addReg(SrcReg)
314 .addImm(UsedRegMask >> 16);
315 else
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
317 .addReg(SrcReg, RegState::Kill)
318 .addImm(UsedRegMask >> 16);
319 } else {
320 if (DstReg != SrcReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
322 .addReg(SrcReg)
323 .addImm(UsedRegMask >> 16);
324 else
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
326 .addReg(SrcReg, RegState::Kill)
327 .addImm(UsedRegMask >> 16);
328
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
330 .addReg(DstReg, RegState::Kill)
331 .addImm(UsedRegMask & 0xFFFF);
332 }
333
334 // Remove the old UPDATE_VRSAVE instruction.
335 MI->eraseFromParent();
336 }
337
spillsCR(const MachineFunction & MF)338 static bool spillsCR(const MachineFunction &MF) {
339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340 return FuncInfo->isCRSpilled();
341 }
342
spillsVRSAVE(const MachineFunction & MF)343 static bool spillsVRSAVE(const MachineFunction &MF) {
344 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
345 return FuncInfo->isVRSAVESpilled();
346 }
347
hasSpills(const MachineFunction & MF)348 static bool hasSpills(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->hasSpills();
351 }
352
hasNonRISpills(const MachineFunction & MF)353 static bool hasNonRISpills(const MachineFunction &MF) {
354 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
355 return FuncInfo->hasNonRISpills();
356 }
357
358 /// determineFrameLayout - Determine the size of the frame and maximum call
359 /// frame size.
determineFrameLayout(MachineFunction & MF,bool UpdateMF,bool UseEstimate) const360 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
361 bool UpdateMF,
362 bool UseEstimate) const {
363 MachineFrameInfo *MFI = MF.getFrameInfo();
364
365 // Get the number of bytes to allocate from the FrameInfo
366 unsigned FrameSize =
367 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
368
369 // Get stack alignments. The frame must be aligned to the greatest of these:
370 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
371 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
372 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
373
374 const PPCRegisterInfo *RegInfo =
375 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
376
377 // If we are a leaf function, and use up to 224 bytes of stack space,
378 // don't have a frame pointer, calls, or dynamic alloca then we do not need
379 // to adjust the stack pointer (we fit in the Red Zone).
380 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
381 // stackless code if all local vars are reg-allocated.
382 bool DisableRedZone = MF.getFunction()->getAttributes().
383 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
384 if (!DisableRedZone &&
385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
386 !Subtarget.isSVR4ABI() || // allocated locals.
387 FrameSize == 0) &&
388 FrameSize <= 224 && // Fits in red zone.
389 !MFI->hasVarSizedObjects() && // No dynamic alloca.
390 !MFI->adjustsStack() && // No calls.
391 !RegInfo->hasBasePointer(MF)) { // No special alignment.
392 // No need for frame
393 if (UpdateMF)
394 MFI->setStackSize(0);
395 return 0;
396 }
397
398 // Get the maximum call frame size of all the calls.
399 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
400
401 // Maximum call frame needs to be at least big enough for linkage area.
402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
403 Subtarget.isDarwinABI(),
404 Subtarget.isELFv2ABI());
405 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
406
407 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
408 // that allocations will be aligned.
409 if (MFI->hasVarSizedObjects())
410 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
411
412 // Update maximum call frame size.
413 if (UpdateMF)
414 MFI->setMaxCallFrameSize(maxCallFrameSize);
415
416 // Include call frame size in total.
417 FrameSize += maxCallFrameSize;
418
419 // Make sure the frame is aligned.
420 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
421
422 // Update frame info.
423 if (UpdateMF)
424 MFI->setStackSize(FrameSize);
425
426 return FrameSize;
427 }
428
429 // hasFP - Return true if the specified function actually has a dedicated frame
430 // pointer register.
hasFP(const MachineFunction & MF) const431 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
432 const MachineFrameInfo *MFI = MF.getFrameInfo();
433 // FIXME: This is pretty much broken by design: hasFP() might be called really
434 // early, before the stack layout was calculated and thus hasFP() might return
435 // true or false here depending on the time of call.
436 return (MFI->getStackSize()) && needsFP(MF);
437 }
438
439 // needsFP - Return true if the specified function should have a dedicated frame
440 // pointer register. This is true if the function has variable sized allocas or
441 // if frame pointer elimination is disabled.
needsFP(const MachineFunction & MF) const442 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
443 const MachineFrameInfo *MFI = MF.getFrameInfo();
444
445 // Naked functions have no stack frame pushed, so we don't have a frame
446 // pointer.
447 if (MF.getFunction()->getAttributes().hasAttribute(
448 AttributeSet::FunctionIndex, Attribute::Naked))
449 return false;
450
451 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
452 MFI->hasVarSizedObjects() ||
453 MFI->hasStackMap() || MFI->hasPatchPoint() ||
454 (MF.getTarget().Options.GuaranteedTailCallOpt &&
455 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
456 }
457
replaceFPWithRealFP(MachineFunction & MF) const458 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
459 bool is31 = needsFP(MF);
460 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
461 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
462
463 const PPCRegisterInfo *RegInfo =
464 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
465 bool HasBP = RegInfo->hasBasePointer(MF);
466 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
467 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
468
469 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
470 BI != BE; ++BI)
471 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
472 --MBBI;
473 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
474 MachineOperand &MO = MBBI->getOperand(I);
475 if (!MO.isReg())
476 continue;
477
478 switch (MO.getReg()) {
479 case PPC::FP:
480 MO.setReg(FPReg);
481 break;
482 case PPC::FP8:
483 MO.setReg(FP8Reg);
484 break;
485 case PPC::BP:
486 MO.setReg(BPReg);
487 break;
488 case PPC::BP8:
489 MO.setReg(BP8Reg);
490 break;
491
492 }
493 }
494 }
495 }
496
emitPrologue(MachineFunction & MF) const497 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
498 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
499 MachineBasicBlock::iterator MBBI = MBB.begin();
500 MachineFrameInfo *MFI = MF.getFrameInfo();
501 const PPCInstrInfo &TII =
502 *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
503 const PPCRegisterInfo *RegInfo =
504 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
505
506 MachineModuleInfo &MMI = MF.getMMI();
507 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
508 DebugLoc dl;
509 bool needsCFI = MMI.hasDebugInfo() ||
510 MF.getFunction()->needsUnwindTableEntry();
511 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
512
513 // Get processor type.
514 bool isPPC64 = Subtarget.isPPC64();
515 // Get the ABI.
516 bool isDarwinABI = Subtarget.isDarwinABI();
517 bool isSVR4ABI = Subtarget.isSVR4ABI();
518 bool isELFv2ABI = Subtarget.isELFv2ABI();
519 assert((isDarwinABI || isSVR4ABI) &&
520 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
521
522 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
523 // process it.
524 if (!isSVR4ABI)
525 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
526 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
527 HandleVRSaveUpdate(MBBI, TII);
528 break;
529 }
530 }
531
532 // Move MBBI back to the beginning of the function.
533 MBBI = MBB.begin();
534
535 // Work out frame sizes.
536 unsigned FrameSize = determineFrameLayout(MF);
537 int NegFrameSize = -FrameSize;
538 if (!isInt<32>(NegFrameSize))
539 llvm_unreachable("Unhandled stack size!");
540
541 if (MFI->isFrameAddressTaken())
542 replaceFPWithRealFP(MF);
543
544 // Check if the link register (LR) must be saved.
545 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
546 bool MustSaveLR = FI->mustSaveLR();
547 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
548 // Do we have a frame pointer and/or base pointer for this function?
549 bool HasFP = hasFP(MF);
550 bool HasBP = RegInfo->hasBasePointer(MF);
551
552 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
553 unsigned BPReg = RegInfo->getBaseRegister(MF);
554 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
555 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
556 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
557 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
558 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
559 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
560 : PPC::MFLR );
561 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
562 : PPC::STW );
563 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
564 : PPC::STWU );
565 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
566 : PPC::STWUX);
567 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
568 : PPC::LIS );
569 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
570 : PPC::ORI );
571 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
572 : PPC::OR );
573 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
574 : PPC::SUBFC);
575 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
576 : PPC::SUBFIC);
577
578 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
579 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
580 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
581 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
582 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
583 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
584
585 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
586
587 int FPOffset = 0;
588 if (HasFP) {
589 if (isSVR4ABI) {
590 MachineFrameInfo *FFI = MF.getFrameInfo();
591 int FPIndex = FI->getFramePointerSaveIndex();
592 assert(FPIndex && "No Frame Pointer Save Slot!");
593 FPOffset = FFI->getObjectOffset(FPIndex);
594 } else {
595 FPOffset =
596 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
597 }
598 }
599
600 int BPOffset = 0;
601 if (HasBP) {
602 if (isSVR4ABI) {
603 MachineFrameInfo *FFI = MF.getFrameInfo();
604 int BPIndex = FI->getBasePointerSaveIndex();
605 assert(BPIndex && "No Base Pointer Save Slot!");
606 BPOffset = FFI->getObjectOffset(BPIndex);
607 } else {
608 BPOffset =
609 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
610 isDarwinABI,
611 isPIC);
612 }
613 }
614
615 int PBPOffset = 0;
616 if (FI->usesPICBase()) {
617 MachineFrameInfo *FFI = MF.getFrameInfo();
618 int PBPIndex = FI->getPICBasePointerSaveIndex();
619 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
620 PBPOffset = FFI->getObjectOffset(PBPIndex);
621 }
622
623 // Get stack alignments.
624 unsigned MaxAlign = MFI->getMaxAlignment();
625 if (HasBP && MaxAlign > 1)
626 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
627 "Invalid alignment!");
628
629 // Frames of 32KB & larger require special handling because they cannot be
630 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
631 bool isLargeFrame = !isInt<16>(NegFrameSize);
632
633 if (MustSaveLR)
634 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
635
636 assert((isPPC64 || MustSaveCRs.empty()) &&
637 "Prologue CR saving supported only in 64-bit mode");
638
639 if (!MustSaveCRs.empty()) { // will only occur for PPC64
640 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
641 // If only one or two CR fields are clobbered, it could be more
642 // efficient to use mfocrf to selectively save just those fields.
643 MachineInstrBuilder MIB =
644 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
645 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
646 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
647 }
648
649 if (HasFP)
650 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
651 BuildMI(MBB, MBBI, dl, StoreInst)
652 .addReg(FPReg)
653 .addImm(FPOffset)
654 .addReg(SPReg);
655
656 if (FI->usesPICBase())
657 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
658 BuildMI(MBB, MBBI, dl, StoreInst)
659 .addReg(PPC::R30)
660 .addImm(PBPOffset)
661 .addReg(SPReg);
662
663 if (HasBP)
664 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
665 BuildMI(MBB, MBBI, dl, StoreInst)
666 .addReg(BPReg)
667 .addImm(BPOffset)
668 .addReg(SPReg);
669
670 if (MustSaveLR)
671 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
672 BuildMI(MBB, MBBI, dl, StoreInst)
673 .addReg(ScratchReg)
674 .addImm(LROffset)
675 .addReg(SPReg);
676
677 if (!MustSaveCRs.empty()) // will only occur for PPC64
678 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
679 .addReg(TempReg, getKillRegState(true))
680 .addImm(8)
681 .addReg(SPReg);
682
683 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
684 if (!FrameSize) return;
685
686 // Adjust stack pointer: r1 += NegFrameSize.
687 // If there is a preferred stack alignment, align R1 now
688
689 if (HasBP) {
690 // Save a copy of r1 as the base pointer.
691 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
692 .addReg(SPReg)
693 .addReg(SPReg);
694 }
695
696 if (HasBP && MaxAlign > 1) {
697 if (isPPC64)
698 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
699 .addReg(SPReg)
700 .addImm(0)
701 .addImm(64 - Log2_32(MaxAlign));
702 else // PPC32...
703 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
704 .addReg(SPReg)
705 .addImm(0)
706 .addImm(32 - Log2_32(MaxAlign))
707 .addImm(31);
708 if (!isLargeFrame) {
709 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
710 .addReg(ScratchReg, RegState::Kill)
711 .addImm(NegFrameSize);
712 } else {
713 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
714 .addImm(NegFrameSize >> 16);
715 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
716 .addReg(TempReg, RegState::Kill)
717 .addImm(NegFrameSize & 0xFFFF);
718 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
719 .addReg(ScratchReg, RegState::Kill)
720 .addReg(TempReg, RegState::Kill);
721 }
722 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
723 .addReg(SPReg, RegState::Kill)
724 .addReg(SPReg)
725 .addReg(ScratchReg);
726
727 } else if (!isLargeFrame) {
728 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
729 .addReg(SPReg)
730 .addImm(NegFrameSize)
731 .addReg(SPReg);
732
733 } else {
734 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
735 .addImm(NegFrameSize >> 16);
736 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
737 .addReg(ScratchReg, RegState::Kill)
738 .addImm(NegFrameSize & 0xFFFF);
739 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
740 .addReg(SPReg, RegState::Kill)
741 .addReg(SPReg)
742 .addReg(ScratchReg);
743 }
744
745 // Add Call Frame Information for the instructions we generated above.
746 if (needsCFI) {
747 unsigned CFIIndex;
748
749 if (HasBP) {
750 // Define CFA in terms of BP. Do this in preference to using FP/SP,
751 // because if the stack needed aligning then CFA won't be at a fixed
752 // offset from FP/SP.
753 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
754 CFIIndex = MMI.addFrameInst(
755 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
756 } else {
757 // Adjust the definition of CFA to account for the change in SP.
758 assert(NegFrameSize);
759 CFIIndex = MMI.addFrameInst(
760 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
761 }
762 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
763 .addCFIIndex(CFIIndex);
764
765 if (HasFP) {
766 // Describe where FP was saved, at a fixed offset from CFA.
767 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
768 CFIIndex = MMI.addFrameInst(
769 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
770 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
771 .addCFIIndex(CFIIndex);
772 }
773
774 if (FI->usesPICBase()) {
775 // Describe where FP was saved, at a fixed offset from CFA.
776 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
777 CFIIndex = MMI.addFrameInst(
778 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
779 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
780 .addCFIIndex(CFIIndex);
781 }
782
783 if (HasBP) {
784 // Describe where BP was saved, at a fixed offset from CFA.
785 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
786 CFIIndex = MMI.addFrameInst(
787 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
788 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
789 .addCFIIndex(CFIIndex);
790 }
791
792 if (MustSaveLR) {
793 // Describe where LR was saved, at a fixed offset from CFA.
794 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
795 CFIIndex = MMI.addFrameInst(
796 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
797 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
798 .addCFIIndex(CFIIndex);
799 }
800 }
801
802 // If there is a frame pointer, copy R1 into R31
803 if (HasFP) {
804 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
805 .addReg(SPReg)
806 .addReg(SPReg);
807
808 if (!HasBP && needsCFI) {
809 // Change the definition of CFA from SP+offset to FP+offset, because SP
810 // will change at every alloca.
811 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
812 unsigned CFIIndex = MMI.addFrameInst(
813 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
814
815 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
816 .addCFIIndex(CFIIndex);
817 }
818 }
819
820 if (needsCFI) {
821 // Describe where callee saved registers were saved, at fixed offsets from
822 // CFA.
823 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
824 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
825 unsigned Reg = CSI[I].getReg();
826 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
827
828 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
829 // subregisters of CR2. We just need to emit a move of CR2.
830 if (PPC::CRBITRCRegClass.contains(Reg))
831 continue;
832
833 // For SVR4, don't emit a move for the CR spill slot if we haven't
834 // spilled CRs.
835 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
836 && MustSaveCRs.empty())
837 continue;
838
839 // For 64-bit SVR4 when we have spilled CRs, the spill location
840 // is SP+8, not a frame-relative slot.
841 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
842 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
843 // the whole CR word. In the ELFv2 ABI, every CR that was
844 // actually saved gets its own CFI record.
845 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
846 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
847 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
848 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
849 .addCFIIndex(CFIIndex);
850 continue;
851 }
852
853 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
854 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
855 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
856 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
857 .addCFIIndex(CFIIndex);
858 }
859 }
860 }
861
emitEpilogue(MachineFunction & MF,MachineBasicBlock & MBB) const862 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
863 MachineBasicBlock &MBB) const {
864 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
865 assert(MBBI != MBB.end() && "Returning block has no terminator");
866 const PPCInstrInfo &TII =
867 *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
868 const PPCRegisterInfo *RegInfo =
869 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
870
871 unsigned RetOpcode = MBBI->getOpcode();
872 DebugLoc dl;
873
874 assert((RetOpcode == PPC::BLR ||
875 RetOpcode == PPC::BLR8 ||
876 RetOpcode == PPC::TCRETURNri ||
877 RetOpcode == PPC::TCRETURNdi ||
878 RetOpcode == PPC::TCRETURNai ||
879 RetOpcode == PPC::TCRETURNri8 ||
880 RetOpcode == PPC::TCRETURNdi8 ||
881 RetOpcode == PPC::TCRETURNai8) &&
882 "Can only insert epilog into returning blocks");
883
884 // Get alignment info so we know how to restore the SP.
885 const MachineFrameInfo *MFI = MF.getFrameInfo();
886
887 // Get the number of bytes allocated from the FrameInfo.
888 int FrameSize = MFI->getStackSize();
889
890 // Get processor type.
891 bool isPPC64 = Subtarget.isPPC64();
892 // Get the ABI.
893 bool isDarwinABI = Subtarget.isDarwinABI();
894 bool isSVR4ABI = Subtarget.isSVR4ABI();
895 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
896
897 // Check if the link register (LR) has been saved.
898 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
899 bool MustSaveLR = FI->mustSaveLR();
900 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
901 // Do we have a frame pointer and/or base pointer for this function?
902 bool HasFP = hasFP(MF);
903 bool HasBP = RegInfo->hasBasePointer(MF);
904
905 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
906 unsigned BPReg = RegInfo->getBaseRegister(MF);
907 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
908 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
909 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
910 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
911 : PPC::MTLR );
912 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
913 : PPC::LWZ );
914 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
915 : PPC::LIS );
916 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
917 : PPC::ORI );
918 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
919 : PPC::ADDI );
920 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
921 : PPC::ADD4 );
922
923 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
924
925 int FPOffset = 0;
926 if (HasFP) {
927 if (isSVR4ABI) {
928 MachineFrameInfo *FFI = MF.getFrameInfo();
929 int FPIndex = FI->getFramePointerSaveIndex();
930 assert(FPIndex && "No Frame Pointer Save Slot!");
931 FPOffset = FFI->getObjectOffset(FPIndex);
932 } else {
933 FPOffset =
934 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
935 }
936 }
937
938 int BPOffset = 0;
939 if (HasBP) {
940 if (isSVR4ABI) {
941 MachineFrameInfo *FFI = MF.getFrameInfo();
942 int BPIndex = FI->getBasePointerSaveIndex();
943 assert(BPIndex && "No Base Pointer Save Slot!");
944 BPOffset = FFI->getObjectOffset(BPIndex);
945 } else {
946 BPOffset =
947 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
948 isDarwinABI,
949 isPIC);
950 }
951 }
952
953 int PBPOffset = 0;
954 if (FI->usesPICBase()) {
955 MachineFrameInfo *FFI = MF.getFrameInfo();
956 int PBPIndex = FI->getPICBasePointerSaveIndex();
957 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
958 PBPOffset = FFI->getObjectOffset(PBPIndex);
959 }
960
961 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
962 RetOpcode == PPC::TCRETURNdi ||
963 RetOpcode == PPC::TCRETURNai ||
964 RetOpcode == PPC::TCRETURNri8 ||
965 RetOpcode == PPC::TCRETURNdi8 ||
966 RetOpcode == PPC::TCRETURNai8;
967
968 if (UsesTCRet) {
969 int MaxTCRetDelta = FI->getTailCallSPDelta();
970 MachineOperand &StackAdjust = MBBI->getOperand(1);
971 assert(StackAdjust.isImm() && "Expecting immediate value.");
972 // Adjust stack pointer.
973 int StackAdj = StackAdjust.getImm();
974 int Delta = StackAdj - MaxTCRetDelta;
975 assert((Delta >= 0) && "Delta must be positive");
976 if (MaxTCRetDelta>0)
977 FrameSize += (StackAdj +Delta);
978 else
979 FrameSize += StackAdj;
980 }
981
982 // Frames of 32KB & larger require special handling because they cannot be
983 // indexed into with a simple LD/LWZ immediate offset operand.
984 bool isLargeFrame = !isInt<16>(FrameSize);
985
986 if (FrameSize) {
987 // In the prologue, the loaded (or persistent) stack pointer value is offset
988 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
989
990 // If this function contained a fastcc call and GuaranteedTailCallOpt is
991 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
992 // call which invalidates the stack pointer value in SP(0). So we use the
993 // value of R31 in this case.
994 if (FI->hasFastCall()) {
995 assert(HasFP && "Expecting a valid frame pointer.");
996 if (!isLargeFrame) {
997 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
998 .addReg(FPReg).addImm(FrameSize);
999 } else {
1000 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1001 .addImm(FrameSize >> 16);
1002 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1003 .addReg(ScratchReg, RegState::Kill)
1004 .addImm(FrameSize & 0xFFFF);
1005 BuildMI(MBB, MBBI, dl, AddInst)
1006 .addReg(SPReg)
1007 .addReg(FPReg)
1008 .addReg(ScratchReg);
1009 }
1010 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1011 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1012 .addReg(SPReg)
1013 .addImm(FrameSize);
1014 } else {
1015 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1016 .addImm(0)
1017 .addReg(SPReg);
1018 }
1019
1020 }
1021
1022 if (MustSaveLR)
1023 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1024 .addImm(LROffset)
1025 .addReg(SPReg);
1026
1027 assert((isPPC64 || MustSaveCRs.empty()) &&
1028 "Epilogue CR restoring supported only in 64-bit mode");
1029
1030 if (!MustSaveCRs.empty()) // will only occur for PPC64
1031 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1032 .addImm(8)
1033 .addReg(SPReg);
1034
1035 if (HasFP)
1036 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1037 .addImm(FPOffset)
1038 .addReg(SPReg);
1039
1040 if (FI->usesPICBase())
1041 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1042 BuildMI(MBB, MBBI, dl, LoadInst)
1043 .addReg(PPC::R30)
1044 .addImm(PBPOffset)
1045 .addReg(SPReg);
1046
1047 if (HasBP)
1048 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1049 .addImm(BPOffset)
1050 .addReg(SPReg);
1051
1052 if (!MustSaveCRs.empty()) // will only occur for PPC64
1053 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1054 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1055 .addReg(TempReg, getKillRegState(i == e-1));
1056
1057 if (MustSaveLR)
1058 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1059
1060 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1061 // call optimization
1062 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1063 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1064 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1065 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1066 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1067
1068 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1069 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1070 .addReg(SPReg).addImm(CallerAllocatedAmt);
1071 } else {
1072 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1073 .addImm(CallerAllocatedAmt >> 16);
1074 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1075 .addReg(ScratchReg, RegState::Kill)
1076 .addImm(CallerAllocatedAmt & 0xFFFF);
1077 BuildMI(MBB, MBBI, dl, AddInst)
1078 .addReg(SPReg)
1079 .addReg(FPReg)
1080 .addReg(ScratchReg);
1081 }
1082 } else if (RetOpcode == PPC::TCRETURNdi) {
1083 MBBI = MBB.getLastNonDebugInstr();
1084 MachineOperand &JumpTarget = MBBI->getOperand(0);
1085 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1086 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1087 } else if (RetOpcode == PPC::TCRETURNri) {
1088 MBBI = MBB.getLastNonDebugInstr();
1089 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1090 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1091 } else if (RetOpcode == PPC::TCRETURNai) {
1092 MBBI = MBB.getLastNonDebugInstr();
1093 MachineOperand &JumpTarget = MBBI->getOperand(0);
1094 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1095 } else if (RetOpcode == PPC::TCRETURNdi8) {
1096 MBBI = MBB.getLastNonDebugInstr();
1097 MachineOperand &JumpTarget = MBBI->getOperand(0);
1098 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1099 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1100 } else if (RetOpcode == PPC::TCRETURNri8) {
1101 MBBI = MBB.getLastNonDebugInstr();
1102 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1103 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1104 } else if (RetOpcode == PPC::TCRETURNai8) {
1105 MBBI = MBB.getLastNonDebugInstr();
1106 MachineOperand &JumpTarget = MBBI->getOperand(0);
1107 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1108 }
1109 }
1110
1111 /// MustSaveLR - Return true if this function requires that we save the LR
1112 /// register onto the stack in the prolog and restore it in the epilog of the
1113 /// function.
MustSaveLR(const MachineFunction & MF,unsigned LR)1114 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
1115 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
1116
1117 // We need a save/restore of LR if there is any def of LR (which is
1118 // defined by calls, including the PIC setup sequence), or if there is
1119 // some use of the LR stack slot (e.g. for builtin_return_address).
1120 // (LR comes in 32 and 64 bit versions.)
1121 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
1122 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
1123 }
1124
1125 void
processFunctionBeforeCalleeSavedScan(MachineFunction & MF,RegScavenger *) const1126 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1127 RegScavenger *) const {
1128 const PPCRegisterInfo *RegInfo =
1129 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1130
1131 // Save and clear the LR state.
1132 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1133 unsigned LR = RegInfo->getRARegister();
1134 FI->setMustSaveLR(MustSaveLR(MF, LR));
1135 MachineRegisterInfo &MRI = MF.getRegInfo();
1136 MRI.setPhysRegUnused(LR);
1137
1138 // Save R31 if necessary
1139 int FPSI = FI->getFramePointerSaveIndex();
1140 bool isPPC64 = Subtarget.isPPC64();
1141 bool isDarwinABI = Subtarget.isDarwinABI();
1142 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
1143 MachineFrameInfo *MFI = MF.getFrameInfo();
1144
1145 // If the frame pointer save index hasn't been defined yet.
1146 if (!FPSI && needsFP(MF)) {
1147 // Find out what the fix offset of the frame pointer save area.
1148 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
1149 // Allocate the frame index for frame pointer save area.
1150 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1151 // Save the result.
1152 FI->setFramePointerSaveIndex(FPSI);
1153 }
1154
1155 int BPSI = FI->getBasePointerSaveIndex();
1156 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1157 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
1158 // Allocate the frame index for the base pointer save area.
1159 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1160 // Save the result.
1161 FI->setBasePointerSaveIndex(BPSI);
1162 }
1163
1164 // Reserve stack space for the PIC Base register (R30).
1165 // Only used in SVR4 32-bit.
1166 if (FI->usesPICBase()) {
1167 int PBPSI = FI->getPICBasePointerSaveIndex();
1168 PBPSI = MFI->CreateFixedObject(4, -8, true);
1169 FI->setPICBasePointerSaveIndex(PBPSI);
1170 }
1171
1172 // Reserve stack space to move the linkage area to in case of a tail call.
1173 int TCSPDelta = 0;
1174 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1175 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1176 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1177 }
1178
1179 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1180 // function uses CR 2, 3, or 4.
1181 if (!isPPC64 && !isDarwinABI &&
1182 (MRI.isPhysRegUsed(PPC::CR2) ||
1183 MRI.isPhysRegUsed(PPC::CR3) ||
1184 MRI.isPhysRegUsed(PPC::CR4))) {
1185 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1186 FI->setCRSpillFrameIndex(FrameIdx);
1187 }
1188 }
1189
processFunctionBeforeFrameFinalized(MachineFunction & MF,RegScavenger * RS) const1190 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1191 RegScavenger *RS) const {
1192 // Early exit if not using the SVR4 ABI.
1193 if (!Subtarget.isSVR4ABI()) {
1194 addScavengingSpillSlot(MF, RS);
1195 return;
1196 }
1197
1198 // Get callee saved register information.
1199 MachineFrameInfo *FFI = MF.getFrameInfo();
1200 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1201
1202 // Early exit if no callee saved registers are modified!
1203 if (CSI.empty() && !needsFP(MF)) {
1204 addScavengingSpillSlot(MF, RS);
1205 return;
1206 }
1207
1208 unsigned MinGPR = PPC::R31;
1209 unsigned MinG8R = PPC::X31;
1210 unsigned MinFPR = PPC::F31;
1211 unsigned MinVR = PPC::V31;
1212
1213 bool HasGPSaveArea = false;
1214 bool HasG8SaveArea = false;
1215 bool HasFPSaveArea = false;
1216 bool HasVRSAVESaveArea = false;
1217 bool HasVRSaveArea = false;
1218
1219 SmallVector<CalleeSavedInfo, 18> GPRegs;
1220 SmallVector<CalleeSavedInfo, 18> G8Regs;
1221 SmallVector<CalleeSavedInfo, 18> FPRegs;
1222 SmallVector<CalleeSavedInfo, 18> VRegs;
1223
1224 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1225 unsigned Reg = CSI[i].getReg();
1226 if (PPC::GPRCRegClass.contains(Reg)) {
1227 HasGPSaveArea = true;
1228
1229 GPRegs.push_back(CSI[i]);
1230
1231 if (Reg < MinGPR) {
1232 MinGPR = Reg;
1233 }
1234 } else if (PPC::G8RCRegClass.contains(Reg)) {
1235 HasG8SaveArea = true;
1236
1237 G8Regs.push_back(CSI[i]);
1238
1239 if (Reg < MinG8R) {
1240 MinG8R = Reg;
1241 }
1242 } else if (PPC::F8RCRegClass.contains(Reg)) {
1243 HasFPSaveArea = true;
1244
1245 FPRegs.push_back(CSI[i]);
1246
1247 if (Reg < MinFPR) {
1248 MinFPR = Reg;
1249 }
1250 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1251 PPC::CRRCRegClass.contains(Reg)) {
1252 ; // do nothing, as we already know whether CRs are spilled
1253 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1254 HasVRSAVESaveArea = true;
1255 } else if (PPC::VRRCRegClass.contains(Reg)) {
1256 HasVRSaveArea = true;
1257
1258 VRegs.push_back(CSI[i]);
1259
1260 if (Reg < MinVR) {
1261 MinVR = Reg;
1262 }
1263 } else {
1264 llvm_unreachable("Unknown RegisterClass!");
1265 }
1266 }
1267
1268 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1269 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1270
1271 int64_t LowerBound = 0;
1272
1273 // Take into account stack space reserved for tail calls.
1274 int TCSPDelta = 0;
1275 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1276 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1277 LowerBound = TCSPDelta;
1278 }
1279
1280 // The Floating-point register save area is right below the back chain word
1281 // of the previous stack frame.
1282 if (HasFPSaveArea) {
1283 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1284 int FI = FPRegs[i].getFrameIdx();
1285
1286 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1287 }
1288
1289 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1290 }
1291
1292 // Check whether the frame pointer register is allocated. If so, make sure it
1293 // is spilled to the correct offset.
1294 if (needsFP(MF)) {
1295 HasGPSaveArea = true;
1296
1297 int FI = PFI->getFramePointerSaveIndex();
1298 assert(FI && "No Frame Pointer Save Slot!");
1299
1300 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1301 }
1302
1303 if (PFI->usesPICBase()) {
1304 HasGPSaveArea = true;
1305
1306 int FI = PFI->getPICBasePointerSaveIndex();
1307 assert(FI && "No PIC Base Pointer Save Slot!");
1308
1309 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1310 }
1311
1312 const PPCRegisterInfo *RegInfo =
1313 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1314 if (RegInfo->hasBasePointer(MF)) {
1315 HasGPSaveArea = true;
1316
1317 int FI = PFI->getBasePointerSaveIndex();
1318 assert(FI && "No Base Pointer Save Slot!");
1319
1320 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1321 }
1322
1323 // General register save area starts right below the Floating-point
1324 // register save area.
1325 if (HasGPSaveArea || HasG8SaveArea) {
1326 // Move general register save area spill slots down, taking into account
1327 // the size of the Floating-point register save area.
1328 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1329 int FI = GPRegs[i].getFrameIdx();
1330
1331 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1332 }
1333
1334 // Move general register save area spill slots down, taking into account
1335 // the size of the Floating-point register save area.
1336 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1337 int FI = G8Regs[i].getFrameIdx();
1338
1339 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1340 }
1341
1342 unsigned MinReg =
1343 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1344 TRI->getEncodingValue(MinG8R));
1345
1346 if (Subtarget.isPPC64()) {
1347 LowerBound -= (31 - MinReg + 1) * 8;
1348 } else {
1349 LowerBound -= (31 - MinReg + 1) * 4;
1350 }
1351 }
1352
1353 // For 32-bit only, the CR save area is below the general register
1354 // save area. For 64-bit SVR4, the CR save area is addressed relative
1355 // to the stack pointer and hence does not need an adjustment here.
1356 // Only CR2 (the first nonvolatile spilled) has an associated frame
1357 // index so that we have a single uniform save area.
1358 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1359 // Adjust the frame index of the CR spill slot.
1360 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1361 unsigned Reg = CSI[i].getReg();
1362
1363 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1364 // Leave Darwin logic as-is.
1365 || (!Subtarget.isSVR4ABI() &&
1366 (PPC::CRBITRCRegClass.contains(Reg) ||
1367 PPC::CRRCRegClass.contains(Reg)))) {
1368 int FI = CSI[i].getFrameIdx();
1369
1370 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1371 }
1372 }
1373
1374 LowerBound -= 4; // The CR save area is always 4 bytes long.
1375 }
1376
1377 if (HasVRSAVESaveArea) {
1378 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1379 // which have the VRSAVE register class?
1380 // Adjust the frame index of the VRSAVE spill slot.
1381 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1382 unsigned Reg = CSI[i].getReg();
1383
1384 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1385 int FI = CSI[i].getFrameIdx();
1386
1387 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1388 }
1389 }
1390
1391 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1392 }
1393
1394 if (HasVRSaveArea) {
1395 // Insert alignment padding, we need 16-byte alignment.
1396 LowerBound = (LowerBound - 15) & ~(15);
1397
1398 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1399 int FI = VRegs[i].getFrameIdx();
1400
1401 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1402 }
1403 }
1404
1405 addScavengingSpillSlot(MF, RS);
1406 }
1407
1408 void
addScavengingSpillSlot(MachineFunction & MF,RegScavenger * RS) const1409 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1410 RegScavenger *RS) const {
1411 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1412 // a large stack, which will require scavenging a register to materialize a
1413 // large offset.
1414
1415 // We need to have a scavenger spill slot for spills if the frame size is
1416 // large. In case there is no free register for large-offset addressing,
1417 // this slot is used for the necessary emergency spill. Also, we need the
1418 // slot for dynamic stack allocations.
1419
1420 // The scavenger might be invoked if the frame offset does not fit into
1421 // the 16-bit immediate. We don't know the complete frame size here
1422 // because we've not yet computed callee-saved register spills or the
1423 // needed alignment padding.
1424 unsigned StackSize = determineFrameLayout(MF, false, true);
1425 MachineFrameInfo *MFI = MF.getFrameInfo();
1426 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1427 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1428 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1429 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1430 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1431 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1432 RC->getAlignment(),
1433 false));
1434
1435 // Might we have over-aligned allocas?
1436 bool HasAlVars = MFI->hasVarSizedObjects() &&
1437 MFI->getMaxAlignment() > getStackAlignment();
1438
1439 // These kinds of spills might need two registers.
1440 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1441 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1442 RC->getAlignment(),
1443 false));
1444
1445 }
1446 }
1447
1448 bool
spillCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const1449 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1450 MachineBasicBlock::iterator MI,
1451 const std::vector<CalleeSavedInfo> &CSI,
1452 const TargetRegisterInfo *TRI) const {
1453
1454 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1455 // Return false otherwise to maintain pre-existing behavior.
1456 if (!Subtarget.isSVR4ABI())
1457 return false;
1458
1459 MachineFunction *MF = MBB.getParent();
1460 const PPCInstrInfo &TII =
1461 *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1462 DebugLoc DL;
1463 bool CRSpilled = false;
1464 MachineInstrBuilder CRMIB;
1465
1466 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1467 unsigned Reg = CSI[i].getReg();
1468 // Only Darwin actually uses the VRSAVE register, but it can still appear
1469 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1470 // Darwin, ignore it.
1471 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1472 continue;
1473
1474 // CR2 through CR4 are the nonvolatile CR fields.
1475 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1476
1477 // Add the callee-saved register as live-in; it's killed at the spill.
1478 MBB.addLiveIn(Reg);
1479
1480 if (CRSpilled && IsCRField) {
1481 CRMIB.addReg(Reg, RegState::ImplicitKill);
1482 continue;
1483 }
1484
1485 // Insert the spill to the stack frame.
1486 if (IsCRField) {
1487 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1488 if (Subtarget.isPPC64()) {
1489 // The actual spill will happen at the start of the prologue.
1490 FuncInfo->addMustSaveCR(Reg);
1491 } else {
1492 CRSpilled = true;
1493 FuncInfo->setSpillsCR();
1494
1495 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1496 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1497 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1498 .addReg(Reg, RegState::ImplicitKill);
1499
1500 MBB.insert(MI, CRMIB);
1501 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1502 .addReg(PPC::R12,
1503 getKillRegState(true)),
1504 CSI[i].getFrameIdx()));
1505 }
1506 } else {
1507 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1508 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1509 CSI[i].getFrameIdx(), RC, TRI);
1510 }
1511 }
1512 return true;
1513 }
1514
1515 static void
restoreCRs(bool isPPC64,bool is31,bool CR2Spilled,bool CR3Spilled,bool CR4Spilled,MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,unsigned CSIIndex)1516 restoreCRs(bool isPPC64, bool is31,
1517 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1518 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1519 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1520
1521 MachineFunction *MF = MBB.getParent();
1522 const PPCInstrInfo &TII =
1523 *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1524 DebugLoc DL;
1525 unsigned RestoreOp, MoveReg;
1526
1527 if (isPPC64)
1528 // This is handled during epilogue generation.
1529 return;
1530 else {
1531 // 32-bit: FP-relative
1532 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1533 PPC::R12),
1534 CSI[CSIIndex].getFrameIdx()));
1535 RestoreOp = PPC::MTOCRF;
1536 MoveReg = PPC::R12;
1537 }
1538
1539 if (CR2Spilled)
1540 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1541 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1542
1543 if (CR3Spilled)
1544 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1545 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1546
1547 if (CR4Spilled)
1548 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1549 .addReg(MoveReg, getKillRegState(true)));
1550 }
1551
1552 void PPCFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const1553 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1554 MachineBasicBlock::iterator I) const {
1555 const PPCInstrInfo &TII =
1556 *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
1557 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1558 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1559 // Add (actually subtract) back the amount the callee popped on return.
1560 if (int CalleeAmt = I->getOperand(1).getImm()) {
1561 bool is64Bit = Subtarget.isPPC64();
1562 CalleeAmt *= -1;
1563 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1564 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1565 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1566 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1567 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1568 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1569 MachineInstr *MI = I;
1570 DebugLoc dl = MI->getDebugLoc();
1571
1572 if (isInt<16>(CalleeAmt)) {
1573 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1574 .addReg(StackReg, RegState::Kill)
1575 .addImm(CalleeAmt);
1576 } else {
1577 MachineBasicBlock::iterator MBBI = I;
1578 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1579 .addImm(CalleeAmt >> 16);
1580 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1581 .addReg(TmpReg, RegState::Kill)
1582 .addImm(CalleeAmt & 0xFFFF);
1583 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1584 .addReg(StackReg, RegState::Kill)
1585 .addReg(TmpReg);
1586 }
1587 }
1588 }
1589 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1590 MBB.erase(I);
1591 }
1592
1593 bool
restoreCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const1594 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1595 MachineBasicBlock::iterator MI,
1596 const std::vector<CalleeSavedInfo> &CSI,
1597 const TargetRegisterInfo *TRI) const {
1598
1599 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1600 // Return false otherwise to maintain pre-existing behavior.
1601 if (!Subtarget.isSVR4ABI())
1602 return false;
1603
1604 MachineFunction *MF = MBB.getParent();
1605 const PPCInstrInfo &TII =
1606 *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1607 bool CR2Spilled = false;
1608 bool CR3Spilled = false;
1609 bool CR4Spilled = false;
1610 unsigned CSIIndex = 0;
1611
1612 // Initialize insertion-point logic; we will be restoring in reverse
1613 // order of spill.
1614 MachineBasicBlock::iterator I = MI, BeforeI = I;
1615 bool AtStart = I == MBB.begin();
1616
1617 if (!AtStart)
1618 --BeforeI;
1619
1620 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1621 unsigned Reg = CSI[i].getReg();
1622
1623 // Only Darwin actually uses the VRSAVE register, but it can still appear
1624 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1625 // Darwin, ignore it.
1626 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1627 continue;
1628
1629 if (Reg == PPC::CR2) {
1630 CR2Spilled = true;
1631 // The spill slot is associated only with CR2, which is the
1632 // first nonvolatile spilled. Save it here.
1633 CSIIndex = i;
1634 continue;
1635 } else if (Reg == PPC::CR3) {
1636 CR3Spilled = true;
1637 continue;
1638 } else if (Reg == PPC::CR4) {
1639 CR4Spilled = true;
1640 continue;
1641 } else {
1642 // When we first encounter a non-CR register after seeing at
1643 // least one CR register, restore all spilled CRs together.
1644 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1645 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1646 bool is31 = needsFP(*MF);
1647 restoreCRs(Subtarget.isPPC64(), is31,
1648 CR2Spilled, CR3Spilled, CR4Spilled,
1649 MBB, I, CSI, CSIIndex);
1650 CR2Spilled = CR3Spilled = CR4Spilled = false;
1651 }
1652
1653 // Default behavior for non-CR saves.
1654 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1655 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1656 RC, TRI);
1657 assert(I != MBB.begin() &&
1658 "loadRegFromStackSlot didn't insert any code!");
1659 }
1660
1661 // Insert in reverse order.
1662 if (AtStart)
1663 I = MBB.begin();
1664 else {
1665 I = BeforeI;
1666 ++I;
1667 }
1668 }
1669
1670 // If we haven't yet spilled the CRs, do so now.
1671 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1672 bool is31 = needsFP(*MF);
1673 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1674 MBB, I, CSI, CSIIndex);
1675 }
1676
1677 return true;
1678 }
1679