1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363 364// 1.7.6 X-Form 365class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 366 InstrItinClass itin, list<dag> pattern> 367 : I<opcode, OOL, IOL, asmstr, itin> { 368 bits<5> RST; 369 bits<5> A; 370 bits<5> B; 371 372 let Pattern = pattern; 373 374 bit RC = 0; // set by isDOT 375 376 let Inst{6-10} = RST; 377 let Inst{11-15} = A; 378 let Inst{16-20} = B; 379 let Inst{21-30} = xo; 380 let Inst{31} = RC; 381} 382 383class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 385 let RST = 0; 386} 387 388class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 389 InstrItinClass itin> 390 : I<opcode, OOL, IOL, asmstr, itin> { 391 let Inst{21-30} = xo; 392} 393 394// This is the same as XForm_base_r3xo, but the first two operands are swapped 395// when code is emitted. 396class XForm_base_r3xo_swapped 397 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 398 InstrItinClass itin> 399 : I<opcode, OOL, IOL, asmstr, itin> { 400 bits<5> A; 401 bits<5> RST; 402 bits<5> B; 403 404 bit RC = 0; // set by isDOT 405 406 let Inst{6-10} = RST; 407 let Inst{11-15} = A; 408 let Inst{16-20} = B; 409 let Inst{21-30} = xo; 410 let Inst{31} = RC; 411} 412 413 414class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 415 InstrItinClass itin, list<dag> pattern> 416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 417 418class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 419 InstrItinClass itin, list<dag> pattern> 420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 421 let RST = 0; 422} 423 424class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 425 InstrItinClass itin, list<dag> pattern> 426 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 427 let A = 0; 428 let B = 0; 429} 430 431class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 432 InstrItinClass itin, list<dag> pattern> 433 : I<opcode, OOL, IOL, asmstr, itin> { 434 bits<5> RST; 435 bits<5> A; 436 bits<1> WS; 437 438 let Pattern = pattern; 439 440 let Inst{6-10} = RST; 441 let Inst{11-15} = A; 442 let Inst{20} = WS; 443 let Inst{21-30} = xo; 444 let Inst{31} = 0; 445} 446 447class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 448 InstrItinClass itin, list<dag> pattern> 449 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 450 let Pattern = pattern; 451} 452 453class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 454 InstrItinClass itin, list<dag> pattern> 455 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 456 457class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 458 InstrItinClass itin, list<dag> pattern> 459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 460 let Pattern = pattern; 461} 462 463class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 464 InstrItinClass itin, list<dag> pattern> 465 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 466 let B = 0; 467 let Pattern = pattern; 468} 469 470class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 471 InstrItinClass itin> 472 : I<opcode, OOL, IOL, asmstr, itin> { 473 bits<3> BF; 474 bits<1> L; 475 bits<5> RA; 476 bits<5> RB; 477 478 let Inst{6-8} = BF; 479 let Inst{9} = 0; 480 let Inst{10} = L; 481 let Inst{11-15} = RA; 482 let Inst{16-20} = RB; 483 let Inst{21-30} = xo; 484 let Inst{31} = 0; 485} 486 487class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 488 InstrItinClass itin> 489 : I<opcode, OOL, IOL, asmstr, itin> { 490 bits<4> CT; 491 bits<5> RA; 492 bits<5> RB; 493 494 let Inst{6} = 0; 495 let Inst{7-10} = CT; 496 let Inst{11-15} = RA; 497 let Inst{16-20} = RB; 498 let Inst{21-30} = xo; 499 let Inst{31} = 0; 500} 501 502class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 503 InstrItinClass itin> 504 : I<opcode, OOL, IOL, asmstr, itin> { 505 bits<5> RS; 506 bits<4> SR; 507 508 let Inst{6-10} = RS; 509 let Inst{12-15} = SR; 510 let Inst{21-30} = xo; 511} 512 513class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 514 InstrItinClass itin> 515 : I<opcode, OOL, IOL, asmstr, itin> { 516 bits<5> MO; 517 518 let Inst{6-10} = MO; 519 let Inst{21-30} = xo; 520} 521 522class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 523 InstrItinClass itin> 524 : I<opcode, OOL, IOL, asmstr, itin> { 525 bits<5> RS; 526 bits<5> RB; 527 528 let Inst{6-10} = RS; 529 let Inst{16-20} = RB; 530 let Inst{21-30} = xo; 531} 532 533class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 534 InstrItinClass itin> 535 : I<opcode, OOL, IOL, asmstr, itin> { 536 bits<5> RS; 537 bits<1> L; 538 539 let Inst{6-10} = RS; 540 let Inst{15} = L; 541 let Inst{21-30} = xo; 542} 543 544class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin> 546 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 547 let L = PPC64; 548} 549 550class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 551 InstrItinClass itin> 552 : I<opcode, OOL, IOL, asmstr, itin> { 553 bits<3> BF; 554 bits<5> FRA; 555 bits<5> FRB; 556 557 let Inst{6-8} = BF; 558 let Inst{9-10} = 0; 559 let Inst{11-15} = FRA; 560 let Inst{16-20} = FRB; 561 let Inst{21-30} = xo; 562 let Inst{31} = 0; 563} 564 565class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 566 InstrItinClass itin, list<dag> pattern> 567 : I<opcode, OOL, IOL, asmstr, itin> { 568 let Pattern = pattern; 569 let Inst{6-10} = 31; 570 let Inst{11-15} = 0; 571 let Inst{16-20} = 0; 572 let Inst{21-30} = xo; 573 let Inst{31} = 0; 574} 575 576class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 577 string asmstr, InstrItinClass itin, list<dag> pattern> 578 : I<opcode, OOL, IOL, asmstr, itin> { 579 bits<2> L; 580 581 let Pattern = pattern; 582 let Inst{6-8} = 0; 583 let Inst{9-10} = L; 584 let Inst{11-15} = 0; 585 let Inst{16-20} = 0; 586 let Inst{21-30} = xo; 587 let Inst{31} = 0; 588} 589 590class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 591 string asmstr, InstrItinClass itin, list<dag> pattern> 592 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 593 let L = 0; 594} 595 596class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 597 InstrItinClass itin, list<dag> pattern> 598 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 599} 600 601class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 602 InstrItinClass itin, list<dag> pattern> 603 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 604 let A = 0; 605} 606 607class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 608 InstrItinClass itin, list<dag> pattern> 609 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 610} 611 612// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 613// numbers presumably relates to some document, but I haven't found it. 614class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 615 InstrItinClass itin, list<dag> pattern> 616 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 617 let Pattern = pattern; 618 619 bit RC = 0; // set by isDOT 620 621 let Inst{6-10} = RST; 622 let Inst{11-20} = 0; 623 let Inst{21-30} = xo; 624 let Inst{31} = RC; 625} 626class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 627 InstrItinClass itin, list<dag> pattern> 628 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 629 let Pattern = pattern; 630 bits<5> FM; 631 632 bit RC = 0; // set by isDOT 633 634 let Inst{6-10} = FM; 635 let Inst{11-20} = 0; 636 let Inst{21-30} = xo; 637 let Inst{31} = RC; 638} 639 640class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 641 InstrItinClass itin, list<dag> pattern> 642 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 643 let RST = 0; 644 let A = 0; 645 let B = 0; 646} 647 648class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 649 InstrItinClass itin, list<dag> pattern> 650 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 651 let RST = 0; 652 let A = 0; 653} 654 655// XX*-Form (VSX) 656class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 657 InstrItinClass itin, list<dag> pattern> 658 : I<opcode, OOL, IOL, asmstr, itin> { 659 bits<6> XT; 660 bits<5> A; 661 bits<5> B; 662 663 let Pattern = pattern; 664 665 let Inst{6-10} = XT{4-0}; 666 let Inst{11-15} = A; 667 let Inst{16-20} = B; 668 let Inst{21-30} = xo; 669 let Inst{31} = XT{5}; 670} 671 672class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 673 InstrItinClass itin, list<dag> pattern> 674 : I<opcode, OOL, IOL, asmstr, itin> { 675 bits<6> XT; 676 bits<6> XB; 677 678 let Pattern = pattern; 679 680 let Inst{6-10} = XT{4-0}; 681 let Inst{11-15} = 0; 682 let Inst{16-20} = XB{4-0}; 683 let Inst{21-29} = xo; 684 let Inst{30} = XB{5}; 685 let Inst{31} = XT{5}; 686} 687 688class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 689 InstrItinClass itin, list<dag> pattern> 690 : I<opcode, OOL, IOL, asmstr, itin> { 691 bits<3> CR; 692 bits<6> XB; 693 694 let Pattern = pattern; 695 696 let Inst{6-8} = CR; 697 let Inst{9-15} = 0; 698 let Inst{16-20} = XB{4-0}; 699 let Inst{21-29} = xo; 700 let Inst{30} = XB{5}; 701 let Inst{31} = 0; 702} 703 704class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 705 InstrItinClass itin, list<dag> pattern> 706 : I<opcode, OOL, IOL, asmstr, itin> { 707 bits<6> XT; 708 bits<6> XB; 709 bits<2> D; 710 711 let Pattern = pattern; 712 713 let Inst{6-10} = XT{4-0}; 714 let Inst{11-13} = 0; 715 let Inst{14-15} = D; 716 let Inst{16-20} = XB{4-0}; 717 let Inst{21-29} = xo; 718 let Inst{30} = XB{5}; 719 let Inst{31} = XT{5}; 720} 721 722class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 723 InstrItinClass itin, list<dag> pattern> 724 : I<opcode, OOL, IOL, asmstr, itin> { 725 bits<6> XT; 726 bits<6> XA; 727 bits<6> XB; 728 729 let Pattern = pattern; 730 731 let Inst{6-10} = XT{4-0}; 732 let Inst{11-15} = XA{4-0}; 733 let Inst{16-20} = XB{4-0}; 734 let Inst{21-28} = xo; 735 let Inst{29} = XA{5}; 736 let Inst{30} = XB{5}; 737 let Inst{31} = XT{5}; 738} 739 740class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 741 InstrItinClass itin, list<dag> pattern> 742 : I<opcode, OOL, IOL, asmstr, itin> { 743 bits<3> CR; 744 bits<6> XA; 745 bits<6> XB; 746 747 let Pattern = pattern; 748 749 let Inst{6-8} = CR; 750 let Inst{9-10} = 0; 751 let Inst{11-15} = XA{4-0}; 752 let Inst{16-20} = XB{4-0}; 753 let Inst{21-28} = xo; 754 let Inst{29} = XA{5}; 755 let Inst{30} = XB{5}; 756 let Inst{31} = 0; 757} 758 759class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 760 InstrItinClass itin, list<dag> pattern> 761 : I<opcode, OOL, IOL, asmstr, itin> { 762 bits<6> XT; 763 bits<6> XA; 764 bits<6> XB; 765 bits<2> D; 766 767 let Pattern = pattern; 768 769 let Inst{6-10} = XT{4-0}; 770 let Inst{11-15} = XA{4-0}; 771 let Inst{16-20} = XB{4-0}; 772 let Inst{21} = 0; 773 let Inst{22-23} = D; 774 let Inst{24-28} = xo; 775 let Inst{29} = XA{5}; 776 let Inst{30} = XB{5}; 777 let Inst{31} = XT{5}; 778} 779 780class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 781 InstrItinClass itin, list<dag> pattern> 782 : I<opcode, OOL, IOL, asmstr, itin> { 783 bits<6> XT; 784 bits<6> XA; 785 bits<6> XB; 786 787 let Pattern = pattern; 788 789 bit RC = 0; // set by isDOT 790 791 let Inst{6-10} = XT{4-0}; 792 let Inst{11-15} = XA{4-0}; 793 let Inst{16-20} = XB{4-0}; 794 let Inst{21} = RC; 795 let Inst{22-28} = xo; 796 let Inst{29} = XA{5}; 797 let Inst{30} = XB{5}; 798 let Inst{31} = XT{5}; 799} 800 801class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 802 InstrItinClass itin, list<dag> pattern> 803 : I<opcode, OOL, IOL, asmstr, itin> { 804 bits<6> XT; 805 bits<6> XA; 806 bits<6> XB; 807 bits<6> XC; 808 809 let Pattern = pattern; 810 811 let Inst{6-10} = XT{4-0}; 812 let Inst{11-15} = XA{4-0}; 813 let Inst{16-20} = XB{4-0}; 814 let Inst{21-25} = XC{4-0}; 815 let Inst{26-27} = xo; 816 let Inst{28} = XC{5}; 817 let Inst{29} = XA{5}; 818 let Inst{30} = XB{5}; 819 let Inst{31} = XT{5}; 820} 821 822// DCB_Form - Form X instruction, used for dcb* instructions. 823class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 824 InstrItinClass itin, list<dag> pattern> 825 : I<31, OOL, IOL, asmstr, itin> { 826 bits<5> A; 827 bits<5> B; 828 829 let Pattern = pattern; 830 831 let Inst{6-10} = immfield; 832 let Inst{11-15} = A; 833 let Inst{16-20} = B; 834 let Inst{21-30} = xo; 835 let Inst{31} = 0; 836} 837 838 839// DSS_Form - Form X instruction, used for altivec dss* instructions. 840class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 841 InstrItinClass itin, list<dag> pattern> 842 : I<31, OOL, IOL, asmstr, itin> { 843 bits<2> STRM; 844 bits<5> A; 845 bits<5> B; 846 847 let Pattern = pattern; 848 849 let Inst{6} = T; 850 let Inst{7-8} = 0; 851 let Inst{9-10} = STRM; 852 let Inst{11-15} = A; 853 let Inst{16-20} = B; 854 let Inst{21-30} = xo; 855 let Inst{31} = 0; 856} 857 858// 1.7.7 XL-Form 859class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 860 InstrItinClass itin, list<dag> pattern> 861 : I<opcode, OOL, IOL, asmstr, itin> { 862 bits<5> CRD; 863 bits<5> CRA; 864 bits<5> CRB; 865 866 let Pattern = pattern; 867 868 let Inst{6-10} = CRD; 869 let Inst{11-15} = CRA; 870 let Inst{16-20} = CRB; 871 let Inst{21-30} = xo; 872 let Inst{31} = 0; 873} 874 875class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 876 InstrItinClass itin, list<dag> pattern> 877 : I<opcode, OOL, IOL, asmstr, itin> { 878 bits<5> CRD; 879 880 let Pattern = pattern; 881 882 let Inst{6-10} = CRD; 883 let Inst{11-15} = CRD; 884 let Inst{16-20} = CRD; 885 let Inst{21-30} = xo; 886 let Inst{31} = 0; 887} 888 889class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 890 InstrItinClass itin, list<dag> pattern> 891 : I<opcode, OOL, IOL, asmstr, itin> { 892 bits<5> BO; 893 bits<5> BI; 894 bits<2> BH; 895 896 let Pattern = pattern; 897 898 let Inst{6-10} = BO; 899 let Inst{11-15} = BI; 900 let Inst{16-18} = 0; 901 let Inst{19-20} = BH; 902 let Inst{21-30} = xo; 903 let Inst{31} = lk; 904} 905 906class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 907 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 908 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 909 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 910 bits<3> CR; 911 912 let BO = BIBO{4-0}; 913 let BI{0-1} = BIBO{5-6}; 914 let BI{2-4} = CR{0-2}; 915 let BH = 0; 916} 917 918class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 919 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 920 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 921 let BO = bo; 922 let BH = 0; 923} 924 925class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 926 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 927 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 928 let BO = bo; 929 let BI = bi; 930 let BH = 0; 931} 932 933class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 934 InstrItinClass itin> 935 : I<opcode, OOL, IOL, asmstr, itin> { 936 bits<3> BF; 937 bits<3> BFA; 938 939 let Inst{6-8} = BF; 940 let Inst{9-10} = 0; 941 let Inst{11-13} = BFA; 942 let Inst{14-15} = 0; 943 let Inst{16-20} = 0; 944 let Inst{21-30} = xo; 945 let Inst{31} = 0; 946} 947 948class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 949 bits<6> opcode2, bits<2> xo2, 950 dag OOL, dag IOL, string asmstr, 951 InstrItinClass itin, list<dag> pattern> 952 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 953 bits<5> BO; 954 bits<5> BI; 955 bits<2> BH; 956 957 bits<5> RST; 958 bits<19> DS_RA; 959 960 let Pattern = pattern; 961 962 let Inst{6-10} = BO; 963 let Inst{11-15} = BI; 964 let Inst{16-18} = 0; 965 let Inst{19-20} = BH; 966 let Inst{21-30} = xo1; 967 let Inst{31} = lk; 968 969 let Inst{38-42} = RST; 970 let Inst{43-47} = DS_RA{18-14}; // Register # 971 let Inst{48-61} = DS_RA{13-0}; // Displacement. 972 let Inst{62-63} = xo2; 973} 974 975class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 976 bits<5> bo, bits<5> bi, bit lk, 977 bits<6> opcode2, bits<2> xo2, 978 dag OOL, dag IOL, string asmstr, 979 InstrItinClass itin, list<dag> pattern> 980 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 981 OOL, IOL, asmstr, itin, pattern> { 982 let BO = bo; 983 let BI = bi; 984 let BH = 0; 985} 986 987// 1.7.8 XFX-Form 988class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 989 InstrItinClass itin> 990 : I<opcode, OOL, IOL, asmstr, itin> { 991 bits<5> RT; 992 bits<10> SPR; 993 994 let Inst{6-10} = RT; 995 let Inst{11} = SPR{4}; 996 let Inst{12} = SPR{3}; 997 let Inst{13} = SPR{2}; 998 let Inst{14} = SPR{1}; 999 let Inst{15} = SPR{0}; 1000 let Inst{16} = SPR{9}; 1001 let Inst{17} = SPR{8}; 1002 let Inst{18} = SPR{7}; 1003 let Inst{19} = SPR{6}; 1004 let Inst{20} = SPR{5}; 1005 let Inst{21-30} = xo; 1006 let Inst{31} = 0; 1007} 1008 1009class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1010 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1011 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1012 let SPR = spr; 1013} 1014 1015class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1016 InstrItinClass itin> 1017 : I<opcode, OOL, IOL, asmstr, itin> { 1018 bits<5> RT; 1019 1020 let Inst{6-10} = RT; 1021 let Inst{11-20} = 0; 1022 let Inst{21-30} = xo; 1023 let Inst{31} = 0; 1024} 1025 1026class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1027 InstrItinClass itin> 1028 : I<opcode, OOL, IOL, asmstr, itin> { 1029 bits<8> FXM; 1030 bits<5> rS; 1031 1032 let Inst{6-10} = rS; 1033 let Inst{11} = 0; 1034 let Inst{12-19} = FXM; 1035 let Inst{20} = 0; 1036 let Inst{21-30} = xo; 1037 let Inst{31} = 0; 1038} 1039 1040class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1041 InstrItinClass itin> 1042 : I<opcode, OOL, IOL, asmstr, itin> { 1043 bits<5> ST; 1044 bits<8> FXM; 1045 1046 let Inst{6-10} = ST; 1047 let Inst{11} = 1; 1048 let Inst{12-19} = FXM; 1049 let Inst{20} = 0; 1050 let Inst{21-30} = xo; 1051 let Inst{31} = 0; 1052} 1053 1054class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1055 InstrItinClass itin> 1056 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1057 1058class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1059 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1060 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1061 let SPR = spr; 1062} 1063 1064// XFL-Form - MTFSF 1065// This is probably 1.7.9, but I don't have the reference that uses this 1066// numbering scheme... 1067class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1068 InstrItinClass itin, list<dag>pattern> 1069 : I<opcode, OOL, IOL, asmstr, itin> { 1070 bits<8> FM; 1071 bits<5> rT; 1072 1073 bit RC = 0; // set by isDOT 1074 let Pattern = pattern; 1075 1076 let Inst{6} = 0; 1077 let Inst{7-14} = FM; 1078 let Inst{15} = 0; 1079 let Inst{16-20} = rT; 1080 let Inst{21-30} = xo; 1081 let Inst{31} = RC; 1082} 1083 1084// 1.7.10 XS-Form - SRADI. 1085class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1086 InstrItinClass itin, list<dag> pattern> 1087 : I<opcode, OOL, IOL, asmstr, itin> { 1088 bits<5> A; 1089 bits<5> RS; 1090 bits<6> SH; 1091 1092 bit RC = 0; // set by isDOT 1093 let Pattern = pattern; 1094 1095 let Inst{6-10} = RS; 1096 let Inst{11-15} = A; 1097 let Inst{16-20} = SH{4,3,2,1,0}; 1098 let Inst{21-29} = xo; 1099 let Inst{30} = SH{5}; 1100 let Inst{31} = RC; 1101} 1102 1103// 1.7.11 XO-Form 1104class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1105 InstrItinClass itin, list<dag> pattern> 1106 : I<opcode, OOL, IOL, asmstr, itin> { 1107 bits<5> RT; 1108 bits<5> RA; 1109 bits<5> RB; 1110 1111 let Pattern = pattern; 1112 1113 bit RC = 0; // set by isDOT 1114 1115 let Inst{6-10} = RT; 1116 let Inst{11-15} = RA; 1117 let Inst{16-20} = RB; 1118 let Inst{21} = oe; 1119 let Inst{22-30} = xo; 1120 let Inst{31} = RC; 1121} 1122 1123class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1124 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1125 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1126 let RB = 0; 1127} 1128 1129// 1.7.12 A-Form 1130class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1131 InstrItinClass itin, list<dag> pattern> 1132 : I<opcode, OOL, IOL, asmstr, itin> { 1133 bits<5> FRT; 1134 bits<5> FRA; 1135 bits<5> FRC; 1136 bits<5> FRB; 1137 1138 let Pattern = pattern; 1139 1140 bit RC = 0; // set by isDOT 1141 1142 let Inst{6-10} = FRT; 1143 let Inst{11-15} = FRA; 1144 let Inst{16-20} = FRB; 1145 let Inst{21-25} = FRC; 1146 let Inst{26-30} = xo; 1147 let Inst{31} = RC; 1148} 1149 1150class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1151 InstrItinClass itin, list<dag> pattern> 1152 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1153 let FRC = 0; 1154} 1155 1156class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1157 InstrItinClass itin, list<dag> pattern> 1158 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1159 let FRB = 0; 1160} 1161 1162class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1163 InstrItinClass itin, list<dag> pattern> 1164 : I<opcode, OOL, IOL, asmstr, itin> { 1165 bits<5> RT; 1166 bits<5> RA; 1167 bits<5> RB; 1168 bits<5> COND; 1169 1170 let Pattern = pattern; 1171 1172 let Inst{6-10} = RT; 1173 let Inst{11-15} = RA; 1174 let Inst{16-20} = RB; 1175 let Inst{21-25} = COND; 1176 let Inst{26-30} = xo; 1177 let Inst{31} = 0; 1178} 1179 1180// 1.7.13 M-Form 1181class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1182 InstrItinClass itin, list<dag> pattern> 1183 : I<opcode, OOL, IOL, asmstr, itin> { 1184 bits<5> RA; 1185 bits<5> RS; 1186 bits<5> RB; 1187 bits<5> MB; 1188 bits<5> ME; 1189 1190 let Pattern = pattern; 1191 1192 bit RC = 0; // set by isDOT 1193 1194 let Inst{6-10} = RS; 1195 let Inst{11-15} = RA; 1196 let Inst{16-20} = RB; 1197 let Inst{21-25} = MB; 1198 let Inst{26-30} = ME; 1199 let Inst{31} = RC; 1200} 1201 1202class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1203 InstrItinClass itin, list<dag> pattern> 1204 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1205} 1206 1207// 1.7.14 MD-Form 1208class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1209 InstrItinClass itin, list<dag> pattern> 1210 : I<opcode, OOL, IOL, asmstr, itin> { 1211 bits<5> RA; 1212 bits<5> RS; 1213 bits<6> SH; 1214 bits<6> MBE; 1215 1216 let Pattern = pattern; 1217 1218 bit RC = 0; // set by isDOT 1219 1220 let Inst{6-10} = RS; 1221 let Inst{11-15} = RA; 1222 let Inst{16-20} = SH{4,3,2,1,0}; 1223 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1224 let Inst{27-29} = xo; 1225 let Inst{30} = SH{5}; 1226 let Inst{31} = RC; 1227} 1228 1229class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1230 InstrItinClass itin, list<dag> pattern> 1231 : I<opcode, OOL, IOL, asmstr, itin> { 1232 bits<5> RA; 1233 bits<5> RS; 1234 bits<5> RB; 1235 bits<6> MBE; 1236 1237 let Pattern = pattern; 1238 1239 bit RC = 0; // set by isDOT 1240 1241 let Inst{6-10} = RS; 1242 let Inst{11-15} = RA; 1243 let Inst{16-20} = RB; 1244 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1245 let Inst{27-30} = xo; 1246 let Inst{31} = RC; 1247} 1248 1249 1250// E-1 VA-Form 1251 1252// VAForm_1 - DACB ordering. 1253class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1254 InstrItinClass itin, list<dag> pattern> 1255 : I<4, OOL, IOL, asmstr, itin> { 1256 bits<5> VD; 1257 bits<5> VA; 1258 bits<5> VC; 1259 bits<5> VB; 1260 1261 let Pattern = pattern; 1262 1263 let Inst{6-10} = VD; 1264 let Inst{11-15} = VA; 1265 let Inst{16-20} = VB; 1266 let Inst{21-25} = VC; 1267 let Inst{26-31} = xo; 1268} 1269 1270// VAForm_1a - DABC ordering. 1271class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1272 InstrItinClass itin, list<dag> pattern> 1273 : I<4, OOL, IOL, asmstr, itin> { 1274 bits<5> VD; 1275 bits<5> VA; 1276 bits<5> VB; 1277 bits<5> VC; 1278 1279 let Pattern = pattern; 1280 1281 let Inst{6-10} = VD; 1282 let Inst{11-15} = VA; 1283 let Inst{16-20} = VB; 1284 let Inst{21-25} = VC; 1285 let Inst{26-31} = xo; 1286} 1287 1288class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1289 InstrItinClass itin, list<dag> pattern> 1290 : I<4, OOL, IOL, asmstr, itin> { 1291 bits<5> VD; 1292 bits<5> VA; 1293 bits<5> VB; 1294 bits<4> SH; 1295 1296 let Pattern = pattern; 1297 1298 let Inst{6-10} = VD; 1299 let Inst{11-15} = VA; 1300 let Inst{16-20} = VB; 1301 let Inst{21} = 0; 1302 let Inst{22-25} = SH; 1303 let Inst{26-31} = xo; 1304} 1305 1306// E-2 VX-Form 1307class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1308 InstrItinClass itin, list<dag> pattern> 1309 : I<4, OOL, IOL, asmstr, itin> { 1310 bits<5> VD; 1311 bits<5> VA; 1312 bits<5> VB; 1313 1314 let Pattern = pattern; 1315 1316 let Inst{6-10} = VD; 1317 let Inst{11-15} = VA; 1318 let Inst{16-20} = VB; 1319 let Inst{21-31} = xo; 1320} 1321 1322class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1323 InstrItinClass itin, list<dag> pattern> 1324 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1325 let VA = VD; 1326 let VB = VD; 1327} 1328 1329 1330class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1331 InstrItinClass itin, list<dag> pattern> 1332 : I<4, OOL, IOL, asmstr, itin> { 1333 bits<5> VD; 1334 bits<5> VB; 1335 1336 let Pattern = pattern; 1337 1338 let Inst{6-10} = VD; 1339 let Inst{11-15} = 0; 1340 let Inst{16-20} = VB; 1341 let Inst{21-31} = xo; 1342} 1343 1344class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1345 InstrItinClass itin, list<dag> pattern> 1346 : I<4, OOL, IOL, asmstr, itin> { 1347 bits<5> VD; 1348 bits<5> IMM; 1349 1350 let Pattern = pattern; 1351 1352 let Inst{6-10} = VD; 1353 let Inst{11-15} = IMM; 1354 let Inst{16-20} = 0; 1355 let Inst{21-31} = xo; 1356} 1357 1358/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1359class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1360 InstrItinClass itin, list<dag> pattern> 1361 : I<4, OOL, IOL, asmstr, itin> { 1362 bits<5> VD; 1363 1364 let Pattern = pattern; 1365 1366 let Inst{6-10} = VD; 1367 let Inst{11-15} = 0; 1368 let Inst{16-20} = 0; 1369 let Inst{21-31} = xo; 1370} 1371 1372/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1373class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1374 InstrItinClass itin, list<dag> pattern> 1375 : I<4, OOL, IOL, asmstr, itin> { 1376 bits<5> VB; 1377 1378 let Pattern = pattern; 1379 1380 let Inst{6-10} = 0; 1381 let Inst{11-15} = 0; 1382 let Inst{16-20} = VB; 1383 let Inst{21-31} = xo; 1384} 1385 1386// E-4 VXR-Form 1387class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1388 InstrItinClass itin, list<dag> pattern> 1389 : I<4, OOL, IOL, asmstr, itin> { 1390 bits<5> VD; 1391 bits<5> VA; 1392 bits<5> VB; 1393 bit RC = 0; 1394 1395 let Pattern = pattern; 1396 1397 let Inst{6-10} = VD; 1398 let Inst{11-15} = VA; 1399 let Inst{16-20} = VB; 1400 let Inst{21} = RC; 1401 let Inst{22-31} = xo; 1402} 1403 1404//===----------------------------------------------------------------------===// 1405class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1406 : I<0, OOL, IOL, asmstr, NoItinerary> { 1407 let isCodeGenOnly = 1; 1408 let PPC64 = 0; 1409 let Pattern = pattern; 1410 let Inst{31-0} = 0; 1411} 1412