1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H 16 17 #include "PPCFrameLowering.h" 18 #include "PPCISelLowering.h" 19 #include "PPCInstrInfo.h" 20 #include "PPCSelectionDAGInfo.h" 21 #include "llvm/ADT/Triple.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/MC/MCInstrItineraries.h" 24 #include "llvm/Target/TargetSubtargetInfo.h" 25 #include <string> 26 27 #define GET_SUBTARGETINFO_HEADER 28 #include "PPCGenSubtargetInfo.inc" 29 30 // GCC #defines PPC on Linux but we use it as our namespace name 31 #undef PPC 32 33 namespace llvm { 34 class StringRef; 35 36 namespace PPC { 37 // -m directive values. 38 enum { 39 DIR_NONE, 40 DIR_32, 41 DIR_440, 42 DIR_601, 43 DIR_602, 44 DIR_603, 45 DIR_7400, 46 DIR_750, 47 DIR_970, 48 DIR_A2, 49 DIR_E500mc, 50 DIR_E5500, 51 DIR_PWR3, 52 DIR_PWR4, 53 DIR_PWR5, 54 DIR_PWR5X, 55 DIR_PWR6, 56 DIR_PWR6X, 57 DIR_PWR7, 58 DIR_PWR8, 59 DIR_64 60 }; 61 } 62 63 class GlobalValue; 64 class TargetMachine; 65 66 class PPCSubtarget : public PPCGenSubtargetInfo { 67 protected: 68 /// TargetTriple - What processor and OS we're targeting. 69 Triple TargetTriple; 70 71 // Calculates type size & alignment 72 const DataLayout DL; 73 74 /// stackAlignment - The minimum alignment known to hold of the stack frame on 75 /// entry to the function and which must be maintained by every function. 76 unsigned StackAlignment; 77 78 /// Selected instruction itineraries (one entry per itinerary class.) 79 InstrItineraryData InstrItins; 80 81 /// Which cpu directive was used. 82 unsigned DarwinDirective; 83 84 /// Used by the ISel to turn in optimizations for POWER4-derived architectures 85 bool HasMFOCRF; 86 bool Has64BitSupport; 87 bool Use64BitRegs; 88 bool UseCRBits; 89 bool IsPPC64; 90 bool HasAltivec; 91 bool HasSPE; 92 bool HasQPX; 93 bool HasVSX; 94 bool HasP8Vector; 95 bool HasFCPSGN; 96 bool HasFSQRT; 97 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; 98 bool HasRecipPrec; 99 bool HasSTFIWX; 100 bool HasLFIWAX; 101 bool HasFPRND; 102 bool HasFPCVT; 103 bool HasISEL; 104 bool HasPOPCNTD; 105 bool HasCMPB; 106 bool HasLDBRX; 107 bool IsBookE; 108 bool HasOnlyMSYNC; 109 bool IsE500; 110 bool IsPPC4xx; 111 bool IsPPC6xx; 112 bool DeprecatedMFTB; 113 bool DeprecatedDST; 114 bool HasLazyResolverStubs; 115 bool IsLittleEndian; 116 117 enum { 118 PPC_ABI_UNKNOWN, 119 PPC_ABI_ELFv1, 120 PPC_ABI_ELFv2 121 } TargetABI; 122 123 PPCFrameLowering FrameLowering; 124 PPCInstrInfo InstrInfo; 125 PPCTargetLowering TLInfo; 126 PPCSelectionDAGInfo TSInfo; 127 128 public: 129 /// This constructor initializes the data members to match that 130 /// of the specified triple. 131 /// 132 PPCSubtarget(const std::string &TT, const std::string &CPU, 133 const std::string &FS, const PPCTargetMachine &TM); 134 135 /// ParseSubtargetFeatures - Parses features string setting specified 136 /// subtarget options. Definition of function is auto generated by tblgen. 137 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 138 139 /// getStackAlignment - Returns the minimum alignment known to hold of the 140 /// stack frame on entry to the function and which must be maintained by every 141 /// function for this subtarget. getStackAlignment()142 unsigned getStackAlignment() const { return StackAlignment; } 143 144 /// getDarwinDirective - Returns the -m directive specified for the cpu. 145 /// getDarwinDirective()146 unsigned getDarwinDirective() const { return DarwinDirective; } 147 148 /// getInstrItins - Return the instruction itineraries based on subtarget 149 /// selection. getInstrItineraryData()150 const InstrItineraryData *getInstrItineraryData() const override { 151 return &InstrItins; 152 } 153 getFrameLowering()154 const PPCFrameLowering *getFrameLowering() const override { 155 return &FrameLowering; 156 } getDataLayout()157 const DataLayout *getDataLayout() const override { return &DL; } getInstrInfo()158 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; } getTargetLowering()159 const PPCTargetLowering *getTargetLowering() const override { 160 return &TLInfo; 161 } getSelectionDAGInfo()162 const PPCSelectionDAGInfo *getSelectionDAGInfo() const override { 163 return &TSInfo; 164 } getRegisterInfo()165 const PPCRegisterInfo *getRegisterInfo() const override { 166 return &getInstrInfo()->getRegisterInfo(); 167 } 168 169 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 170 /// so that we can use initializer lists for subtarget initialization. 171 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 172 173 private: 174 void initializeEnvironment(); 175 void initSubtargetFeatures(StringRef CPU, StringRef FS); 176 177 public: 178 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode. 179 /// isPPC64()180 bool isPPC64() const { return IsPPC64; } 181 182 /// has64BitSupport - Return true if the selected CPU supports 64-bit 183 /// instructions, regardless of whether we are in 32-bit or 64-bit mode. has64BitSupport()184 bool has64BitSupport() const { return Has64BitSupport; } 185 186 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit 187 /// registers in 32-bit mode when possible. This can only true if 188 /// has64BitSupport() returns true. use64BitRegs()189 bool use64BitRegs() const { return Use64BitRegs; } 190 191 /// useCRBits - Return true if we should store and manipulate i1 values in 192 /// the individual condition register bits. useCRBits()193 bool useCRBits() const { return UseCRBits; } 194 195 /// hasLazyResolverStub - Return true if accesses to the specified global have 196 /// to go through a dyld lazy resolution stub. This means that an extra load 197 /// is required to get the address of the global. 198 bool hasLazyResolverStub(const GlobalValue *GV, 199 const TargetMachine &TM) const; 200 201 // isLittleEndian - True if generating little-endian code isLittleEndian()202 bool isLittleEndian() const { return IsLittleEndian; } 203 204 // Specific obvious features. hasFCPSGN()205 bool hasFCPSGN() const { return HasFCPSGN; } hasFSQRT()206 bool hasFSQRT() const { return HasFSQRT; } hasFRE()207 bool hasFRE() const { return HasFRE; } hasFRES()208 bool hasFRES() const { return HasFRES; } hasFRSQRTE()209 bool hasFRSQRTE() const { return HasFRSQRTE; } hasFRSQRTES()210 bool hasFRSQRTES() const { return HasFRSQRTES; } hasRecipPrec()211 bool hasRecipPrec() const { return HasRecipPrec; } hasSTFIWX()212 bool hasSTFIWX() const { return HasSTFIWX; } hasLFIWAX()213 bool hasLFIWAX() const { return HasLFIWAX; } hasFPRND()214 bool hasFPRND() const { return HasFPRND; } hasFPCVT()215 bool hasFPCVT() const { return HasFPCVT; } hasAltivec()216 bool hasAltivec() const { return HasAltivec; } hasSPE()217 bool hasSPE() const { return HasSPE; } hasQPX()218 bool hasQPX() const { return HasQPX; } hasVSX()219 bool hasVSX() const { return HasVSX; } hasP8Vector()220 bool hasP8Vector() const { return HasP8Vector; } hasMFOCRF()221 bool hasMFOCRF() const { return HasMFOCRF; } hasISEL()222 bool hasISEL() const { return HasISEL; } hasPOPCNTD()223 bool hasPOPCNTD() const { return HasPOPCNTD; } hasCMPB()224 bool hasCMPB() const { return HasCMPB; } hasLDBRX()225 bool hasLDBRX() const { return HasLDBRX; } isBookE()226 bool isBookE() const { return IsBookE; } hasOnlyMSYNC()227 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; } isPPC4xx()228 bool isPPC4xx() const { return IsPPC4xx; } isPPC6xx()229 bool isPPC6xx() const { return IsPPC6xx; } isE500()230 bool isE500() const { return IsE500; } isDeprecatedMFTB()231 bool isDeprecatedMFTB() const { return DeprecatedMFTB; } isDeprecatedDST()232 bool isDeprecatedDST() const { return DeprecatedDST; } 233 getTargetTriple()234 const Triple &getTargetTriple() const { return TargetTriple; } 235 236 /// isDarwin - True if this is any darwin platform. isDarwin()237 bool isDarwin() const { return TargetTriple.isMacOSX(); } 238 /// isBGQ - True if this is a BG/Q platform. isBGQ()239 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; } 240 isTargetELF()241 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } isTargetMachO()242 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 243 isDarwinABI()244 bool isDarwinABI() const { return isDarwin(); } isSVR4ABI()245 bool isSVR4ABI() const { return !isDarwin(); } isELFv2ABI()246 bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; } 247 enableEarlyIfConversion()248 bool enableEarlyIfConversion() const override { return hasISEL(); } 249 250 // Scheduling customization. 251 bool enableMachineScheduler() const override; 252 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 253 bool enablePostMachineScheduler() const override; 254 AntiDepBreakMode getAntiDepBreakMode() const override; 255 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 256 257 void overrideSchedPolicy(MachineSchedPolicy &Policy, 258 MachineInstr *begin, 259 MachineInstr *end, 260 unsigned NumRegionInstrs) const override; 261 bool useAA() const override; 262 263 bool enableSubRegLiveness() const override; 264 }; 265 } // End llvm namespace 266 267 #endif 268