1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H 12 #define LLVM_LIB_TARGET_R600_AMDGPU_H 13 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUInstrPrinter; 20 class AMDGPUSubtarget; 21 class AMDGPUTargetMachine; 22 class FunctionPass; 23 class MCAsmInfo; 24 class raw_ostream; 25 class Target; 26 class TargetMachine; 27 28 // R600 Passes 29 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 30 FunctionPass *createR600TextureIntrinsicsReplacer(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 34 FunctionPass *createR600Packetizer(TargetMachine &tm); 35 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 38 // SI Passes 39 FunctionPass *createSITypeRewriter(); 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSIFoldOperandsPass(); 42 FunctionPass *createSILowerI1CopiesPass(); 43 FunctionPass *createSIShrinkInstructionsPass(); 44 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 45 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm); 46 FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm); 47 FunctionPass *createSIFixSGPRLiveRangesPass(); 48 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 49 FunctionPass *createSIInsertWaits(TargetMachine &tm); 50 FunctionPass *createSIPrepareScratchRegs(); 51 52 void initializeSIFoldOperandsPass(PassRegistry &); 53 extern char &SIFoldOperandsID; 54 55 void initializeSILowerI1CopiesPass(PassRegistry &); 56 extern char &SILowerI1CopiesID; 57 58 void initializeSILoadStoreOptimizerPass(PassRegistry &); 59 extern char &SILoadStoreOptimizerID; 60 61 // Passes common to R600 and SI 62 FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST); 63 Pass *createAMDGPUStructurizeCFGPass(); 64 FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 65 ModulePass *createAMDGPUAlwaysInlinePass(); 66 67 /// \brief Creates an AMDGPU-specific Target Transformation Info pass. 68 ImmutablePass * 69 createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM); 70 71 void initializeSIFixSGPRLiveRangesPass(PassRegistry&); 72 extern char &SIFixSGPRLiveRangesID; 73 74 75 extern Target TheAMDGPUTarget; 76 extern Target TheGCNTarget; 77 78 namespace AMDGPU { 79 enum TargetIndex { 80 TI_CONSTDATA_START, 81 TI_SCRATCH_RSRC_DWORD0, 82 TI_SCRATCH_RSRC_DWORD1, 83 TI_SCRATCH_RSRC_DWORD2, 84 TI_SCRATCH_RSRC_DWORD3 85 }; 86 } 87 88 #define END_OF_TEXT_LABEL_NAME "EndOfTextLabel" 89 90 } // End namespace llvm 91 92 namespace ShaderType { 93 enum Type { 94 PIXEL = 0, 95 VERTEX = 1, 96 GEOMETRY = 2, 97 COMPUTE = 3 98 }; 99 } 100 101 /// OpenCL uses address spaces to differentiate between 102 /// various memory regions on the hardware. On the CPU 103 /// all of the address spaces point to the same memory, 104 /// however on the GPU, each address space points to 105 /// a separate piece of memory that is unique from other 106 /// memory locations. 107 namespace AMDGPUAS { 108 enum AddressSpaces { 109 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 110 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 111 CONSTANT_ADDRESS = 2, ///< Address space for constant memory 112 LOCAL_ADDRESS = 3, ///< Address space for local memory. 113 FLAT_ADDRESS = 4, ///< Address space for flat memory. 114 REGION_ADDRESS = 5, ///< Address space for region memory. 115 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 116 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 117 118 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 119 // order to be able to dynamically index a constant buffer, for example: 120 // 121 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 122 123 CONSTANT_BUFFER_0 = 8, 124 CONSTANT_BUFFER_1 = 9, 125 CONSTANT_BUFFER_2 = 10, 126 CONSTANT_BUFFER_3 = 11, 127 CONSTANT_BUFFER_4 = 12, 128 CONSTANT_BUFFER_5 = 13, 129 CONSTANT_BUFFER_6 = 14, 130 CONSTANT_BUFFER_7 = 15, 131 CONSTANT_BUFFER_8 = 16, 132 CONSTANT_BUFFER_9 = 17, 133 CONSTANT_BUFFER_10 = 18, 134 CONSTANT_BUFFER_11 = 19, 135 CONSTANT_BUFFER_12 = 20, 136 CONSTANT_BUFFER_13 = 21, 137 CONSTANT_BUFFER_14 = 22, 138 CONSTANT_BUFFER_15 = 23, 139 ADDRESS_NONE = 24, ///< Address space for unknown memory. 140 LAST_ADDRESS = ADDRESS_NONE 141 }; 142 143 } // namespace AMDGPUAS 144 145 #endif 146