1f4a2713aSLionel Sambuc//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===// 2f4a2713aSLionel Sambuc// 3f4a2713aSLionel Sambuc// The LLVM Compiler Infrastructure 4f4a2713aSLionel Sambuc// 5f4a2713aSLionel Sambuc// This file is distributed under the University of Illinois Open Source 6f4a2713aSLionel Sambuc// License. See LICENSE.TXT for details. 7f4a2713aSLionel Sambuc// 8f4a2713aSLionel Sambuc//==-----------------------------------------------------------------------===// 9f4a2713aSLionel Sambuc 10*0a6a1f1dSLionel Sambucinclude "llvm/Target/Target.td" 11f4a2713aSLionel Sambuc 12f4a2713aSLionel Sambuc//===----------------------------------------------------------------------===// 13f4a2713aSLionel Sambuc// Subtarget Features 14f4a2713aSLionel Sambuc//===----------------------------------------------------------------------===// 15f4a2713aSLionel Sambuc 16f4a2713aSLionel Sambuc// Debugging Features 17f4a2713aSLionel Sambuc 18f4a2713aSLionel Sambucdef FeatureDumpCode : SubtargetFeature <"DumpCode", 19f4a2713aSLionel Sambuc "DumpCode", 20f4a2713aSLionel Sambuc "true", 21f4a2713aSLionel Sambuc "Dump MachineInstrs in the CodeEmitter">; 22f4a2713aSLionel Sambuc 23f4a2713aSLionel Sambucdef FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer", 24f4a2713aSLionel Sambuc "EnableIRStructurizer", 25f4a2713aSLionel Sambuc "false", 26f4a2713aSLionel Sambuc "Disable IR Structurizer">; 27f4a2713aSLionel Sambuc 28*0a6a1f1dSLionel Sambucdef FeaturePromoteAlloca : SubtargetFeature <"promote-alloca", 29*0a6a1f1dSLionel Sambuc "EnablePromoteAlloca", 30*0a6a1f1dSLionel Sambuc "true", 31*0a6a1f1dSLionel Sambuc "Enable promote alloca pass">; 32*0a6a1f1dSLionel Sambuc 33f4a2713aSLionel Sambuc// Target features 34f4a2713aSLionel Sambuc 35f4a2713aSLionel Sambucdef FeatureIfCvt : SubtargetFeature <"disable-ifcvt", 36f4a2713aSLionel Sambuc "EnableIfCvt", 37f4a2713aSLionel Sambuc "false", 38f4a2713aSLionel Sambuc "Disable the if conversion pass">; 39f4a2713aSLionel Sambuc 40f4a2713aSLionel Sambucdef FeatureFP64 : SubtargetFeature<"fp64", 41f4a2713aSLionel Sambuc "FP64", 42f4a2713aSLionel Sambuc "true", 43*0a6a1f1dSLionel Sambuc "Enable double precision operations">; 44*0a6a1f1dSLionel Sambuc 45*0a6a1f1dSLionel Sambucdef FeatureFP64Denormals : SubtargetFeature<"fp64-denormals", 46*0a6a1f1dSLionel Sambuc "FP64Denormals", 47*0a6a1f1dSLionel Sambuc "true", 48*0a6a1f1dSLionel Sambuc "Enable double precision denormal handling", 49*0a6a1f1dSLionel Sambuc [FeatureFP64]>; 50*0a6a1f1dSLionel Sambuc 51*0a6a1f1dSLionel Sambuc// Some instructions do not support denormals despite this flag. Using 52*0a6a1f1dSLionel Sambuc// fp32 denormals also causes instructions to run at the double 53*0a6a1f1dSLionel Sambuc// precision rate for the device. 54*0a6a1f1dSLionel Sambucdef FeatureFP32Denormals : SubtargetFeature<"fp32-denormals", 55*0a6a1f1dSLionel Sambuc "FP32Denormals", 56*0a6a1f1dSLionel Sambuc "true", 57*0a6a1f1dSLionel Sambuc "Enable single precision denormal handling">; 58f4a2713aSLionel Sambuc 59f4a2713aSLionel Sambucdef Feature64BitPtr : SubtargetFeature<"64BitPtr", 60f4a2713aSLionel Sambuc "Is64bit", 61f4a2713aSLionel Sambuc "true", 62*0a6a1f1dSLionel Sambuc "Specify if 64-bit addressing should be used">; 63f4a2713aSLionel Sambuc 64f4a2713aSLionel Sambucdef FeatureR600ALUInst : SubtargetFeature<"R600ALUInst", 65f4a2713aSLionel Sambuc "R600ALUInst", 66f4a2713aSLionel Sambuc "false", 67*0a6a1f1dSLionel Sambuc "Older version of ALU instructions encoding">; 68f4a2713aSLionel Sambuc 69f4a2713aSLionel Sambucdef FeatureVertexCache : SubtargetFeature<"HasVertexCache", 70f4a2713aSLionel Sambuc "HasVertexCache", 71f4a2713aSLionel Sambuc "true", 72*0a6a1f1dSLionel Sambuc "Specify use of dedicated vertex cache">; 73f4a2713aSLionel Sambuc 74f4a2713aSLionel Sambucdef FeatureCaymanISA : SubtargetFeature<"caymanISA", 75f4a2713aSLionel Sambuc "CaymanISA", 76f4a2713aSLionel Sambuc "true", 77f4a2713aSLionel Sambuc "Use Cayman ISA">; 78f4a2713aSLionel Sambuc 79*0a6a1f1dSLionel Sambucdef FeatureCFALUBug : SubtargetFeature<"cfalubug", 80*0a6a1f1dSLionel Sambuc "CFALUBug", 81*0a6a1f1dSLionel Sambuc "true", 82*0a6a1f1dSLionel Sambuc "GPU has CF_ALU bug">; 83*0a6a1f1dSLionel Sambuc 84*0a6a1f1dSLionel Sambuc// XXX - This should probably be removed once enabled by default 85*0a6a1f1dSLionel Sambucdef FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt", 86*0a6a1f1dSLionel Sambuc "EnableLoadStoreOpt", 87*0a6a1f1dSLionel Sambuc "true", 88*0a6a1f1dSLionel Sambuc "Enable SI load/store optimizer pass">; 89*0a6a1f1dSLionel Sambuc 90*0a6a1f1dSLionel Sambucdef FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space", 91*0a6a1f1dSLionel Sambuc "FlatAddressSpace", 92*0a6a1f1dSLionel Sambuc "true", 93*0a6a1f1dSLionel Sambuc "Support flat address space">; 94*0a6a1f1dSLionel Sambuc 95*0a6a1f1dSLionel Sambucdef FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling", 96*0a6a1f1dSLionel Sambuc "EnableVGPRSpilling", 97*0a6a1f1dSLionel Sambuc "true", 98*0a6a1f1dSLionel Sambuc "Enable spilling of VGPRs to scratch memory">; 99*0a6a1f1dSLionel Sambuc 100*0a6a1f1dSLionel Sambucdef FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug", 101*0a6a1f1dSLionel Sambuc "SGPRInitBug", 102*0a6a1f1dSLionel Sambuc "true", 103*0a6a1f1dSLionel Sambuc "VI SGPR initilization bug requiring a fixed SGPR allocation size">; 104*0a6a1f1dSLionel Sambuc 105f4a2713aSLionel Sambucclass SubtargetFeatureFetchLimit <string Value> : 106f4a2713aSLionel Sambuc SubtargetFeature <"fetch"#Value, 107f4a2713aSLionel Sambuc "TexVTXClauseSize", 108f4a2713aSLionel Sambuc Value, 109f4a2713aSLionel Sambuc "Limit the maximum number of fetches in a clause to "#Value>; 110f4a2713aSLionel Sambuc 111f4a2713aSLionel Sambucdef FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">; 112f4a2713aSLionel Sambucdef FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">; 113f4a2713aSLionel Sambuc 114*0a6a1f1dSLionel Sambucclass SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature< 115*0a6a1f1dSLionel Sambuc "wavefrontsize"#Value, 116*0a6a1f1dSLionel Sambuc "WavefrontSize", 117*0a6a1f1dSLionel Sambuc !cast<string>(Value), 118*0a6a1f1dSLionel Sambuc "The number of threads per wavefront">; 119*0a6a1f1dSLionel Sambuc 120*0a6a1f1dSLionel Sambucdef FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>; 121*0a6a1f1dSLionel Sambucdef FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>; 122*0a6a1f1dSLionel Sambucdef FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>; 123*0a6a1f1dSLionel Sambuc 124*0a6a1f1dSLionel Sambucclass SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature< 125*0a6a1f1dSLionel Sambuc "localmemorysize"#Value, 126*0a6a1f1dSLionel Sambuc "LocalMemorySize", 127*0a6a1f1dSLionel Sambuc !cast<string>(Value), 128*0a6a1f1dSLionel Sambuc "The size of local memory in bytes">; 129*0a6a1f1dSLionel Sambuc 130f4a2713aSLionel Sambucclass SubtargetFeatureGeneration <string Value, 131f4a2713aSLionel Sambuc list<SubtargetFeature> Implies> : 132f4a2713aSLionel Sambuc SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value, 133f4a2713aSLionel Sambuc Value#" GPU generation", Implies>; 134f4a2713aSLionel Sambuc 135*0a6a1f1dSLionel Sambucdef FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>; 136*0a6a1f1dSLionel Sambucdef FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>; 137*0a6a1f1dSLionel Sambucdef FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>; 138*0a6a1f1dSLionel Sambuc 139f4a2713aSLionel Sambucdef FeatureR600 : SubtargetFeatureGeneration<"R600", 140*0a6a1f1dSLionel Sambuc [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>; 141f4a2713aSLionel Sambuc 142f4a2713aSLionel Sambucdef FeatureR700 : SubtargetFeatureGeneration<"R700", 143*0a6a1f1dSLionel Sambuc [FeatureFetchLimit16, FeatureLocalMemorySize0]>; 144f4a2713aSLionel Sambuc 145f4a2713aSLionel Sambucdef FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN", 146*0a6a1f1dSLionel Sambuc [FeatureFetchLimit16, FeatureLocalMemorySize32768]>; 147f4a2713aSLionel Sambuc 148f4a2713aSLionel Sambucdef FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS", 149*0a6a1f1dSLionel Sambuc [FeatureFetchLimit16, FeatureWavefrontSize64, 150*0a6a1f1dSLionel Sambuc FeatureLocalMemorySize32768] 151*0a6a1f1dSLionel Sambuc>; 152f4a2713aSLionel Sambuc 153f4a2713aSLionel Sambucdef FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS", 154*0a6a1f1dSLionel Sambuc [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768, 155*0a6a1f1dSLionel Sambuc FeatureWavefrontSize64]>; 156f4a2713aSLionel Sambuc 157f4a2713aSLionel Sambucdef FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS", 158*0a6a1f1dSLionel Sambuc [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, 159*0a6a1f1dSLionel Sambuc FeatureWavefrontSize64, FeatureFlatAddressSpace]>; 160*0a6a1f1dSLionel Sambuc 161*0a6a1f1dSLionel Sambucdef FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS", 162*0a6a1f1dSLionel Sambuc [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, 163*0a6a1f1dSLionel Sambuc FeatureWavefrontSize64, FeatureFlatAddressSpace]>; 164*0a6a1f1dSLionel Sambuc 165f4a2713aSLionel Sambuc//===----------------------------------------------------------------------===// 166f4a2713aSLionel Sambuc 167f4a2713aSLionel Sambucdef AMDGPUInstrInfo : InstrInfo { 168f4a2713aSLionel Sambuc let guessInstructionProperties = 1; 169f4a2713aSLionel Sambuc} 170f4a2713aSLionel Sambuc 171*0a6a1f1dSLionel Sambucdef AMDGPUAsmParser : AsmParser { 172*0a6a1f1dSLionel Sambuc // Some of the R600 registers have the same name, so this crashes. 173*0a6a1f1dSLionel Sambuc // For example T0_XYZW and T0_XY both have the asm name T0. 174*0a6a1f1dSLionel Sambuc let ShouldEmitMatchRegisterName = 0; 175f4a2713aSLionel Sambuc} 176f4a2713aSLionel Sambuc 177f4a2713aSLionel Sambucdef AMDGPU : Target { 178f4a2713aSLionel Sambuc // Pull in Instruction Info: 179f4a2713aSLionel Sambuc let InstructionSet = AMDGPUInstrInfo; 180*0a6a1f1dSLionel Sambuc let AssemblyParsers = [AMDGPUAsmParser]; 181*0a6a1f1dSLionel Sambuc} 182*0a6a1f1dSLionel Sambuc 183*0a6a1f1dSLionel Sambuc// Dummy Instruction itineraries for pseudo instructions 184*0a6a1f1dSLionel Sambucdef ALU_NULL : FuncUnit; 185*0a6a1f1dSLionel Sambucdef NullALU : InstrItinClass; 186*0a6a1f1dSLionel Sambuc 187*0a6a1f1dSLionel Sambuc//===----------------------------------------------------------------------===// 188*0a6a1f1dSLionel Sambuc// Predicate helper class 189*0a6a1f1dSLionel Sambuc//===----------------------------------------------------------------------===// 190*0a6a1f1dSLionel Sambuc 191*0a6a1f1dSLionel Sambucclass PredicateControl { 192*0a6a1f1dSLionel Sambuc Predicate SubtargetPredicate; 193*0a6a1f1dSLionel Sambuc list<Predicate> OtherPredicates = []; 194*0a6a1f1dSLionel Sambuc list<Predicate> Predicates = !listconcat([SubtargetPredicate], 195*0a6a1f1dSLionel Sambuc OtherPredicates); 196f4a2713aSLionel Sambuc} 197f4a2713aSLionel Sambuc 198f4a2713aSLionel Sambuc// Include AMDGPU TD files 199f4a2713aSLionel Sambucinclude "R600Schedule.td" 200f4a2713aSLionel Sambucinclude "SISchedule.td" 201f4a2713aSLionel Sambucinclude "Processors.td" 202f4a2713aSLionel Sambucinclude "AMDGPUInstrInfo.td" 203f4a2713aSLionel Sambucinclude "AMDGPUIntrinsics.td" 204f4a2713aSLionel Sambucinclude "AMDGPURegisterInfo.td" 205f4a2713aSLionel Sambucinclude "AMDGPUInstructions.td" 206f4a2713aSLionel Sambucinclude "AMDGPUCallingConv.td" 207