1//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
10// Include AMDIL TD files
11include "AMDILBase.td"
12
13//===----------------------------------------------------------------------===//
14// Subtarget Features
15//===----------------------------------------------------------------------===//
16
17// Debugging Features
18
19def FeatureDumpCode : SubtargetFeature <"DumpCode",
20        "DumpCode",
21        "true",
22        "Dump MachineInstrs in the CodeEmitter">;
23
24def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
25        "EnableIRStructurizer",
26        "false",
27        "Disable IR Structurizer">;
28
29// Target features
30
31def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
32        "EnableIfCvt",
33        "false",
34        "Disable the if conversion pass">;
35
36def FeatureFP64     : SubtargetFeature<"fp64",
37        "FP64",
38        "true",
39        "Enable 64bit double precision operations">;
40
41def Feature64BitPtr : SubtargetFeature<"64BitPtr",
42        "Is64bit",
43        "true",
44        "Specify if 64bit addressing should be used.">;
45
46def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
47        "Is32on64bit",
48        "false",
49        "Specify if 64bit sized pointers with 32bit addressing should be used.">;
50
51def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
52        "R600ALUInst",
53        "false",
54        "Older version of ALU instructions encoding.">;
55
56def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
57        "HasVertexCache",
58        "true",
59        "Specify use of dedicated vertex cache.">;
60
61def FeatureCaymanISA : SubtargetFeature<"caymanISA",
62        "CaymanISA",
63        "true",
64        "Use Cayman ISA">;
65
66class SubtargetFeatureFetchLimit <string Value> :
67                          SubtargetFeature <"fetch"#Value,
68        "TexVTXClauseSize",
69        Value,
70        "Limit the maximum number of fetches in a clause to "#Value>;
71
72def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
73def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
74
75class SubtargetFeatureGeneration <string Value,
76                                  list<SubtargetFeature> Implies> :
77        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
78                          Value#" GPU generation", Implies>;
79
80def FeatureR600 : SubtargetFeatureGeneration<"R600",
81        [FeatureR600ALUInst, FeatureFetchLimit8]>;
82
83def FeatureR700 : SubtargetFeatureGeneration<"R700",
84        [FeatureFetchLimit16]>;
85
86def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
87        [FeatureFetchLimit16]>;
88
89def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
90        [FeatureFetchLimit16]>;
91
92def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
93        [Feature64BitPtr, FeatureFP64]>;
94
95def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
96        [Feature64BitPtr, FeatureFP64]>;
97//===----------------------------------------------------------------------===//
98
99def AMDGPUInstrInfo : InstrInfo {
100  let guessInstructionProperties = 1;
101}
102
103//===----------------------------------------------------------------------===//
104// Declare the target which we are implementing
105//===----------------------------------------------------------------------===//
106def AMDGPUAsmWriter : AsmWriter {
107    string AsmWriterClassName = "InstPrinter";
108    int Variant = 0;
109    bit isMCAsmWriter = 1;
110}
111
112def AMDGPU : Target {
113  // Pull in Instruction Info:
114  let InstructionSet = AMDGPUInstrInfo;
115  let AssemblyWriters = [AMDGPUAsmWriter];
116}
117
118// Include AMDGPU TD files
119include "R600Schedule.td"
120include "SISchedule.td"
121include "Processors.td"
122include "AMDGPUInstrInfo.td"
123include "AMDGPUIntrinsics.td"
124include "AMDGPURegisterInfo.td"
125include "AMDGPUInstructions.td"
126include "AMDGPUCallingConv.td"
127