1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains DAG node defintions for the AMDGPU target. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// AMDGPU DAG Profiles 16//===----------------------------------------------------------------------===// 17 18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [ 19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 20]>; 21 22def AMDGPUTrigPreOp : SDTypeProfile<1, 2, 23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>] 24>; 25 26def AMDGPULdExpOp : SDTypeProfile<1, 2, 27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>] 28>; 29 30def AMDGPUFPClassOp : SDTypeProfile<1, 2, 31 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>] 32>; 33 34def AMDGPUDivScaleOp : SDTypeProfile<2, 3, 35 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>] 36>; 37 38// float, float, float, vcc 39def AMDGPUFmasOp : SDTypeProfile<1, 4, 40 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>] 41>; 42 43//===----------------------------------------------------------------------===// 44// AMDGPU DAG Nodes 45// 46 47// This argument to this node is a dword address. 48def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>; 49 50def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>; 51def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>; 52 53// out = a - floor(a) 54def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>; 55 56// out = 1.0 / a 57def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>; 58 59// out = 1.0 / sqrt(a) 60def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>; 61 62// out = 1.0 / sqrt(a) 63def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>; 64 65// out = 1.0 / sqrt(a) result clamped to +/- max_float. 66def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>; 67 68def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>; 69 70def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>; 71 72// out = max(a, b) a and b are floats, where a nan comparison fails. 73// This is not commutative because this gives the second operand: 74// x < nan ? x : nan -> nan 75// nan < x ? nan : x -> x 76def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp, 77 [] 78>; 79 80def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>; 81def AMDGPUmad : SDNode<"AMDGPUISD::MAD", SDTFPTernaryOp, []>; 82 83// out = max(a, b) a and b are signed ints 84def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp, 85 [SDNPCommutative, SDNPAssociative] 86>; 87 88// out = max(a, b) a and b are unsigned ints 89def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp, 90 [SDNPCommutative, SDNPAssociative] 91>; 92 93// out = min(a, b) a and b are floats, where a nan comparison fails. 94def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp, 95 [] 96>; 97 98// out = min(a, b) a and b are signed ints 99def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp, 100 [SDNPCommutative, SDNPAssociative] 101>; 102 103// out = min(a, b) a and b are unsigned ints 104def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp, 105 [SDNPCommutative, SDNPAssociative] 106>; 107 108// FIXME: TableGen doesn't like commutative instructions with more 109// than 2 operands. 110// out = max(a, b, c) a, b and c are floats 111def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp, 112 [/*SDNPCommutative, SDNPAssociative*/] 113>; 114 115// out = max(a, b, c) a, b, and c are signed ints 116def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp, 117 [/*SDNPCommutative, SDNPAssociative*/] 118>; 119 120// out = max(a, b, c) a, b and c are unsigned ints 121def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp, 122 [/*SDNPCommutative, SDNPAssociative*/] 123>; 124 125// out = min(a, b, c) a, b and c are floats 126def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp, 127 [/*SDNPCommutative, SDNPAssociative*/] 128>; 129 130// out = min(a, b, c) a, b and c are signed ints 131def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp, 132 [/*SDNPCommutative, SDNPAssociative*/] 133>; 134 135// out = min(a, b) a and b are unsigned ints 136def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp, 137 [/*SDNPCommutative, SDNPAssociative*/] 138>; 139 140def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0", 141 SDTIntToFPOp, []>; 142def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1", 143 SDTIntToFPOp, []>; 144def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2", 145 SDTIntToFPOp, []>; 146def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3", 147 SDTIntToFPOp, []>; 148 149 150// urecip - This operation is a helper for integer division, it returns the 151// result of 1 / a as a fractional unsigned integer. 152// out = (2^32 / a) + e 153// e is rounding error 154def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>; 155 156// Special case divide preop and flags. 157def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>; 158 159// Special case divide FMA with scale and flags (src0 = Quotient, 160// src1 = Denominator, src2 = Numerator). 161def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>; 162 163// Single or double precision division fixup. 164// Special case divide fixup and flags(src0 = Quotient, src1 = 165// Denominator, src2 = Numerator). 166def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>; 167 168// Look Up 2.0 / pi src0 with segment select src1[4:0] 169def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>; 170 171def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD", 172 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 173 [SDNPHasChain, SDNPMayLoad]>; 174 175def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE", 176 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 177 [SDNPHasChain, SDNPMayStore]>; 178 179// MSKOR instructions are atomic memory instructions used mainly for storing 180// 8-bit and 16-bit values. The definition is: 181// 182// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src) 183// 184// src0: vec4(src, 0, 0, mask) 185// src1: dst - rat offset (aka pointer) in dwords 186def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR", 187 SDTypeProfile<0, 2, []>, 188 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 189 190def AMDGPUround : SDNode<"ISD::FROUND", 191 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>; 192 193def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>; 194def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>; 195def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>; 196def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>; 197 198def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>; 199 200// Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when 201// performing the mulitply. The result is a 32-bit value. 202def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp, 203 [SDNPCommutative] 204>; 205def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp, 206 [SDNPCommutative] 207>; 208 209def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp, 210 [] 211>; 212def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp, 213 [] 214>; 215 216//===----------------------------------------------------------------------===// 217// Flow Control Profile Types 218//===----------------------------------------------------------------------===// 219// Branch instruction where second and third are basic blocks 220def SDTIL_BRCond : SDTypeProfile<0, 2, [ 221 SDTCisVT<0, OtherVT> 222 ]>; 223 224//===----------------------------------------------------------------------===// 225// Flow Control DAG Nodes 226//===----------------------------------------------------------------------===// 227def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; 228 229//===----------------------------------------------------------------------===// 230// Call/Return DAG Nodes 231//===----------------------------------------------------------------------===// 232def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone, 233 [SDNPHasChain, SDNPOptInGlue]>; 234