1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIISelLowering.h"
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/CodeGen/MachineScheduler.h"
24
25 using namespace llvm;
26
27 #define DEBUG_TYPE "amdgpu-subtarget"
28
29 #define GET_SUBTARGETINFO_ENUM
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "AMDGPUGenSubtargetInfo.inc"
33
computeDataLayout(const AMDGPUSubtarget & ST)34 static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
35 std::string Ret = "e-p:32:32";
36
37 if (ST.is64bit()) {
38 // 32-bit private, local, and region pointers. 64-bit global and constant.
39 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
40 }
41
42 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
43 "-v512:512-v1024:1024-v2048:2048-n32:64";
44
45 return Ret;
46 }
47
48 AMDGPUSubtarget &
initializeSubtargetDependencies(StringRef GPU,StringRef FS)49 AMDGPUSubtarget::initializeSubtargetDependencies(StringRef GPU, StringRef FS) {
50 // Determine default and user-specified characteristics
51 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
52 // enabled, but some instructions do not respect them and they run at the
53 // double precision rate, so don't enable by default.
54 //
55 // We want to be able to turn these off, but making this a subtarget feature
56 // for SI has the unhelpful behavior that it unsets everything else if you
57 // disable it.
58
59 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
60 FullFS += FS;
61
62 ParseSubtargetFeatures(GPU, FullFS);
63
64 // FIXME: I don't think think Evergreen has any useful support for
65 // denormals, but should be checked. Should we issue a warning somewhere
66 // if someone tries to enable these?
67 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
68 FP32Denormals = false;
69 FP64Denormals = false;
70 }
71 return *this;
72 }
73
AMDGPUSubtarget(StringRef TT,StringRef GPU,StringRef FS,TargetMachine & TM)74 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
75 TargetMachine &TM)
76 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
77 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
78 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
79 FP64Denormals(false), FP32Denormals(false), CaymanISA(false),
80 FlatAddressSpace(false), EnableIRStructurizer(true),
81 EnablePromoteAlloca(false), EnableIfCvt(true),
82 EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
83 EnableVGPRSpilling(false),SGPRInitBug(false),
84 DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),
85 FrameLowering(TargetFrameLowering::StackGrowsUp,
86 64 * 16, // Maximum stack alignment (long16)
87 0),
88 InstrItins(getInstrItineraryForCPU(GPU)),
89 TargetTriple(TT) {
90 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
91 InstrInfo.reset(new R600InstrInfo(*this));
92 TLInfo.reset(new R600TargetLowering(TM));
93 } else {
94 InstrInfo.reset(new SIInstrInfo(*this));
95 TLInfo.reset(new SITargetLowering(TM));
96 }
97 }
98
getStackEntrySize() const99 unsigned AMDGPUSubtarget::getStackEntrySize() const {
100 assert(getGeneration() <= NORTHERN_ISLANDS);
101 switch(getWavefrontSize()) {
102 case 16:
103 return 8;
104 case 32:
105 return hasCaymanISA() ? 4 : 8;
106 case 64:
107 return 4;
108 default:
109 llvm_unreachable("Illegal wavefront size.");
110 }
111 }
112
getAmdKernelCodeChipID() const113 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
114 switch(getGeneration()) {
115 default: llvm_unreachable("ChipID unknown");
116 case SEA_ISLANDS: return 12;
117 }
118 }
119
isVGPRSpillingEnabled(const SIMachineFunctionInfo * MFI) const120 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
121 const SIMachineFunctionInfo *MFI) const {
122 return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
123 }
124
overrideSchedPolicy(MachineSchedPolicy & Policy,MachineInstr * begin,MachineInstr * end,unsigned NumRegionInstrs) const125 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
126 MachineInstr *begin,
127 MachineInstr *end,
128 unsigned NumRegionInstrs) const {
129 if (getGeneration() >= SOUTHERN_ISLANDS) {
130
131 // Track register pressure so the scheduler can try to decrease
132 // pressure once register usage is above the threshold defined by
133 // SIRegisterInfo::getRegPressureSetLimit()
134 Policy.ShouldTrackPressure = true;
135
136 // Enabling both top down and bottom up scheduling seems to give us less
137 // register spills than just using one of these approaches on its own.
138 Policy.OnlyTopDown = false;
139 Policy.OnlyBottomUp = false;
140 }
141 }
142