1set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
2
3tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
4tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
5tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
6tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
7tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
8tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
9tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
10tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
11tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
12tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
13add_public_tablegen_target(AMDGPUCommonTableGen)
14
15add_llvm_target(R600CodeGen
16  AMDILCFGStructurizer.cpp
17  AMDGPUAlwaysInlinePass.cpp
18  AMDGPUAsmPrinter.cpp
19  AMDGPUFrameLowering.cpp
20  AMDGPUIntrinsicInfo.cpp
21  AMDGPUISelDAGToDAG.cpp
22  AMDGPUMCInstLower.cpp
23  AMDGPUMachineFunction.cpp
24  AMDGPUSubtarget.cpp
25  AMDGPUTargetMachine.cpp
26  AMDGPUTargetTransformInfo.cpp
27  AMDGPUISelLowering.cpp
28  AMDGPUInstrInfo.cpp
29  AMDGPUPromoteAlloca.cpp
30  AMDGPURegisterInfo.cpp
31  R600ClauseMergePass.cpp
32  R600ControlFlowFinalizer.cpp
33  R600EmitClauseMarkers.cpp
34  R600ExpandSpecialInstrs.cpp
35  R600InstrInfo.cpp
36  R600ISelLowering.cpp
37  R600MachineFunctionInfo.cpp
38  R600MachineScheduler.cpp
39  R600OptimizeVectorRegisters.cpp
40  R600Packetizer.cpp
41  R600RegisterInfo.cpp
42  R600TextureIntrinsicsReplacer.cpp
43  SIAnnotateControlFlow.cpp
44  SIFixSGPRCopies.cpp
45  SIFixSGPRLiveRanges.cpp
46  SIFoldOperands.cpp
47  SIInsertWaits.cpp
48  SIInstrInfo.cpp
49  SIISelLowering.cpp
50  SILoadStoreOptimizer.cpp
51  SILowerControlFlow.cpp
52  SILowerI1Copies.cpp
53  SIMachineFunctionInfo.cpp
54  SIPrepareScratchRegs.cpp
55  SIRegisterInfo.cpp
56  SIShrinkInstructions.cpp
57  SITypeRewriter.cpp
58  )
59
60add_subdirectory(AsmParser)
61add_subdirectory(InstPrinter)
62add_subdirectory(TargetInfo)
63add_subdirectory(MCTargetDesc)
64