1//===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen definitions for instructions which are available only on Cayman 11// family GPUs. 12// 13//===----------------------------------------------------------------------===// 14 15def isCayman : Predicate<"Subtarget.hasCaymanISA()">; 16 17//===----------------------------------------------------------------------===// 18// Cayman Instructions 19//===----------------------------------------------------------------------===// 20 21let Predicates = [isCayman] in { 22 23def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24", 24 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU 25>; 26def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24", 27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU 28>; 29 30def : IMad24Pat<MULADD_INT24_cm>; 31 32let isVector = 1 in { 33 34def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 35 36def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 37def MULHI_INT_cm : MULHI_INT_Common<0x90>; 38def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 39def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 40def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>; 41def EXP_IEEE_cm : EXP_IEEE_Common<0x81>; 42def LOG_IEEE_cm : LOG_IEEE_Common<0x83>; 43def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>; 44def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>; 45def SIN_cm : SIN_Common<0x8D>; 46def COS_cm : COS_Common<0x8E>; 47} // End isVector = 1 48 49def : RsqPat<RECIPSQRT_IEEE_cm, f32>; 50 51def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>; 52 53defm DIV_cm : DIV_Common<RECIP_IEEE_cm>; 54defm : Expand24UBitOps<MULLO_UINT_cm, ADD_INT>; 55 56// RECIP_UINT emulation for Cayman 57// The multiplication scales from [0,1] to the unsigned integer range 58def : Pat < 59 (AMDGPUurecip i32:$src0), 60 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)), 61 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1))) 62>; 63 64 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> { 65 let ADDR = 0; 66 let POP_COUNT = 0; 67 let COUNT = 0; 68 } 69 70 71def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>; 72 73class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> : 74 CF_MEM_RAT_CACHELESS <0x14, 0, mask, 75 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr), 76 "STORE_DWORD $rw_gpr, $index_gpr", 77 [(global_store vt:$rw_gpr, i32:$index_gpr)]> { 78 let eop = 0; // This bit is not used on Cayman. 79} 80 81def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>; 82def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>; 83def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>; 84 85class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 86 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> { 87 88 // Static fields 89 let VC_INST = 0; 90 let FETCH_TYPE = 2; 91 let FETCH_WHOLE_QUAD = 0; 92 let BUFFER_ID = buffer_id; 93 let SRC_REL = 0; 94 // XXX: We can infer this field based on the SRC_GPR. This would allow us 95 // to store vertex addresses in any channel, not just X. 96 let SRC_SEL_X = 0; 97 let SRC_SEL_Y = 0; 98 let STRUCTURED_READ = 0; 99 let LDS_REQ = 0; 100 let COALESCED_READ = 0; 101 102 let Inst{31-0} = Word0; 103} 104 105class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern> 106 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 107 (outs R600_TReg32_X:$dst_gpr), pattern> { 108 109 let DST_SEL_X = 0; 110 let DST_SEL_Y = 7; // Masked 111 let DST_SEL_Z = 7; // Masked 112 let DST_SEL_W = 7; // Masked 113 let DATA_FORMAT = 1; // FMT_8 114} 115 116class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern> 117 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 118 (outs R600_TReg32_X:$dst_gpr), pattern> { 119 let DST_SEL_X = 0; 120 let DST_SEL_Y = 7; // Masked 121 let DST_SEL_Z = 7; // Masked 122 let DST_SEL_W = 7; // Masked 123 let DATA_FORMAT = 5; // FMT_16 124 125} 126 127class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern> 128 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 129 (outs R600_TReg32_X:$dst_gpr), pattern> { 130 131 let DST_SEL_X = 0; 132 let DST_SEL_Y = 7; // Masked 133 let DST_SEL_Z = 7; // Masked 134 let DST_SEL_W = 7; // Masked 135 let DATA_FORMAT = 0xD; // COLOR_32 136 137 // This is not really necessary, but there were some GPU hangs that appeared 138 // to be caused by ALU instructions in the next instruction group that wrote 139 // to the $src_gpr registers of the VTX_READ. 140 // e.g. 141 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 142 // %T2_X<def> = MOV %ZERO 143 //Adding this constraint prevents this from happening. 144 let Constraints = "$src_gpr.ptr = $dst_gpr"; 145} 146 147class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern> 148 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id, 149 (outs R600_Reg64:$dst_gpr), pattern> { 150 151 let DST_SEL_X = 0; 152 let DST_SEL_Y = 1; 153 let DST_SEL_Z = 7; 154 let DST_SEL_W = 7; 155 let DATA_FORMAT = 0x1D; // COLOR_32_32 156} 157 158class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern> 159 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 160 (outs R600_Reg128:$dst_gpr), pattern> { 161 162 let DST_SEL_X = 0; 163 let DST_SEL_Y = 1; 164 let DST_SEL_Z = 2; 165 let DST_SEL_W = 3; 166 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 167 168 // XXX: Need to force VTX_READ_128 instructions to write to the same register 169 // that holds its buffer address to avoid potential hangs. We can't use 170 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 171 // registers are different sizes. 172} 173 174//===----------------------------------------------------------------------===// 175// VTX Read from parameter memory space 176//===----------------------------------------------------------------------===// 177def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0, 178 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 179>; 180 181def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0, 182 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 183>; 184 185def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0, 186 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 187>; 188 189def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0, 190 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 191>; 192 193def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0, 194 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 195>; 196 197//===----------------------------------------------------------------------===// 198// VTX Read from global memory space 199//===----------------------------------------------------------------------===// 200 201// 8-bit reads 202def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1, 203 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] 204>; 205 206def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1, 207 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] 208>; 209 210// 32-bit reads 211def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1, 212 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 213>; 214 215// 64-bit reads 216def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1, 217 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 218>; 219 220// 128-bit reads 221def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1, 222 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 223>; 224 225} // End isCayman 226 227