1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This file provides AMDGPU specific target descriptions.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "InstPrinter/AMDGPUInstPrinter.h"
18 #include "SIDefines.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MachineLocation.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27
28 using namespace llvm;
29
30 #define GET_INSTRINFO_MC_DESC
31 #include "AMDGPUGenInstrInfo.inc"
32
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "AMDGPUGenSubtargetInfo.inc"
35
36 #define GET_REGINFO_MC_DESC
37 #include "AMDGPUGenRegisterInfo.inc"
38
createAMDGPUMCInstrInfo()39 static MCInstrInfo *createAMDGPUMCInstrInfo() {
40 MCInstrInfo *X = new MCInstrInfo();
41 InitAMDGPUMCInstrInfo(X);
42 return X;
43 }
44
createAMDGPUMCRegisterInfo(StringRef TT)45 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
46 MCRegisterInfo *X = new MCRegisterInfo();
47 InitAMDGPUMCRegisterInfo(X, 0);
48 return X;
49 }
50
createAMDGPUMCSubtargetInfo(StringRef TT,StringRef CPU,StringRef FS)51 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
52 StringRef FS) {
53 MCSubtargetInfo * X = new MCSubtargetInfo();
54 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
55 return X;
56 }
57
createAMDGPUMCCodeGenInfo(StringRef TT,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)58 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
59 CodeModel::Model CM,
60 CodeGenOpt::Level OL) {
61 MCCodeGenInfo *X = new MCCodeGenInfo();
62 X->InitMCCodeGenInfo(RM, CM, OL);
63 return X;
64 }
65
createAMDGPUMCInstPrinter(const Target & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI,const MCSubtargetInfo & STI)66 static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
67 unsigned SyntaxVariant,
68 const MCAsmInfo &MAI,
69 const MCInstrInfo &MII,
70 const MCRegisterInfo &MRI,
71 const MCSubtargetInfo &STI) {
72 return new AMDGPUInstPrinter(MAI, MII, MRI);
73 }
74
createAMDGPUMCCodeEmitter(const MCInstrInfo & MCII,const MCRegisterInfo & MRI,const MCSubtargetInfo & STI,MCContext & Ctx)75 static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
76 const MCRegisterInfo &MRI,
77 const MCSubtargetInfo &STI,
78 MCContext &Ctx) {
79 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
80 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
81 } else {
82 return createR600MCCodeEmitter(MCII, MRI, STI);
83 }
84 }
85
createMCStreamer(const Target & T,StringRef TT,MCContext & Ctx,MCAsmBackend & MAB,raw_ostream & _OS,MCCodeEmitter * _Emitter,const MCSubtargetInfo & STI,bool RelaxAll)86 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
87 MCContext &Ctx, MCAsmBackend &MAB,
88 raw_ostream &_OS, MCCodeEmitter *_Emitter,
89 const MCSubtargetInfo &STI, bool RelaxAll) {
90 return createELFStreamer(Ctx, MAB, _OS, _Emitter, false);
91 }
92
LLVMInitializeR600TargetMC()93 extern "C" void LLVMInitializeR600TargetMC() {
94
95 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget);
96 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Z(TheGCNTarget);
97
98 TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
99 TargetRegistry::RegisterMCCodeGenInfo(TheGCNTarget, createAMDGPUMCCodeGenInfo);
100
101 TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
102 TargetRegistry::RegisterMCInstrInfo(TheGCNTarget, createAMDGPUMCInstrInfo);
103
104 TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
105 TargetRegistry::RegisterMCRegInfo(TheGCNTarget, createAMDGPUMCRegisterInfo);
106
107 TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
108 TargetRegistry::RegisterMCSubtargetInfo(TheGCNTarget, createAMDGPUMCSubtargetInfo);
109
110 TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter);
111 TargetRegistry::RegisterMCInstPrinter(TheGCNTarget, createAMDGPUMCInstPrinter);
112
113 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter);
114 TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createAMDGPUMCCodeEmitter);
115
116 TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend);
117 TargetRegistry::RegisterMCAsmBackend(TheGCNTarget, createAMDGPUAsmBackend);
118
119 TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer);
120 TargetRegistry::RegisterMCObjectStreamer(TheGCNTarget, createMCStreamer);
121 }
122