1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Machine Scheduler interface
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef R600MACHINESCHEDULER_H_
16 #define R600MACHINESCHEDULER_H_
17 
18 #include "R600InstrInfo.h"
19 #include "llvm/ADT/PriorityQueue.h"
20 #include "llvm/CodeGen/MachineScheduler.h"
21 #include "llvm/Support/Debug.h"
22 
23 using namespace llvm;
24 
25 namespace llvm {
26 
27 class R600SchedStrategy : public MachineSchedStrategy {
28 
29   const ScheduleDAGMI *DAG;
30   const R600InstrInfo *TII;
31   const R600RegisterInfo *TRI;
32   MachineRegisterInfo *MRI;
33 
34   enum InstKind {
35     IDAlu,
36     IDFetch,
37     IDOther,
38     IDLast
39   };
40 
41   enum AluKind {
42     AluAny,
43     AluT_X,
44     AluT_Y,
45     AluT_Z,
46     AluT_W,
47     AluT_XYZW,
48     AluPredX,
49     AluTrans,
50     AluDiscarded, // LLVM Instructions that are going to be eliminated
51     AluLast
52   };
53 
54   std::vector<SUnit *> Available[IDLast], Pending[IDLast];
55   std::vector<SUnit *> AvailableAlus[AluLast];
56   std::vector<SUnit *> PhysicalRegCopy;
57 
58   InstKind CurInstKind;
59   int CurEmitted;
60   InstKind NextInstKind;
61 
62   unsigned AluInstCount;
63   unsigned FetchInstCount;
64 
65   int InstKindLimit[IDLast];
66 
67   int OccupedSlotsMask;
68 
69 public:
70   R600SchedStrategy() :
71     DAG(0), TII(0), TRI(0), MRI(0) {
72   }
73 
74   virtual ~R600SchedStrategy() {
75   }
76 
77   virtual void initialize(ScheduleDAGMI *dag);
78   virtual SUnit *pickNode(bool &IsTopNode);
79   virtual void schedNode(SUnit *SU, bool IsTopNode);
80   virtual void releaseTopNode(SUnit *SU);
81   virtual void releaseBottomNode(SUnit *SU);
82 
83 private:
84   std::vector<MachineInstr *> InstructionsGroupCandidate;
85   bool VLIW5;
86 
87   int getInstKind(SUnit *SU);
88   bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
89   AluKind getAluKind(SUnit *SU) const;
90   void LoadAlu();
91   unsigned AvailablesAluCount() const;
92   SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
93   void PrepareNextSlot();
94   SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
95 
96   void AssignSlot(MachineInstr *MI, unsigned Slot);
97   SUnit* pickAlu();
98   SUnit* pickOther(int QID);
99   void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
100 };
101 
102 } // namespace llvm
103 
104 #endif /* R600MACHINESCHEDULER_H_ */
105