1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #include "llvm/MC/MCInstrDesc.h"
12 
13 #ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H
14 #define LLVM_LIB_TARGET_R600_SIDEFINES_H
15 
16 namespace SIInstrFlags {
17 // This needs to be kept in sync with the field bits in InstSI.
18 enum {
19   SALU = 1 << 3,
20   VALU = 1 << 4,
21 
22   SOP1 = 1 << 5,
23   SOP2 = 1 << 6,
24   SOPC = 1 << 7,
25   SOPK = 1 << 8,
26   SOPP = 1 << 9,
27 
28   VOP1 = 1 << 10,
29   VOP2 = 1 << 11,
30   VOP3 = 1 << 12,
31   VOPC = 1 << 13,
32 
33   MUBUF = 1 << 14,
34   MTBUF = 1 << 15,
35   SMRD = 1 << 16,
36   DS = 1 << 17,
37   MIMG = 1 << 18,
38   FLAT = 1 << 19,
39   WQM = 1 << 20
40 };
41 }
42 
43 namespace llvm {
44 namespace AMDGPU {
45   enum OperandType {
46     /// Operand with register or 32-bit immediate
47     OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET,
48     /// Operand with register or inline constant
49     OPERAND_REG_INLINE_C
50   };
51 }
52 }
53 
54 namespace SIInstrFlags {
55   enum Flags {
56     // First 4 bits are the instruction encoding
57     VM_CNT = 1 << 0,
58     EXP_CNT = 1 << 1,
59     LGKM_CNT = 1 << 2
60   };
61 
62   // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
63   // The result is true if any of these tests are true.
64   enum ClassFlags {
65     S_NAN = 1 << 0,        // Signaling NaN
66     Q_NAN = 1 << 1,        // Quiet NaN
67     N_INFINITY = 1 << 2,   // Negative infinity
68     N_NORMAL = 1 << 3,     // Negative normal
69     N_SUBNORMAL = 1 << 4,  // Negative subnormal
70     N_ZERO = 1 << 5,       // Negative zero
71     P_ZERO = 1 << 6,       // Positive zero
72     P_SUBNORMAL = 1 << 7,  // Positive subnormal
73     P_NORMAL = 1 << 8,     // Positive normal
74     P_INFINITY = 1 << 9    // Positive infinity
75   };
76 }
77 
78 namespace SISrcMods {
79   enum {
80    NEG = 1 << 0,
81    ABS = 1 << 1
82   };
83 }
84 
85 namespace SIOutMods {
86   enum {
87     NONE = 0,
88     MUL2 = 1,
89     MUL4 = 2,
90     DIV2 = 3
91   };
92 }
93 
94 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
95 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
96 #define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
97 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
98 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
99 #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
100 #define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
101 #define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
102 #define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
103 #define   S_00B84C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
104 #define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
105 #define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
106 #define   S_00B84C_TGID_Y_EN(x)                                       (((x) & 0x1) << 8)
107 #define   S_00B84C_TGID_Z_EN(x)                                       (((x) & 0x1) << 9)
108 #define   S_00B84C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 10)
109 #define   S_00B84C_TIDIG_COMP_CNT(x)                                  (((x) & 0x03) << 11)
110 
111 #define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
112 #define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC
113 
114 
115 #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
116 #define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
117 #define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
118 #define   C_00B848_VGPRS                                              0xFFFFFFC0
119 #define   S_00B848_SGPRS(x)                                           (((x) & 0x0F) << 6)
120 #define   G_00B848_SGPRS(x)                                           (((x) >> 6) & 0x0F)
121 #define   C_00B848_SGPRS                                              0xFFFFFC3F
122 #define   S_00B848_PRIORITY(x)                                        (((x) & 0x03) << 10)
123 #define   G_00B848_PRIORITY(x)                                        (((x) >> 10) & 0x03)
124 #define   C_00B848_PRIORITY                                           0xFFFFF3FF
125 #define   S_00B848_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
126 #define   G_00B848_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
127 #define   C_00B848_FLOAT_MODE                                         0xFFF00FFF
128 #define   S_00B848_PRIV(x)                                            (((x) & 0x1) << 20)
129 #define   G_00B848_PRIV(x)                                            (((x) >> 20) & 0x1)
130 #define   C_00B848_PRIV                                               0xFFEFFFFF
131 #define   S_00B848_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
132 #define   G_00B848_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
133 #define   C_00B848_DX10_CLAMP                                         0xFFDFFFFF
134 #define   S_00B848_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
135 #define   G_00B848_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
136 #define   C_00B848_DEBUG_MODE                                         0xFFBFFFFF
137 #define   S_00B848_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
138 #define   G_00B848_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
139 #define   C_00B848_IEEE_MODE                                          0xFF7FFFFF
140 
141 
142 // Helpers for setting FLOAT_MODE
143 #define FP_ROUND_ROUND_TO_NEAREST 0
144 #define FP_ROUND_ROUND_TO_INF 1
145 #define FP_ROUND_ROUND_TO_NEGINF 2
146 #define FP_ROUND_ROUND_TO_ZERO 3
147 
148 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
149 // precision.
150 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
151 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
152 
153 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
154 #define FP_DENORM_FLUSH_OUT 1
155 #define FP_DENORM_FLUSH_IN 2
156 #define FP_DENORM_FLUSH_NONE 3
157 
158 
159 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
160 // precision.
161 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
162 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
163 
164 #define R_00B860_COMPUTE_TMPRING_SIZE                                   0x00B860
165 #define   S_00B860_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
166 
167 #define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
168 #define   S_0286E8_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
169 
170 
171 #endif
172