1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief SI Implementation of TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14
15
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
27
28 using namespace llvm;
29
SIInstrInfo(const AMDGPUSubtarget & st)30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st),
32 RI(st) { }
33
34 //===----------------------------------------------------------------------===//
35 // TargetInstrInfo callbacks
36 //===----------------------------------------------------------------------===//
37
getNumOperandsNoGlue(SDNode * Node)38 static unsigned getNumOperandsNoGlue(SDNode *Node) {
39 unsigned N = Node->getNumOperands();
40 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
41 --N;
42 return N;
43 }
44
findChainOperand(SDNode * Load)45 static SDValue findChainOperand(SDNode *Load) {
46 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
47 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
48 return LastOp;
49 }
50
51 /// \brief Returns true if both nodes have the same value for the given
52 /// operand \p Op, or if both nodes do not have this operand.
nodesHaveSameOperandValue(SDNode * N0,SDNode * N1,unsigned OpName)53 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
54 unsigned Opc0 = N0->getMachineOpcode();
55 unsigned Opc1 = N1->getMachineOpcode();
56
57 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
58 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59
60 if (Op0Idx == -1 && Op1Idx == -1)
61 return true;
62
63
64 if ((Op0Idx == -1 && Op1Idx != -1) ||
65 (Op1Idx == -1 && Op0Idx != -1))
66 return false;
67
68 // getNamedOperandIdx returns the index for the MachineInstr's operands,
69 // which includes the result as the first operand. We are indexing into the
70 // MachineSDNode's operands, so we need to skip the result operand to get
71 // the real index.
72 --Op0Idx;
73 --Op1Idx;
74
75 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
76 }
77
areLoadsFromSameBasePtr(SDNode * Load0,SDNode * Load1,int64_t & Offset0,int64_t & Offset1) const78 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset0,
80 int64_t &Offset1) const {
81 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
82 return false;
83
84 unsigned Opc0 = Load0->getMachineOpcode();
85 unsigned Opc1 = Load1->getMachineOpcode();
86
87 // Make sure both are actually loads.
88 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
89 return false;
90
91 if (isDS(Opc0) && isDS(Opc1)) {
92
93 // FIXME: Handle this case:
94 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
95 return false;
96
97 // Check base reg.
98 if (Load0->getOperand(1) != Load1->getOperand(1))
99 return false;
100
101 // Check chain.
102 if (findChainOperand(Load0) != findChainOperand(Load1))
103 return false;
104
105 // Skip read2 / write2 variants for simplicity.
106 // TODO: We should report true if the used offsets are adjacent (excluded
107 // st64 versions).
108 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
109 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
110 return false;
111
112 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
113 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
114 return true;
115 }
116
117 if (isSMRD(Opc0) && isSMRD(Opc1)) {
118 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
119
120 // Check base reg.
121 if (Load0->getOperand(0) != Load1->getOperand(0))
122 return false;
123
124 const ConstantSDNode *Load0Offset =
125 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
126 const ConstantSDNode *Load1Offset =
127 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
128
129 if (!Load0Offset || !Load1Offset)
130 return false;
131
132 // Check chain.
133 if (findChainOperand(Load0) != findChainOperand(Load1))
134 return false;
135
136 Offset0 = Load0Offset->getZExtValue();
137 Offset1 = Load1Offset->getZExtValue();
138 return true;
139 }
140
141 // MUBUF and MTBUF can access the same addresses.
142 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
143
144 // MUBUF and MTBUF have vaddr at different indices.
145 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
146 findChainOperand(Load0) != findChainOperand(Load1) ||
147 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
148 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
149 return false;
150
151 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
152 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
153
154 if (OffIdx0 == -1 || OffIdx1 == -1)
155 return false;
156
157 // getNamedOperandIdx returns the index for MachineInstrs. Since they
158 // inlcude the output in the operand list, but SDNodes don't, we need to
159 // subtract the index by one.
160 --OffIdx0;
161 --OffIdx1;
162
163 SDValue Off0 = Load0->getOperand(OffIdx0);
164 SDValue Off1 = Load1->getOperand(OffIdx1);
165
166 // The offset might be a FrameIndexSDNode.
167 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
168 return false;
169
170 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
171 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
172 return true;
173 }
174
175 return false;
176 }
177
isStride64(unsigned Opc)178 static bool isStride64(unsigned Opc) {
179 switch (Opc) {
180 case AMDGPU::DS_READ2ST64_B32:
181 case AMDGPU::DS_READ2ST64_B64:
182 case AMDGPU::DS_WRITE2ST64_B32:
183 case AMDGPU::DS_WRITE2ST64_B64:
184 return true;
185 default:
186 return false;
187 }
188 }
189
getLdStBaseRegImmOfs(MachineInstr * LdSt,unsigned & BaseReg,unsigned & Offset,const TargetRegisterInfo * TRI) const190 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
191 unsigned &BaseReg, unsigned &Offset,
192 const TargetRegisterInfo *TRI) const {
193 unsigned Opc = LdSt->getOpcode();
194 if (isDS(Opc)) {
195 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
196 AMDGPU::OpName::offset);
197 if (OffsetImm) {
198 // Normal, single offset LDS instruction.
199 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
200 AMDGPU::OpName::addr);
201
202 BaseReg = AddrReg->getReg();
203 Offset = OffsetImm->getImm();
204 return true;
205 }
206
207 // The 2 offset instructions use offset0 and offset1 instead. We can treat
208 // these as a load with a single offset if the 2 offsets are consecutive. We
209 // will use this for some partially aligned loads.
210 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
211 AMDGPU::OpName::offset0);
212 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
213 AMDGPU::OpName::offset1);
214
215 uint8_t Offset0 = Offset0Imm->getImm();
216 uint8_t Offset1 = Offset1Imm->getImm();
217 assert(Offset1 > Offset0);
218
219 if (Offset1 - Offset0 == 1) {
220 // Each of these offsets is in element sized units, so we need to convert
221 // to bytes of the individual reads.
222
223 unsigned EltSize;
224 if (LdSt->mayLoad())
225 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
226 else {
227 assert(LdSt->mayStore());
228 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
229 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
230 }
231
232 if (isStride64(Opc))
233 EltSize *= 64;
234
235 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
236 AMDGPU::OpName::addr);
237 BaseReg = AddrReg->getReg();
238 Offset = EltSize * Offset0;
239 return true;
240 }
241
242 return false;
243 }
244
245 if (isMUBUF(Opc) || isMTBUF(Opc)) {
246 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
247 return false;
248
249 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
250 AMDGPU::OpName::vaddr);
251 if (!AddrReg)
252 return false;
253
254 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
255 AMDGPU::OpName::offset);
256 BaseReg = AddrReg->getReg();
257 Offset = OffsetImm->getImm();
258 return true;
259 }
260
261 if (isSMRD(Opc)) {
262 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
263 AMDGPU::OpName::offset);
264 if (!OffsetImm)
265 return false;
266
267 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
268 AMDGPU::OpName::sbase);
269 BaseReg = SBaseReg->getReg();
270 Offset = OffsetImm->getImm();
271 return true;
272 }
273
274 return false;
275 }
276
shouldClusterLoads(MachineInstr * FirstLdSt,MachineInstr * SecondLdSt,unsigned NumLoads) const277 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
278 MachineInstr *SecondLdSt,
279 unsigned NumLoads) const {
280 unsigned Opc0 = FirstLdSt->getOpcode();
281 unsigned Opc1 = SecondLdSt->getOpcode();
282
283 // TODO: This needs finer tuning
284 if (NumLoads > 4)
285 return false;
286
287 if (isDS(Opc0) && isDS(Opc1))
288 return true;
289
290 if (isSMRD(Opc0) && isSMRD(Opc1))
291 return true;
292
293 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
294 return true;
295
296 return false;
297 }
298
299 void
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const300 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
301 MachineBasicBlock::iterator MI, DebugLoc DL,
302 unsigned DestReg, unsigned SrcReg,
303 bool KillSrc) const {
304
305 // If we are trying to copy to or from SCC, there is a bug somewhere else in
306 // the backend. While it may be theoretically possible to do this, it should
307 // never be necessary.
308 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
309
310 static const int16_t Sub0_15[] = {
311 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
312 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
313 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
314 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
315 };
316
317 static const int16_t Sub0_7[] = {
318 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
319 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
320 };
321
322 static const int16_t Sub0_3[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
324 };
325
326 static const int16_t Sub0_2[] = {
327 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
328 };
329
330 static const int16_t Sub0_1[] = {
331 AMDGPU::sub0, AMDGPU::sub1, 0
332 };
333
334 unsigned Opcode;
335 const int16_t *SubIndices;
336
337 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
338 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
339 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
340 .addReg(SrcReg, getKillRegState(KillSrc));
341 return;
342
343 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
344 if (DestReg == AMDGPU::VCC) {
345 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
346 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
347 .addReg(SrcReg, getKillRegState(KillSrc));
348 } else {
349 // FIXME: Hack until VReg_1 removed.
350 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
352 .addImm(0)
353 .addReg(SrcReg, getKillRegState(KillSrc));
354 }
355
356 return;
357 }
358
359 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
360 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
361 .addReg(SrcReg, getKillRegState(KillSrc));
362 return;
363
364 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
365 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
366 Opcode = AMDGPU::S_MOV_B32;
367 SubIndices = Sub0_3;
368
369 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
370 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
371 Opcode = AMDGPU::S_MOV_B32;
372 SubIndices = Sub0_7;
373
374 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
375 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
376 Opcode = AMDGPU::S_MOV_B32;
377 SubIndices = Sub0_15;
378
379 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
380 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
381 AMDGPU::SReg_32RegClass.contains(SrcReg));
382 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
383 .addReg(SrcReg, getKillRegState(KillSrc));
384 return;
385
386 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
387 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
388 AMDGPU::SReg_64RegClass.contains(SrcReg));
389 Opcode = AMDGPU::V_MOV_B32_e32;
390 SubIndices = Sub0_1;
391
392 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
393 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
394 Opcode = AMDGPU::V_MOV_B32_e32;
395 SubIndices = Sub0_2;
396
397 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
398 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
399 AMDGPU::SReg_128RegClass.contains(SrcReg));
400 Opcode = AMDGPU::V_MOV_B32_e32;
401 SubIndices = Sub0_3;
402
403 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
404 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
405 AMDGPU::SReg_256RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
407 SubIndices = Sub0_7;
408
409 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_512RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
413 SubIndices = Sub0_15;
414
415 } else {
416 llvm_unreachable("Can't copy register!");
417 }
418
419 while (unsigned SubIdx = *SubIndices++) {
420 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
421 get(Opcode), RI.getSubReg(DestReg, SubIdx));
422
423 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
424
425 if (*SubIndices)
426 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
427 }
428 }
429
commuteOpcode(unsigned Opcode) const430 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
431 int NewOpc;
432
433 // Try to map original to commuted opcode
434 NewOpc = AMDGPU::getCommuteRev(Opcode);
435 // Check if the commuted (REV) opcode exists on the target.
436 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
437 return NewOpc;
438
439 // Try to map commuted to original opcode
440 NewOpc = AMDGPU::getCommuteOrig(Opcode);
441 // Check if the original (non-REV) opcode exists on the target.
442 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
443 return NewOpc;
444
445 return Opcode;
446 }
447
getMovOpcode(const TargetRegisterClass * DstRC) const448 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
449
450 if (DstRC->getSize() == 4) {
451 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
452 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
453 return AMDGPU::S_MOV_B64;
454 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
455 return AMDGPU::V_MOV_B64_PSEUDO;
456 }
457 return AMDGPU::COPY;
458 }
459
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const460 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MI,
462 unsigned SrcReg, bool isKill,
463 int FrameIndex,
464 const TargetRegisterClass *RC,
465 const TargetRegisterInfo *TRI) const {
466 MachineFunction *MF = MBB.getParent();
467 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
468 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
469 DebugLoc DL = MBB.findDebugLoc(MI);
470 int Opcode = -1;
471
472 if (RI.isSGPRClass(RC)) {
473 // We are only allowed to create one new instruction when spilling
474 // registers, so we need to use pseudo instruction for spilling
475 // SGPRs.
476 switch (RC->getSize() * 8) {
477 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
478 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
479 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
480 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
481 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
482 }
483 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
484 MFI->setHasSpilledVGPRs();
485
486 switch(RC->getSize() * 8) {
487 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
488 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
489 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
490 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
491 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
492 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
493 }
494 }
495
496 if (Opcode != -1) {
497 FrameInfo->setObjectAlignment(FrameIndex, 4);
498 BuildMI(MBB, MI, DL, get(Opcode))
499 .addReg(SrcReg)
500 .addFrameIndex(FrameIndex)
501 // Place-holder registers, these will be filled in by
502 // SIPrepareScratchRegs.
503 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
504 .addReg(AMDGPU::SGPR0, RegState::Undef);
505 } else {
506 LLVMContext &Ctx = MF->getFunction()->getContext();
507 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
508 " spill register");
509 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
510 .addReg(SrcReg);
511 }
512 }
513
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const514 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator MI,
516 unsigned DestReg, int FrameIndex,
517 const TargetRegisterClass *RC,
518 const TargetRegisterInfo *TRI) const {
519 MachineFunction *MF = MBB.getParent();
520 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
521 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
522 DebugLoc DL = MBB.findDebugLoc(MI);
523 int Opcode = -1;
524
525 if (RI.isSGPRClass(RC)){
526 switch(RC->getSize() * 8) {
527 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
528 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
529 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
530 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
531 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
532 }
533 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
534 switch(RC->getSize() * 8) {
535 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
536 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
537 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
538 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
539 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
540 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
541 }
542 }
543
544 if (Opcode != -1) {
545 FrameInfo->setObjectAlignment(FrameIndex, 4);
546 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
547 .addFrameIndex(FrameIndex)
548 // Place-holder registers, these will be filled in by
549 // SIPrepareScratchRegs.
550 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
551 .addReg(AMDGPU::SGPR0, RegState::Undef);
552
553 } else {
554 LLVMContext &Ctx = MF->getFunction()->getContext();
555 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
556 " restore register");
557 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
558 }
559 }
560
561 /// \param @Offset Offset in bytes of the FrameIndex being spilled
calculateLDSSpillAddress(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,RegScavenger * RS,unsigned TmpReg,unsigned FrameOffset,unsigned Size) const562 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
563 MachineBasicBlock::iterator MI,
564 RegScavenger *RS, unsigned TmpReg,
565 unsigned FrameOffset,
566 unsigned Size) const {
567 MachineFunction *MF = MBB.getParent();
568 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
569 const AMDGPUSubtarget &ST = MF->getTarget().getSubtarget<AMDGPUSubtarget>();
570 const SIRegisterInfo *TRI =
571 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
572 DebugLoc DL = MBB.findDebugLoc(MI);
573 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
574 unsigned WavefrontSize = ST.getWavefrontSize();
575
576 unsigned TIDReg = MFI->getTIDReg();
577 if (!MFI->hasCalculatedTID()) {
578 MachineBasicBlock &Entry = MBB.getParent()->front();
579 MachineBasicBlock::iterator Insert = Entry.front();
580 DebugLoc DL = Insert->getDebugLoc();
581
582 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
583 if (TIDReg == AMDGPU::NoRegister)
584 return TIDReg;
585
586
587 if (MFI->getShaderType() == ShaderType::COMPUTE &&
588 WorkGroupSize > WavefrontSize) {
589
590 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
591 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
592 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
593 unsigned InputPtrReg =
594 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
595 static const unsigned TIDIGRegs[3] = {
596 TIDIGXReg, TIDIGYReg, TIDIGZReg
597 };
598 for (unsigned Reg : TIDIGRegs) {
599 if (!Entry.isLiveIn(Reg))
600 Entry.addLiveIn(Reg);
601 }
602
603 RS->enterBasicBlock(&Entry);
604 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
605 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
606 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
607 .addReg(InputPtrReg)
608 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
609 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
610 .addReg(InputPtrReg)
611 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
612
613 // NGROUPS.X * NGROUPS.Y
614 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
615 .addReg(STmp1)
616 .addReg(STmp0);
617 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
618 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
619 .addReg(STmp1)
620 .addReg(TIDIGXReg);
621 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
622 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
623 .addReg(STmp0)
624 .addReg(TIDIGYReg)
625 .addReg(TIDReg);
626 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
627 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
628 .addReg(TIDReg)
629 .addReg(TIDIGZReg);
630 } else {
631 // Get the wave id
632 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
633 TIDReg)
634 .addImm(-1)
635 .addImm(0);
636
637 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
638 TIDReg)
639 .addImm(-1)
640 .addReg(TIDReg);
641 }
642
643 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
644 TIDReg)
645 .addImm(2)
646 .addReg(TIDReg);
647 MFI->setTIDReg(TIDReg);
648 }
649
650 // Add FrameIndex to LDS offset
651 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
652 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
653 .addImm(LDSOffset)
654 .addReg(TIDReg);
655
656 return TmpReg;
657 }
658
insertNOPs(MachineBasicBlock::iterator MI,int Count) const659 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
660 int Count) const {
661 while (Count > 0) {
662 int Arg;
663 if (Count >= 8)
664 Arg = 7;
665 else
666 Arg = Count - 1;
667 Count -= 8;
668 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
669 .addImm(Arg);
670 }
671 }
672
expandPostRAPseudo(MachineBasicBlock::iterator MI) const673 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
674 MachineBasicBlock &MBB = *MI->getParent();
675 DebugLoc DL = MBB.findDebugLoc(MI);
676 switch (MI->getOpcode()) {
677 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
678
679 case AMDGPU::SI_CONSTDATA_PTR: {
680 unsigned Reg = MI->getOperand(0).getReg();
681 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
682 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
683
684 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
685
686 // Add 32-bit offset from this instruction to the start of the constant data.
687 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
688 .addReg(RegLo)
689 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
690 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
691 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
692 .addReg(RegHi)
693 .addImm(0)
694 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
695 .addReg(AMDGPU::SCC, RegState::Implicit);
696 MI->eraseFromParent();
697 break;
698 }
699 case AMDGPU::SGPR_USE:
700 // This is just a placeholder for register allocation.
701 MI->eraseFromParent();
702 break;
703
704 case AMDGPU::V_MOV_B64_PSEUDO: {
705 unsigned Dst = MI->getOperand(0).getReg();
706 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
707 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
708
709 const MachineOperand &SrcOp = MI->getOperand(1);
710 // FIXME: Will this work for 64-bit floating point immediates?
711 assert(!SrcOp.isFPImm());
712 if (SrcOp.isImm()) {
713 APInt Imm(64, SrcOp.getImm());
714 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
715 .addImm(Imm.getLoBits(32).getZExtValue())
716 .addReg(Dst, RegState::Implicit);
717 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
718 .addImm(Imm.getHiBits(32).getZExtValue())
719 .addReg(Dst, RegState::Implicit);
720 } else {
721 assert(SrcOp.isReg());
722 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
723 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
724 .addReg(Dst, RegState::Implicit);
725 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
726 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
727 .addReg(Dst, RegState::Implicit);
728 }
729 MI->eraseFromParent();
730 break;
731 }
732 }
733 return true;
734 }
735
commuteInstruction(MachineInstr * MI,bool NewMI) const736 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
737 bool NewMI) const {
738
739 if (MI->getNumOperands() < 3)
740 return nullptr;
741
742 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
743 AMDGPU::OpName::src0);
744 assert(Src0Idx != -1 && "Should always have src0 operand");
745
746 MachineOperand &Src0 = MI->getOperand(Src0Idx);
747 if (!Src0.isReg())
748 return nullptr;
749
750 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
751 AMDGPU::OpName::src1);
752 if (Src1Idx == -1)
753 return nullptr;
754
755 MachineOperand &Src1 = MI->getOperand(Src1Idx);
756
757 // Make sure it's legal to commute operands for VOP2.
758 if (isVOP2(MI->getOpcode()) &&
759 (!isOperandLegal(MI, Src0Idx, &Src1) ||
760 !isOperandLegal(MI, Src1Idx, &Src0))) {
761 return nullptr;
762 }
763
764 if (!Src1.isReg()) {
765 // Allow commuting instructions with Imm operands.
766 if (NewMI || !Src1.isImm() ||
767 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
768 return nullptr;
769 }
770
771 // Be sure to copy the source modifiers to the right place.
772 if (MachineOperand *Src0Mods
773 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
774 MachineOperand *Src1Mods
775 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
776
777 int Src0ModsVal = Src0Mods->getImm();
778 if (!Src1Mods && Src0ModsVal != 0)
779 return nullptr;
780
781 // XXX - This assert might be a lie. It might be useful to have a neg
782 // modifier with 0.0.
783 int Src1ModsVal = Src1Mods->getImm();
784 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
785
786 Src1Mods->setImm(Src0ModsVal);
787 Src0Mods->setImm(Src1ModsVal);
788 }
789
790 unsigned Reg = Src0.getReg();
791 unsigned SubReg = Src0.getSubReg();
792 if (Src1.isImm())
793 Src0.ChangeToImmediate(Src1.getImm());
794 else
795 llvm_unreachable("Should only have immediates");
796
797 Src1.ChangeToRegister(Reg, false);
798 Src1.setSubReg(SubReg);
799 } else {
800 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
801 }
802
803 if (MI)
804 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
805
806 return MI;
807 }
808
809 // This needs to be implemented because the source modifiers may be inserted
810 // between the true commutable operands, and the base
811 // TargetInstrInfo::commuteInstruction uses it.
findCommutedOpIndices(MachineInstr * MI,unsigned & SrcOpIdx1,unsigned & SrcOpIdx2) const812 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
813 unsigned &SrcOpIdx1,
814 unsigned &SrcOpIdx2) const {
815 const MCInstrDesc &MCID = MI->getDesc();
816 if (!MCID.isCommutable())
817 return false;
818
819 unsigned Opc = MI->getOpcode();
820 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
821 if (Src0Idx == -1)
822 return false;
823
824 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
825 // immediate.
826 if (!MI->getOperand(Src0Idx).isReg())
827 return false;
828
829 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
830 if (Src1Idx == -1)
831 return false;
832
833 if (!MI->getOperand(Src1Idx).isReg())
834 return false;
835
836 // If any source modifiers are set, the generic instruction commuting won't
837 // understand how to copy the source modifiers.
838 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
839 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
840 return false;
841
842 SrcOpIdx1 = Src0Idx;
843 SrcOpIdx2 = Src1Idx;
844 return true;
845 }
846
buildMovInstr(MachineBasicBlock * MBB,MachineBasicBlock::iterator I,unsigned DstReg,unsigned SrcReg) const847 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
848 MachineBasicBlock::iterator I,
849 unsigned DstReg,
850 unsigned SrcReg) const {
851 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
852 DstReg) .addReg(SrcReg);
853 }
854
isMov(unsigned Opcode) const855 bool SIInstrInfo::isMov(unsigned Opcode) const {
856 switch(Opcode) {
857 default: return false;
858 case AMDGPU::S_MOV_B32:
859 case AMDGPU::S_MOV_B64:
860 case AMDGPU::V_MOV_B32_e32:
861 case AMDGPU::V_MOV_B32_e64:
862 return true;
863 }
864 }
865
866 bool
isSafeToMoveRegClassDefs(const TargetRegisterClass * RC) const867 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
868 return RC != &AMDGPU::EXECRegRegClass;
869 }
870
871 bool
isTriviallyReMaterializable(const MachineInstr * MI,AliasAnalysis * AA) const872 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
873 AliasAnalysis *AA) const {
874 switch(MI->getOpcode()) {
875 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
876 case AMDGPU::S_MOV_B32:
877 case AMDGPU::S_MOV_B64:
878 case AMDGPU::V_MOV_B32_e32:
879 return MI->getOperand(1).isImm();
880 }
881 }
882
offsetsDoNotOverlap(int WidthA,int OffsetA,int WidthB,int OffsetB)883 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
884 int WidthB, int OffsetB) {
885 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
886 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
887 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
888 return LowOffset + LowWidth <= HighOffset;
889 }
890
checkInstOffsetsDoNotOverlap(MachineInstr * MIa,MachineInstr * MIb) const891 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
892 MachineInstr *MIb) const {
893 unsigned BaseReg0, Offset0;
894 unsigned BaseReg1, Offset1;
895
896 if (getLdStBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
897 getLdStBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
898 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
899 "read2 / write2 not expected here yet");
900 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
901 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
902 if (BaseReg0 == BaseReg1 &&
903 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
904 return true;
905 }
906 }
907
908 return false;
909 }
910
areMemAccessesTriviallyDisjoint(MachineInstr * MIa,MachineInstr * MIb,AliasAnalysis * AA) const911 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
912 MachineInstr *MIb,
913 AliasAnalysis *AA) const {
914 unsigned Opc0 = MIa->getOpcode();
915 unsigned Opc1 = MIb->getOpcode();
916
917 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
918 "MIa must load from or modify a memory location");
919 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
920 "MIb must load from or modify a memory location");
921
922 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
923 return false;
924
925 // XXX - Can we relax this between address spaces?
926 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
927 return false;
928
929 // TODO: Should we check the address space from the MachineMemOperand? That
930 // would allow us to distinguish objects we know don't alias based on the
931 // underlying addres space, even if it was lowered to a different one,
932 // e.g. private accesses lowered to use MUBUF instructions on a scratch
933 // buffer.
934 if (isDS(Opc0)) {
935 if (isDS(Opc1))
936 return checkInstOffsetsDoNotOverlap(MIa, MIb);
937
938 return !isFLAT(Opc1);
939 }
940
941 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
942 if (isMUBUF(Opc1) || isMTBUF(Opc1))
943 return checkInstOffsetsDoNotOverlap(MIa, MIb);
944
945 return !isFLAT(Opc1) && !isSMRD(Opc1);
946 }
947
948 if (isSMRD(Opc0)) {
949 if (isSMRD(Opc1))
950 return checkInstOffsetsDoNotOverlap(MIa, MIb);
951
952 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
953 }
954
955 if (isFLAT(Opc0)) {
956 if (isFLAT(Opc1))
957 return checkInstOffsetsDoNotOverlap(MIa, MIb);
958
959 return false;
960 }
961
962 return false;
963 }
964
isInlineConstant(const APInt & Imm) const965 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
966 int64_t SVal = Imm.getSExtValue();
967 if (SVal >= -16 && SVal <= 64)
968 return true;
969
970 if (Imm.getBitWidth() == 64) {
971 uint64_t Val = Imm.getZExtValue();
972 return (DoubleToBits(0.0) == Val) ||
973 (DoubleToBits(1.0) == Val) ||
974 (DoubleToBits(-1.0) == Val) ||
975 (DoubleToBits(0.5) == Val) ||
976 (DoubleToBits(-0.5) == Val) ||
977 (DoubleToBits(2.0) == Val) ||
978 (DoubleToBits(-2.0) == Val) ||
979 (DoubleToBits(4.0) == Val) ||
980 (DoubleToBits(-4.0) == Val);
981 }
982
983 // The actual type of the operand does not seem to matter as long
984 // as the bits match one of the inline immediate values. For example:
985 //
986 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
987 // so it is a legal inline immediate.
988 //
989 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
990 // floating-point, so it is a legal inline immediate.
991 uint32_t Val = Imm.getZExtValue();
992
993 return (FloatToBits(0.0f) == Val) ||
994 (FloatToBits(1.0f) == Val) ||
995 (FloatToBits(-1.0f) == Val) ||
996 (FloatToBits(0.5f) == Val) ||
997 (FloatToBits(-0.5f) == Val) ||
998 (FloatToBits(2.0f) == Val) ||
999 (FloatToBits(-2.0f) == Val) ||
1000 (FloatToBits(4.0f) == Val) ||
1001 (FloatToBits(-4.0f) == Val);
1002 }
1003
isInlineConstant(const MachineOperand & MO) const1004 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
1005 if (MO.isImm())
1006 return isInlineConstant(APInt(32, MO.getImm(), true));
1007
1008 return false;
1009 }
1010
isLiteralConstant(const MachineOperand & MO) const1011 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
1012 return MO.isImm() && !isInlineConstant(MO);
1013 }
1014
compareMachineOp(const MachineOperand & Op0,const MachineOperand & Op1)1015 static bool compareMachineOp(const MachineOperand &Op0,
1016 const MachineOperand &Op1) {
1017 if (Op0.getType() != Op1.getType())
1018 return false;
1019
1020 switch (Op0.getType()) {
1021 case MachineOperand::MO_Register:
1022 return Op0.getReg() == Op1.getReg();
1023 case MachineOperand::MO_Immediate:
1024 return Op0.getImm() == Op1.getImm();
1025 default:
1026 llvm_unreachable("Didn't expect to be comparing these operand types");
1027 }
1028 }
1029
isImmOperandLegal(const MachineInstr * MI,unsigned OpNo,const MachineOperand & MO) const1030 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1031 const MachineOperand &MO) const {
1032 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1033
1034 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1035
1036 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1037 return true;
1038
1039 if (OpInfo.RegClass < 0)
1040 return false;
1041
1042 if (isLiteralConstant(MO))
1043 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1044
1045 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1046 }
1047
canFoldOffset(unsigned OffsetSize,unsigned AS) const1048 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) const {
1049 switch (AS) {
1050 case AMDGPUAS::GLOBAL_ADDRESS: {
1051 // MUBUF instructions a 12-bit offset in bytes.
1052 return isUInt<12>(OffsetSize);
1053 }
1054 case AMDGPUAS::CONSTANT_ADDRESS: {
1055 // SMRD instructions have an 8-bit offset in dwords on SI and
1056 // a 20-bit offset in bytes on VI.
1057 if (RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1058 return isUInt<20>(OffsetSize);
1059 else
1060 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1061 }
1062 case AMDGPUAS::LOCAL_ADDRESS:
1063 case AMDGPUAS::REGION_ADDRESS: {
1064 // The single offset versions have a 16-bit offset in bytes.
1065 return isUInt<16>(OffsetSize);
1066 }
1067 case AMDGPUAS::PRIVATE_ADDRESS:
1068 // Indirect register addressing does not use any offsets.
1069 default:
1070 return 0;
1071 }
1072 }
1073
hasVALU32BitEncoding(unsigned Opcode) const1074 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1075 int Op32 = AMDGPU::getVOPe32(Opcode);
1076 if (Op32 == -1)
1077 return false;
1078
1079 return pseudoToMCOpcode(Op32) != -1;
1080 }
1081
hasModifiers(unsigned Opcode) const1082 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1083 // The src0_modifier operand is present on all instructions
1084 // that have modifiers.
1085
1086 return AMDGPU::getNamedOperandIdx(Opcode,
1087 AMDGPU::OpName::src0_modifiers) != -1;
1088 }
1089
hasModifiersSet(const MachineInstr & MI,unsigned OpName) const1090 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1091 unsigned OpName) const {
1092 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1093 return Mods && Mods->getImm();
1094 }
1095
usesConstantBus(const MachineRegisterInfo & MRI,const MachineOperand & MO) const1096 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1097 const MachineOperand &MO) const {
1098 // Literal constants use the constant bus.
1099 if (isLiteralConstant(MO))
1100 return true;
1101
1102 if (!MO.isReg() || !MO.isUse())
1103 return false;
1104
1105 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1106 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1107
1108 // FLAT_SCR is just an SGPR pair.
1109 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1110 return true;
1111
1112 // EXEC register uses the constant bus.
1113 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1114 return true;
1115
1116 // SGPRs use the constant bus
1117 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1118 (!MO.isImplicit() &&
1119 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1120 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1121 return true;
1122 }
1123
1124 return false;
1125 }
1126
verifyInstruction(const MachineInstr * MI,StringRef & ErrInfo) const1127 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1128 StringRef &ErrInfo) const {
1129 uint16_t Opcode = MI->getOpcode();
1130 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1131 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1132 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1133 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1134
1135 // Make sure the number of operands is correct.
1136 const MCInstrDesc &Desc = get(Opcode);
1137 if (!Desc.isVariadic() &&
1138 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1139 ErrInfo = "Instruction has wrong number of operands.";
1140 return false;
1141 }
1142
1143 // Make sure the register classes are correct
1144 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1145 if (MI->getOperand(i).isFPImm()) {
1146 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1147 "all fp values to integers.";
1148 return false;
1149 }
1150
1151 int RegClass = Desc.OpInfo[i].RegClass;
1152
1153 switch (Desc.OpInfo[i].OperandType) {
1154 case MCOI::OPERAND_REGISTER:
1155 if (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm()) {
1156 ErrInfo = "Illegal immediate value for operand.";
1157 return false;
1158 }
1159 break;
1160 case AMDGPU::OPERAND_REG_IMM32:
1161 break;
1162 case AMDGPU::OPERAND_REG_INLINE_C:
1163 if (isLiteralConstant(MI->getOperand(i))) {
1164 ErrInfo = "Illegal immediate value for operand.";
1165 return false;
1166 }
1167 break;
1168 case MCOI::OPERAND_IMMEDIATE:
1169 // Check if this operand is an immediate.
1170 // FrameIndex operands will be replaced by immediates, so they are
1171 // allowed.
1172 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1173 ErrInfo = "Expected immediate, but got non-immediate";
1174 return false;
1175 }
1176 // Fall-through
1177 default:
1178 continue;
1179 }
1180
1181 if (!MI->getOperand(i).isReg())
1182 continue;
1183
1184 if (RegClass != -1) {
1185 unsigned Reg = MI->getOperand(i).getReg();
1186 if (TargetRegisterInfo::isVirtualRegister(Reg))
1187 continue;
1188
1189 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1190 if (!RC->contains(Reg)) {
1191 ErrInfo = "Operand has incorrect register class.";
1192 return false;
1193 }
1194 }
1195 }
1196
1197
1198 // Verify VOP*
1199 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1200 // Only look at the true operands. Only a real operand can use the constant
1201 // bus, and we don't want to check pseudo-operands like the source modifier
1202 // flags.
1203 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1204
1205 unsigned ConstantBusCount = 0;
1206 unsigned SGPRUsed = AMDGPU::NoRegister;
1207 for (int OpIdx : OpIndices) {
1208 if (OpIdx == -1)
1209 break;
1210
1211 const MachineOperand &MO = MI->getOperand(OpIdx);
1212 if (usesConstantBus(MRI, MO)) {
1213 if (MO.isReg()) {
1214 if (MO.getReg() != SGPRUsed)
1215 ++ConstantBusCount;
1216 SGPRUsed = MO.getReg();
1217 } else {
1218 ++ConstantBusCount;
1219 }
1220 }
1221 }
1222 if (ConstantBusCount > 1) {
1223 ErrInfo = "VOP* instruction uses the constant bus more than once";
1224 return false;
1225 }
1226 }
1227
1228 // Verify misc. restrictions on specific instructions.
1229 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1230 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1231 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1232 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1233 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1234 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1235 if (!compareMachineOp(Src0, Src1) &&
1236 !compareMachineOp(Src0, Src2)) {
1237 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1238 return false;
1239 }
1240 }
1241 }
1242
1243 return true;
1244 }
1245
getVALUOp(const MachineInstr & MI)1246 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1247 switch (MI.getOpcode()) {
1248 default: return AMDGPU::INSTRUCTION_LIST_END;
1249 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1250 case AMDGPU::COPY: return AMDGPU::COPY;
1251 case AMDGPU::PHI: return AMDGPU::PHI;
1252 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1253 case AMDGPU::S_MOV_B32:
1254 return MI.getOperand(1).isReg() ?
1255 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1256 case AMDGPU::S_ADD_I32:
1257 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1258 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1259 case AMDGPU::S_SUB_I32:
1260 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1261 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1262 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1263 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1264 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1265 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1266 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1267 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1268 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1269 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1270 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1271 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1272 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1273 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1274 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1275 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1276 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1277 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1278 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1279 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1280 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1281 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1282 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1283 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1284 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1285 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1286 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1287 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1288 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1289 case AMDGPU::S_LOAD_DWORD_IMM:
1290 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1291 case AMDGPU::S_LOAD_DWORDX2_IMM:
1292 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1293 case AMDGPU::S_LOAD_DWORDX4_IMM:
1294 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1295 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1296 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1297 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1298 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1299 }
1300 }
1301
isSALUOpSupportedOnVALU(const MachineInstr & MI) const1302 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1303 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1304 }
1305
getOpRegClass(const MachineInstr & MI,unsigned OpNo) const1306 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1307 unsigned OpNo) const {
1308 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1309 const MCInstrDesc &Desc = get(MI.getOpcode());
1310 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1311 Desc.OpInfo[OpNo].RegClass == -1) {
1312 unsigned Reg = MI.getOperand(OpNo).getReg();
1313
1314 if (TargetRegisterInfo::isVirtualRegister(Reg))
1315 return MRI.getRegClass(Reg);
1316 return RI.getRegClass(Reg);
1317 }
1318
1319 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1320 return RI.getRegClass(RCID);
1321 }
1322
canReadVGPR(const MachineInstr & MI,unsigned OpNo) const1323 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1324 switch (MI.getOpcode()) {
1325 case AMDGPU::COPY:
1326 case AMDGPU::REG_SEQUENCE:
1327 case AMDGPU::PHI:
1328 case AMDGPU::INSERT_SUBREG:
1329 return RI.hasVGPRs(getOpRegClass(MI, 0));
1330 default:
1331 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1332 }
1333 }
1334
legalizeOpWithMove(MachineInstr * MI,unsigned OpIdx) const1335 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1336 MachineBasicBlock::iterator I = MI;
1337 MachineBasicBlock *MBB = MI->getParent();
1338 MachineOperand &MO = MI->getOperand(OpIdx);
1339 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1340 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1341 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1342 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1343 if (MO.isReg())
1344 Opcode = AMDGPU::COPY;
1345 else if (RI.isSGPRClass(RC))
1346 Opcode = AMDGPU::S_MOV_B32;
1347
1348
1349 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1350 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1351 VRC = &AMDGPU::VReg_64RegClass;
1352 else
1353 VRC = &AMDGPU::VGPR_32RegClass;
1354
1355 unsigned Reg = MRI.createVirtualRegister(VRC);
1356 DebugLoc DL = MBB->findDebugLoc(I);
1357 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1358 .addOperand(MO);
1359 MO.ChangeToRegister(Reg, false);
1360 }
1361
buildExtractSubReg(MachineBasicBlock::iterator MI,MachineRegisterInfo & MRI,MachineOperand & SuperReg,const TargetRegisterClass * SuperRC,unsigned SubIdx,const TargetRegisterClass * SubRC) const1362 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1363 MachineRegisterInfo &MRI,
1364 MachineOperand &SuperReg,
1365 const TargetRegisterClass *SuperRC,
1366 unsigned SubIdx,
1367 const TargetRegisterClass *SubRC)
1368 const {
1369 assert(SuperReg.isReg());
1370
1371 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1372 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1373
1374 // Just in case the super register is itself a sub-register, copy it to a new
1375 // value so we don't need to worry about merging its subreg index with the
1376 // SubIdx passed to this function. The register coalescer should be able to
1377 // eliminate this extra copy.
1378 MachineBasicBlock *MBB = MI->getParent();
1379 DebugLoc DL = MI->getDebugLoc();
1380
1381 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1382 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1383
1384 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1385 .addReg(NewSuperReg, 0, SubIdx);
1386
1387 return SubReg;
1388 }
1389
buildExtractSubRegOrImm(MachineBasicBlock::iterator MII,MachineRegisterInfo & MRI,MachineOperand & Op,const TargetRegisterClass * SuperRC,unsigned SubIdx,const TargetRegisterClass * SubRC) const1390 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1391 MachineBasicBlock::iterator MII,
1392 MachineRegisterInfo &MRI,
1393 MachineOperand &Op,
1394 const TargetRegisterClass *SuperRC,
1395 unsigned SubIdx,
1396 const TargetRegisterClass *SubRC) const {
1397 if (Op.isImm()) {
1398 // XXX - Is there a better way to do this?
1399 if (SubIdx == AMDGPU::sub0)
1400 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1401 if (SubIdx == AMDGPU::sub1)
1402 return MachineOperand::CreateImm(Op.getImm() >> 32);
1403
1404 llvm_unreachable("Unhandled register index for immediate");
1405 }
1406
1407 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1408 SubIdx, SubRC);
1409 return MachineOperand::CreateReg(SubReg, false);
1410 }
1411
split64BitImm(SmallVectorImpl<MachineInstr * > & Worklist,MachineBasicBlock::iterator MI,MachineRegisterInfo & MRI,const TargetRegisterClass * RC,const MachineOperand & Op) const1412 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1413 MachineBasicBlock::iterator MI,
1414 MachineRegisterInfo &MRI,
1415 const TargetRegisterClass *RC,
1416 const MachineOperand &Op) const {
1417 MachineBasicBlock *MBB = MI->getParent();
1418 DebugLoc DL = MI->getDebugLoc();
1419 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1420 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1421 unsigned Dst = MRI.createVirtualRegister(RC);
1422
1423 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1424 LoDst)
1425 .addImm(Op.getImm() & 0xFFFFFFFF);
1426 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1427 HiDst)
1428 .addImm(Op.getImm() >> 32);
1429
1430 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1431 .addReg(LoDst)
1432 .addImm(AMDGPU::sub0)
1433 .addReg(HiDst)
1434 .addImm(AMDGPU::sub1);
1435
1436 Worklist.push_back(Lo);
1437 Worklist.push_back(Hi);
1438
1439 return Dst;
1440 }
1441
1442 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
swapOperands(MachineBasicBlock::iterator Inst) const1443 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1444 assert(Inst->getNumExplicitOperands() == 3);
1445 MachineOperand Op1 = Inst->getOperand(1);
1446 Inst->RemoveOperand(1);
1447 Inst->addOperand(Op1);
1448 }
1449
isOperandLegal(const MachineInstr * MI,unsigned OpIdx,const MachineOperand * MO) const1450 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1451 const MachineOperand *MO) const {
1452 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1453 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1454 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1455 const TargetRegisterClass *DefinedRC =
1456 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1457 if (!MO)
1458 MO = &MI->getOperand(OpIdx);
1459
1460 if (isVALU(InstDesc.Opcode) && usesConstantBus(MRI, *MO)) {
1461 unsigned SGPRUsed =
1462 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1463 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1464 if (i == OpIdx)
1465 continue;
1466 if (usesConstantBus(MRI, MI->getOperand(i)) &&
1467 MI->getOperand(i).isReg() && MI->getOperand(i).getReg() != SGPRUsed) {
1468 return false;
1469 }
1470 }
1471 }
1472
1473 if (MO->isReg()) {
1474 assert(DefinedRC);
1475 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1476
1477 // In order to be legal, the common sub-class must be equal to the
1478 // class of the current operand. For example:
1479 //
1480 // v_mov_b32 s0 ; Operand defined as vsrc_32
1481 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1482 //
1483 // s_sendmsg 0, s0 ; Operand defined as m0reg
1484 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1485
1486 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1487 }
1488
1489
1490 // Handle non-register types that are treated like immediates.
1491 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1492
1493 if (!DefinedRC) {
1494 // This operand expects an immediate.
1495 return true;
1496 }
1497
1498 return isImmOperandLegal(MI, OpIdx, *MO);
1499 }
1500
legalizeOperands(MachineInstr * MI) const1501 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1502 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1503
1504 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1505 AMDGPU::OpName::src0);
1506 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1507 AMDGPU::OpName::src1);
1508 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1509 AMDGPU::OpName::src2);
1510
1511 // Legalize VOP2
1512 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1513 // Legalize src0
1514 if (!isOperandLegal(MI, Src0Idx))
1515 legalizeOpWithMove(MI, Src0Idx);
1516
1517 // Legalize src1
1518 if (isOperandLegal(MI, Src1Idx))
1519 return;
1520
1521 // Usually src0 of VOP2 instructions allow more types of inputs
1522 // than src1, so try to commute the instruction to decrease our
1523 // chances of having to insert a MOV instruction to legalize src1.
1524 if (MI->isCommutable()) {
1525 if (commuteInstruction(MI))
1526 // If we are successful in commuting, then we know MI is legal, so
1527 // we are done.
1528 return;
1529 }
1530
1531 legalizeOpWithMove(MI, Src1Idx);
1532 return;
1533 }
1534
1535 // XXX - Do any VOP3 instructions read VCC?
1536 // Legalize VOP3
1537 if (isVOP3(MI->getOpcode())) {
1538 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1539
1540 // Find the one SGPR operand we are allowed to use.
1541 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1542
1543 for (unsigned i = 0; i < 3; ++i) {
1544 int Idx = VOP3Idx[i];
1545 if (Idx == -1)
1546 break;
1547 MachineOperand &MO = MI->getOperand(Idx);
1548
1549 if (MO.isReg()) {
1550 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1551 continue; // VGPRs are legal
1552
1553 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1554
1555 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1556 SGPRReg = MO.getReg();
1557 // We can use one SGPR in each VOP3 instruction.
1558 continue;
1559 }
1560 } else if (!isLiteralConstant(MO)) {
1561 // If it is not a register and not a literal constant, then it must be
1562 // an inline constant which is always legal.
1563 continue;
1564 }
1565 // If we make it this far, then the operand is not legal and we must
1566 // legalize it.
1567 legalizeOpWithMove(MI, Idx);
1568 }
1569 }
1570
1571 // Legalize REG_SEQUENCE and PHI
1572 // The register class of the operands much be the same type as the register
1573 // class of the output.
1574 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1575 MI->getOpcode() == AMDGPU::PHI) {
1576 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1577 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1578 if (!MI->getOperand(i).isReg() ||
1579 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1580 continue;
1581 const TargetRegisterClass *OpRC =
1582 MRI.getRegClass(MI->getOperand(i).getReg());
1583 if (RI.hasVGPRs(OpRC)) {
1584 VRC = OpRC;
1585 } else {
1586 SRC = OpRC;
1587 }
1588 }
1589
1590 // If any of the operands are VGPR registers, then they all most be
1591 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1592 // them.
1593 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1594 if (!VRC) {
1595 assert(SRC);
1596 VRC = RI.getEquivalentVGPRClass(SRC);
1597 }
1598 RC = VRC;
1599 } else {
1600 RC = SRC;
1601 }
1602
1603 // Update all the operands so they have the same type.
1604 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1605 if (!MI->getOperand(i).isReg() ||
1606 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1607 continue;
1608 unsigned DstReg = MRI.createVirtualRegister(RC);
1609 MachineBasicBlock *InsertBB;
1610 MachineBasicBlock::iterator Insert;
1611 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1612 InsertBB = MI->getParent();
1613 Insert = MI;
1614 } else {
1615 // MI is a PHI instruction.
1616 InsertBB = MI->getOperand(i + 1).getMBB();
1617 Insert = InsertBB->getFirstTerminator();
1618 }
1619 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1620 get(AMDGPU::COPY), DstReg)
1621 .addOperand(MI->getOperand(i));
1622 MI->getOperand(i).setReg(DstReg);
1623 }
1624 }
1625
1626 // Legalize INSERT_SUBREG
1627 // src0 must have the same register class as dst
1628 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1629 unsigned Dst = MI->getOperand(0).getReg();
1630 unsigned Src0 = MI->getOperand(1).getReg();
1631 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1632 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1633 if (DstRC != Src0RC) {
1634 MachineBasicBlock &MBB = *MI->getParent();
1635 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1636 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1637 .addReg(Src0);
1638 MI->getOperand(1).setReg(NewSrc0);
1639 }
1640 return;
1641 }
1642
1643 // Legalize MUBUF* instructions
1644 // FIXME: If we start using the non-addr64 instructions for compute, we
1645 // may need to legalize them here.
1646 int SRsrcIdx =
1647 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1648 if (SRsrcIdx != -1) {
1649 // We have an MUBUF instruction
1650 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1651 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1652 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1653 RI.getRegClass(SRsrcRC))) {
1654 // The operands are legal.
1655 // FIXME: We may need to legalize operands besided srsrc.
1656 return;
1657 }
1658
1659 MachineBasicBlock &MBB = *MI->getParent();
1660 // Extract the the ptr from the resource descriptor.
1661
1662 // SRsrcPtrLo = srsrc:sub0
1663 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1664 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VGPR_32RegClass);
1665
1666 // SRsrcPtrHi = srsrc:sub1
1667 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1668 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VGPR_32RegClass);
1669
1670 // Create an empty resource descriptor
1671 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1672 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1673 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1674 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1675 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1676
1677 // Zero64 = 0
1678 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1679 Zero64)
1680 .addImm(0);
1681
1682 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1683 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1684 SRsrcFormatLo)
1685 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1686
1687 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1688 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1689 SRsrcFormatHi)
1690 .addImm(RsrcDataFormat >> 32);
1691
1692 // NewSRsrc = {Zero64, SRsrcFormat}
1693 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1694 NewSRsrc)
1695 .addReg(Zero64)
1696 .addImm(AMDGPU::sub0_sub1)
1697 .addReg(SRsrcFormatLo)
1698 .addImm(AMDGPU::sub2)
1699 .addReg(SRsrcFormatHi)
1700 .addImm(AMDGPU::sub3);
1701
1702 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1703 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1704 unsigned NewVAddrLo;
1705 unsigned NewVAddrHi;
1706 if (VAddr) {
1707 // This is already an ADDR64 instruction so we need to add the pointer
1708 // extracted from the resource descriptor to the current value of VAddr.
1709 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1710 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1711
1712 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1713 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1714 NewVAddrLo)
1715 .addReg(SRsrcPtrLo)
1716 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1717 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1718
1719 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1720 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1721 NewVAddrHi)
1722 .addReg(SRsrcPtrHi)
1723 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1724 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1725 .addReg(AMDGPU::VCC, RegState::Implicit);
1726
1727 } else {
1728 // This instructions is the _OFFSET variant, so we need to convert it to
1729 // ADDR64.
1730 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1731 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1732 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1733 assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
1734 "with non-zero soffset is not implemented");
1735 (void)SOffset;
1736
1737 // Create the new instruction.
1738 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1739 MachineInstr *Addr64 =
1740 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1741 .addOperand(*VData)
1742 .addOperand(*SRsrc)
1743 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1744 // This will be replaced later
1745 // with the new value of vaddr.
1746 .addOperand(*Offset);
1747
1748 MI->removeFromParent();
1749 MI = Addr64;
1750
1751 NewVAddrLo = SRsrcPtrLo;
1752 NewVAddrHi = SRsrcPtrHi;
1753 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1754 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1755 }
1756
1757 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1758 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1759 NewVAddr)
1760 .addReg(NewVAddrLo)
1761 .addImm(AMDGPU::sub0)
1762 .addReg(NewVAddrHi)
1763 .addImm(AMDGPU::sub1);
1764
1765
1766 // Update the instruction to use NewVaddr
1767 VAddr->setReg(NewVAddr);
1768 // Update the instruction to use NewSRsrc
1769 SRsrc->setReg(NewSRsrc);
1770 }
1771 }
1772
splitSMRD(MachineInstr * MI,const TargetRegisterClass * HalfRC,unsigned HalfImmOp,unsigned HalfSGPROp,MachineInstr * & Lo,MachineInstr * & Hi) const1773 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1774 const TargetRegisterClass *HalfRC,
1775 unsigned HalfImmOp, unsigned HalfSGPROp,
1776 MachineInstr *&Lo, MachineInstr *&Hi) const {
1777
1778 DebugLoc DL = MI->getDebugLoc();
1779 MachineBasicBlock *MBB = MI->getParent();
1780 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1781 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1782 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1783 unsigned HalfSize = HalfRC->getSize();
1784 const MachineOperand *OffOp =
1785 getNamedOperand(*MI, AMDGPU::OpName::offset);
1786 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1787
1788 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1789 // on VI.
1790 if (OffOp) {
1791 bool isVI = RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
1792 unsigned OffScale = isVI ? 1 : 4;
1793 // Handle the _IMM variant
1794 unsigned LoOffset = OffOp->getImm() * OffScale;
1795 unsigned HiOffset = LoOffset + HalfSize;
1796 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1797 .addOperand(*SBase)
1798 .addImm(LoOffset / OffScale);
1799
1800 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1801 unsigned OffsetSGPR =
1802 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1803 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1804 .addImm(HiOffset); // The offset in register is in bytes.
1805 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1806 .addOperand(*SBase)
1807 .addReg(OffsetSGPR);
1808 } else {
1809 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1810 .addOperand(*SBase)
1811 .addImm(HiOffset / OffScale);
1812 }
1813 } else {
1814 // Handle the _SGPR variant
1815 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1816 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1817 .addOperand(*SBase)
1818 .addOperand(*SOff);
1819 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1820 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1821 .addOperand(*SOff)
1822 .addImm(HalfSize);
1823 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1824 .addOperand(*SBase)
1825 .addReg(OffsetSGPR);
1826 }
1827
1828 unsigned SubLo, SubHi;
1829 switch (HalfSize) {
1830 case 4:
1831 SubLo = AMDGPU::sub0;
1832 SubHi = AMDGPU::sub1;
1833 break;
1834 case 8:
1835 SubLo = AMDGPU::sub0_sub1;
1836 SubHi = AMDGPU::sub2_sub3;
1837 break;
1838 case 16:
1839 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1840 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1841 break;
1842 case 32:
1843 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1844 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1845 break;
1846 default:
1847 llvm_unreachable("Unhandled HalfSize");
1848 }
1849
1850 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1851 .addOperand(MI->getOperand(0))
1852 .addReg(RegLo)
1853 .addImm(SubLo)
1854 .addReg(RegHi)
1855 .addImm(SubHi);
1856 }
1857
moveSMRDToVALU(MachineInstr * MI,MachineRegisterInfo & MRI) const1858 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1859 MachineBasicBlock *MBB = MI->getParent();
1860 switch (MI->getOpcode()) {
1861 case AMDGPU::S_LOAD_DWORD_IMM:
1862 case AMDGPU::S_LOAD_DWORD_SGPR:
1863 case AMDGPU::S_LOAD_DWORDX2_IMM:
1864 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1865 case AMDGPU::S_LOAD_DWORDX4_IMM:
1866 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1867 unsigned NewOpcode = getVALUOp(*MI);
1868 unsigned RegOffset;
1869 unsigned ImmOffset;
1870
1871 if (MI->getOperand(2).isReg()) {
1872 RegOffset = MI->getOperand(2).getReg();
1873 ImmOffset = 0;
1874 } else {
1875 assert(MI->getOperand(2).isImm());
1876 // SMRD instructions take a dword offsets on SI and byte offset on VI
1877 // and MUBUF instructions always take a byte offset.
1878 ImmOffset = MI->getOperand(2).getImm();
1879 if (RI.ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1880 ImmOffset <<= 2;
1881 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1882
1883 if (isUInt<12>(ImmOffset)) {
1884 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1885 RegOffset)
1886 .addImm(0);
1887 } else {
1888 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1889 RegOffset)
1890 .addImm(ImmOffset);
1891 ImmOffset = 0;
1892 }
1893 }
1894
1895 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1896 unsigned DWord0 = RegOffset;
1897 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1898 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1899 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1900 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1901
1902 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1903 .addImm(0);
1904 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1905 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1906 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1907 .addImm(RsrcDataFormat >> 32);
1908 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1909 .addReg(DWord0)
1910 .addImm(AMDGPU::sub0)
1911 .addReg(DWord1)
1912 .addImm(AMDGPU::sub1)
1913 .addReg(DWord2)
1914 .addImm(AMDGPU::sub2)
1915 .addReg(DWord3)
1916 .addImm(AMDGPU::sub3);
1917 MI->setDesc(get(NewOpcode));
1918 if (MI->getOperand(2).isReg()) {
1919 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1920 } else {
1921 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1922 }
1923 MI->getOperand(1).setReg(SRsrc);
1924 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1925
1926 const TargetRegisterClass *NewDstRC =
1927 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1928
1929 unsigned DstReg = MI->getOperand(0).getReg();
1930 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1931 MRI.replaceRegWith(DstReg, NewDstReg);
1932 break;
1933 }
1934 case AMDGPU::S_LOAD_DWORDX8_IMM:
1935 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1936 MachineInstr *Lo, *Hi;
1937 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1938 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1939 MI->eraseFromParent();
1940 moveSMRDToVALU(Lo, MRI);
1941 moveSMRDToVALU(Hi, MRI);
1942 break;
1943 }
1944
1945 case AMDGPU::S_LOAD_DWORDX16_IMM:
1946 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1947 MachineInstr *Lo, *Hi;
1948 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1949 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1950 MI->eraseFromParent();
1951 moveSMRDToVALU(Lo, MRI);
1952 moveSMRDToVALU(Hi, MRI);
1953 break;
1954 }
1955 }
1956 }
1957
moveToVALU(MachineInstr & TopInst) const1958 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1959 SmallVector<MachineInstr *, 128> Worklist;
1960 Worklist.push_back(&TopInst);
1961
1962 while (!Worklist.empty()) {
1963 MachineInstr *Inst = Worklist.pop_back_val();
1964 MachineBasicBlock *MBB = Inst->getParent();
1965 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1966
1967 unsigned Opcode = Inst->getOpcode();
1968 unsigned NewOpcode = getVALUOp(*Inst);
1969
1970 // Handle some special cases
1971 switch (Opcode) {
1972 default:
1973 if (isSMRD(Inst->getOpcode())) {
1974 moveSMRDToVALU(Inst, MRI);
1975 }
1976 break;
1977 case AMDGPU::S_MOV_B64: {
1978 DebugLoc DL = Inst->getDebugLoc();
1979
1980 // If the source operand is a register we can replace this with a
1981 // copy.
1982 if (Inst->getOperand(1).isReg()) {
1983 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1984 .addOperand(Inst->getOperand(0))
1985 .addOperand(Inst->getOperand(1));
1986 Worklist.push_back(Copy);
1987 } else {
1988 // Otherwise, we need to split this into two movs, because there is
1989 // no 64-bit VALU move instruction.
1990 unsigned Reg = Inst->getOperand(0).getReg();
1991 unsigned Dst = split64BitImm(Worklist,
1992 Inst,
1993 MRI,
1994 MRI.getRegClass(Reg),
1995 Inst->getOperand(1));
1996 MRI.replaceRegWith(Reg, Dst);
1997 }
1998 Inst->eraseFromParent();
1999 continue;
2000 }
2001 case AMDGPU::S_AND_B64:
2002 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
2003 Inst->eraseFromParent();
2004 continue;
2005
2006 case AMDGPU::S_OR_B64:
2007 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
2008 Inst->eraseFromParent();
2009 continue;
2010
2011 case AMDGPU::S_XOR_B64:
2012 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2013 Inst->eraseFromParent();
2014 continue;
2015
2016 case AMDGPU::S_NOT_B64:
2017 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2018 Inst->eraseFromParent();
2019 continue;
2020
2021 case AMDGPU::S_BCNT1_I32_B64:
2022 splitScalar64BitBCNT(Worklist, Inst);
2023 Inst->eraseFromParent();
2024 continue;
2025
2026 case AMDGPU::S_BFE_I64: {
2027 splitScalar64BitBFE(Worklist, Inst);
2028 Inst->eraseFromParent();
2029 continue;
2030 }
2031
2032 case AMDGPU::S_LSHL_B32:
2033 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2034 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2035 swapOperands(Inst);
2036 }
2037 break;
2038 case AMDGPU::S_ASHR_I32:
2039 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2040 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2041 swapOperands(Inst);
2042 }
2043 break;
2044 case AMDGPU::S_LSHR_B32:
2045 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2046 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2047 swapOperands(Inst);
2048 }
2049 break;
2050 case AMDGPU::S_LSHL_B64:
2051 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2052 NewOpcode = AMDGPU::V_LSHLREV_B64;
2053 swapOperands(Inst);
2054 }
2055 break;
2056 case AMDGPU::S_ASHR_I64:
2057 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2058 NewOpcode = AMDGPU::V_ASHRREV_I64;
2059 swapOperands(Inst);
2060 }
2061 break;
2062 case AMDGPU::S_LSHR_B64:
2063 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2064 NewOpcode = AMDGPU::V_LSHRREV_B64;
2065 swapOperands(Inst);
2066 }
2067 break;
2068
2069 case AMDGPU::S_BFE_U64:
2070 case AMDGPU::S_BFM_B64:
2071 llvm_unreachable("Moving this op to VALU not implemented");
2072 }
2073
2074 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2075 // We cannot move this instruction to the VALU, so we should try to
2076 // legalize its operands instead.
2077 legalizeOperands(Inst);
2078 continue;
2079 }
2080
2081 // Use the new VALU Opcode.
2082 const MCInstrDesc &NewDesc = get(NewOpcode);
2083 Inst->setDesc(NewDesc);
2084
2085 // Remove any references to SCC. Vector instructions can't read from it, and
2086 // We're just about to add the implicit use / defs of VCC, and we don't want
2087 // both.
2088 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2089 MachineOperand &Op = Inst->getOperand(i);
2090 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2091 Inst->RemoveOperand(i);
2092 }
2093
2094 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2095 // We are converting these to a BFE, so we need to add the missing
2096 // operands for the size and offset.
2097 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2098 Inst->addOperand(MachineOperand::CreateImm(0));
2099 Inst->addOperand(MachineOperand::CreateImm(Size));
2100
2101 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2102 // The VALU version adds the second operand to the result, so insert an
2103 // extra 0 operand.
2104 Inst->addOperand(MachineOperand::CreateImm(0));
2105 }
2106
2107 addDescImplicitUseDef(NewDesc, Inst);
2108
2109 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2110 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2111 // If we need to move this to VGPRs, we need to unpack the second operand
2112 // back into the 2 separate ones for bit offset and width.
2113 assert(OffsetWidthOp.isImm() &&
2114 "Scalar BFE is only implemented for constant width and offset");
2115 uint32_t Imm = OffsetWidthOp.getImm();
2116
2117 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2118 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2119 Inst->RemoveOperand(2); // Remove old immediate.
2120 Inst->addOperand(MachineOperand::CreateImm(Offset));
2121 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2122 }
2123
2124 // Update the destination register class.
2125
2126 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2127
2128 switch (Opcode) {
2129 // For target instructions, getOpRegClass just returns the virtual
2130 // register class associated with the operand, so we need to find an
2131 // equivalent VGPR register class in order to move the instruction to the
2132 // VALU.
2133 case AMDGPU::COPY:
2134 case AMDGPU::PHI:
2135 case AMDGPU::REG_SEQUENCE:
2136 case AMDGPU::INSERT_SUBREG:
2137 if (RI.hasVGPRs(NewDstRC))
2138 continue;
2139 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2140 if (!NewDstRC)
2141 continue;
2142 break;
2143 default:
2144 break;
2145 }
2146
2147 unsigned DstReg = Inst->getOperand(0).getReg();
2148 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2149 MRI.replaceRegWith(DstReg, NewDstReg);
2150
2151 // Legalize the operands
2152 legalizeOperands(Inst);
2153
2154 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2155 E = MRI.use_end(); I != E; ++I) {
2156 MachineInstr &UseMI = *I->getParent();
2157 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2158 Worklist.push_back(&UseMI);
2159 }
2160 }
2161 }
2162 }
2163
2164 //===----------------------------------------------------------------------===//
2165 // Indirect addressing callbacks
2166 //===----------------------------------------------------------------------===//
2167
calculateIndirectAddress(unsigned RegIndex,unsigned Channel) const2168 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2169 unsigned Channel) const {
2170 assert(Channel == 0);
2171 return RegIndex;
2172 }
2173
getIndirectAddrRegClass() const2174 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2175 return &AMDGPU::VGPR_32RegClass;
2176 }
2177
splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr * > & Worklist,MachineInstr * Inst,unsigned Opcode) const2178 void SIInstrInfo::splitScalar64BitUnaryOp(
2179 SmallVectorImpl<MachineInstr *> &Worklist,
2180 MachineInstr *Inst,
2181 unsigned Opcode) const {
2182 MachineBasicBlock &MBB = *Inst->getParent();
2183 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2184
2185 MachineOperand &Dest = Inst->getOperand(0);
2186 MachineOperand &Src0 = Inst->getOperand(1);
2187 DebugLoc DL = Inst->getDebugLoc();
2188
2189 MachineBasicBlock::iterator MII = Inst;
2190
2191 const MCInstrDesc &InstDesc = get(Opcode);
2192 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2193 MRI.getRegClass(Src0.getReg()) :
2194 &AMDGPU::SGPR_32RegClass;
2195
2196 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2197
2198 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2199 AMDGPU::sub0, Src0SubRC);
2200
2201 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2202 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2203
2204 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2205 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2206 .addOperand(SrcReg0Sub0);
2207
2208 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2209 AMDGPU::sub1, Src0SubRC);
2210
2211 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2212 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2213 .addOperand(SrcReg0Sub1);
2214
2215 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2216 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2217 .addReg(DestSub0)
2218 .addImm(AMDGPU::sub0)
2219 .addReg(DestSub1)
2220 .addImm(AMDGPU::sub1);
2221
2222 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2223
2224 // Try to legalize the operands in case we need to swap the order to keep it
2225 // valid.
2226 Worklist.push_back(LoHalf);
2227 Worklist.push_back(HiHalf);
2228 }
2229
splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr * > & Worklist,MachineInstr * Inst,unsigned Opcode) const2230 void SIInstrInfo::splitScalar64BitBinaryOp(
2231 SmallVectorImpl<MachineInstr *> &Worklist,
2232 MachineInstr *Inst,
2233 unsigned Opcode) const {
2234 MachineBasicBlock &MBB = *Inst->getParent();
2235 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2236
2237 MachineOperand &Dest = Inst->getOperand(0);
2238 MachineOperand &Src0 = Inst->getOperand(1);
2239 MachineOperand &Src1 = Inst->getOperand(2);
2240 DebugLoc DL = Inst->getDebugLoc();
2241
2242 MachineBasicBlock::iterator MII = Inst;
2243
2244 const MCInstrDesc &InstDesc = get(Opcode);
2245 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2246 MRI.getRegClass(Src0.getReg()) :
2247 &AMDGPU::SGPR_32RegClass;
2248
2249 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2250 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2251 MRI.getRegClass(Src1.getReg()) :
2252 &AMDGPU::SGPR_32RegClass;
2253
2254 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2255
2256 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2257 AMDGPU::sub0, Src0SubRC);
2258 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2259 AMDGPU::sub0, Src1SubRC);
2260
2261 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2262 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2263
2264 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2265 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2266 .addOperand(SrcReg0Sub0)
2267 .addOperand(SrcReg1Sub0);
2268
2269 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2270 AMDGPU::sub1, Src0SubRC);
2271 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2272 AMDGPU::sub1, Src1SubRC);
2273
2274 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2275 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2276 .addOperand(SrcReg0Sub1)
2277 .addOperand(SrcReg1Sub1);
2278
2279 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2280 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2281 .addReg(DestSub0)
2282 .addImm(AMDGPU::sub0)
2283 .addReg(DestSub1)
2284 .addImm(AMDGPU::sub1);
2285
2286 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2287
2288 // Try to legalize the operands in case we need to swap the order to keep it
2289 // valid.
2290 Worklist.push_back(LoHalf);
2291 Worklist.push_back(HiHalf);
2292 }
2293
splitScalar64BitBCNT(SmallVectorImpl<MachineInstr * > & Worklist,MachineInstr * Inst) const2294 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2295 MachineInstr *Inst) const {
2296 MachineBasicBlock &MBB = *Inst->getParent();
2297 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2298
2299 MachineBasicBlock::iterator MII = Inst;
2300 DebugLoc DL = Inst->getDebugLoc();
2301
2302 MachineOperand &Dest = Inst->getOperand(0);
2303 MachineOperand &Src = Inst->getOperand(1);
2304
2305 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2306 const TargetRegisterClass *SrcRC = Src.isReg() ?
2307 MRI.getRegClass(Src.getReg()) :
2308 &AMDGPU::SGPR_32RegClass;
2309
2310 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2311 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2312
2313 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2314
2315 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2316 AMDGPU::sub0, SrcSubRC);
2317 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2318 AMDGPU::sub1, SrcSubRC);
2319
2320 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2321 .addOperand(SrcRegSub0)
2322 .addImm(0);
2323
2324 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2325 .addOperand(SrcRegSub1)
2326 .addReg(MidReg);
2327
2328 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2329
2330 Worklist.push_back(First);
2331 Worklist.push_back(Second);
2332 }
2333
splitScalar64BitBFE(SmallVectorImpl<MachineInstr * > & Worklist,MachineInstr * Inst) const2334 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2335 MachineInstr *Inst) const {
2336 MachineBasicBlock &MBB = *Inst->getParent();
2337 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2338 MachineBasicBlock::iterator MII = Inst;
2339 DebugLoc DL = Inst->getDebugLoc();
2340
2341 MachineOperand &Dest = Inst->getOperand(0);
2342 uint32_t Imm = Inst->getOperand(2).getImm();
2343 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2344 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2345
2346 (void) Offset;
2347
2348 // Only sext_inreg cases handled.
2349 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2350 BitWidth <= 32 &&
2351 Offset == 0 &&
2352 "Not implemented");
2353
2354 if (BitWidth < 32) {
2355 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2356 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2357 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2358
2359 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2360 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2361 .addImm(0)
2362 .addImm(BitWidth);
2363
2364 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2365 .addImm(31)
2366 .addReg(MidRegLo);
2367
2368 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2369 .addReg(MidRegLo)
2370 .addImm(AMDGPU::sub0)
2371 .addReg(MidRegHi)
2372 .addImm(AMDGPU::sub1);
2373
2374 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2375 return;
2376 }
2377
2378 MachineOperand &Src = Inst->getOperand(1);
2379 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2380 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2381
2382 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2383 .addImm(31)
2384 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2385
2386 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2387 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2388 .addImm(AMDGPU::sub0)
2389 .addReg(TmpReg)
2390 .addImm(AMDGPU::sub1);
2391
2392 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2393 }
2394
addDescImplicitUseDef(const MCInstrDesc & NewDesc,MachineInstr * Inst) const2395 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2396 MachineInstr *Inst) const {
2397 // Add the implict and explicit register definitions.
2398 if (NewDesc.ImplicitUses) {
2399 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2400 unsigned Reg = NewDesc.ImplicitUses[i];
2401 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2402 }
2403 }
2404
2405 if (NewDesc.ImplicitDefs) {
2406 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2407 unsigned Reg = NewDesc.ImplicitDefs[i];
2408 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2409 }
2410 }
2411 }
2412
findUsedSGPR(const MachineInstr * MI,int OpIndices[3]) const2413 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2414 int OpIndices[3]) const {
2415 const MCInstrDesc &Desc = get(MI->getOpcode());
2416
2417 // Find the one SGPR operand we are allowed to use.
2418 unsigned SGPRReg = AMDGPU::NoRegister;
2419
2420 // First we need to consider the instruction's operand requirements before
2421 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2422 // of VCC, but we are still bound by the constant bus requirement to only use
2423 // one.
2424 //
2425 // If the operand's class is an SGPR, we can never move it.
2426
2427 for (const MachineOperand &MO : MI->implicit_operands()) {
2428 // We only care about reads.
2429 if (MO.isDef())
2430 continue;
2431
2432 if (MO.getReg() == AMDGPU::VCC)
2433 return AMDGPU::VCC;
2434
2435 if (MO.getReg() == AMDGPU::FLAT_SCR)
2436 return AMDGPU::FLAT_SCR;
2437 }
2438
2439 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2440 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2441
2442 for (unsigned i = 0; i < 3; ++i) {
2443 int Idx = OpIndices[i];
2444 if (Idx == -1)
2445 break;
2446
2447 const MachineOperand &MO = MI->getOperand(Idx);
2448 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2449 SGPRReg = MO.getReg();
2450
2451 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2452 UsedSGPRs[i] = MO.getReg();
2453 }
2454
2455 if (SGPRReg != AMDGPU::NoRegister)
2456 return SGPRReg;
2457
2458 // We don't have a required SGPR operand, so we have a bit more freedom in
2459 // selecting operands to move.
2460
2461 // Try to select the most used SGPR. If an SGPR is equal to one of the
2462 // others, we choose that.
2463 //
2464 // e.g.
2465 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2466 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2467
2468 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2469 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2470 SGPRReg = UsedSGPRs[0];
2471 }
2472
2473 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2474 if (UsedSGPRs[1] == UsedSGPRs[2])
2475 SGPRReg = UsedSGPRs[1];
2476 }
2477
2478 return SGPRReg;
2479 }
2480
buildIndirectWrite(MachineBasicBlock * MBB,MachineBasicBlock::iterator I,unsigned ValueReg,unsigned Address,unsigned OffsetReg) const2481 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2482 MachineBasicBlock *MBB,
2483 MachineBasicBlock::iterator I,
2484 unsigned ValueReg,
2485 unsigned Address, unsigned OffsetReg) const {
2486 const DebugLoc &DL = MBB->findDebugLoc(I);
2487 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2488 getIndirectIndexBegin(*MBB->getParent()));
2489
2490 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2491 .addReg(IndirectBaseReg, RegState::Define)
2492 .addOperand(I->getOperand(0))
2493 .addReg(IndirectBaseReg)
2494 .addReg(OffsetReg)
2495 .addImm(0)
2496 .addReg(ValueReg);
2497 }
2498
buildIndirectRead(MachineBasicBlock * MBB,MachineBasicBlock::iterator I,unsigned ValueReg,unsigned Address,unsigned OffsetReg) const2499 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2500 MachineBasicBlock *MBB,
2501 MachineBasicBlock::iterator I,
2502 unsigned ValueReg,
2503 unsigned Address, unsigned OffsetReg) const {
2504 const DebugLoc &DL = MBB->findDebugLoc(I);
2505 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2506 getIndirectIndexBegin(*MBB->getParent()));
2507
2508 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2509 .addOperand(I->getOperand(0))
2510 .addOperand(I->getOperand(1))
2511 .addReg(IndirectBaseReg)
2512 .addReg(OffsetReg)
2513 .addImm(0);
2514
2515 }
2516
reserveIndirectRegisters(BitVector & Reserved,const MachineFunction & MF) const2517 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2518 const MachineFunction &MF) const {
2519 int End = getIndirectIndexEnd(MF);
2520 int Begin = getIndirectIndexBegin(MF);
2521
2522 if (End == -1)
2523 return;
2524
2525
2526 for (int Index = Begin; Index <= End; ++Index)
2527 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2528
2529 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2530 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2531
2532 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2533 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2534
2535 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2536 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2537
2538 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2539 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2540
2541 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2542 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2543 }
2544
getNamedOperand(MachineInstr & MI,unsigned OperandName) const2545 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2546 unsigned OperandName) const {
2547 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2548 if (Idx == -1)
2549 return nullptr;
2550
2551 return &MI.getOperand(Idx);
2552 }
2553
getDefaultRsrcDataFormat() const2554 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2555 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2556 if (ST.isAmdHsaOS())
2557 RsrcDataFormat |= (1ULL << 56);
2558
2559 return RsrcDataFormat;
2560 }
2561