1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the SI registers 12//===----------------------------------------------------------------------===// 13 14class SIReg <string n, bits<16> encoding = 0> : Register<n> { 15 let Namespace = "AMDGPU"; 16 let HWEncoding = encoding; 17} 18 19// Special Registers 20def VCC_LO : SIReg<"vcc_lo", 106>; 21def VCC_HI : SIReg<"vcc_hi", 107>; 22 23// VCC for 64-bit instructions 24def VCC : RegisterWithSubRegs<"VCC", [VCC_LO, VCC_HI]> { 25 let Namespace = "AMDGPU"; 26 let SubRegIndices = [sub0, sub1]; 27 let HWEncoding = 106; 28} 29 30def EXEC_LO : SIReg<"exec_lo", 126>; 31def EXEC_HI : SIReg<"exec_hi", 127>; 32 33def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]> { 34 let Namespace = "AMDGPU"; 35 let SubRegIndices = [sub0, sub1]; 36 let HWEncoding = 126; 37} 38 39def SCC : SIReg<"SCC", 253>; 40def M0 : SIReg <"M0", 124>; 41 42def FLAT_SCR_LO : SIReg<"flat_scr_lo", 104>; // Offset in units of 256-bytes. 43def FLAT_SCR_HI : SIReg<"flat_scr_hi", 105>; // Size is the per-thread scratch size, in bytes. 44 45// Pair to indicate location of scratch space for flat accesses. 46def FLAT_SCR : RegisterWithSubRegs <"FLAT_SCR", [FLAT_SCR_LO, FLAT_SCR_HI]> { 47 let Namespace = "AMDGPU"; 48 let SubRegIndices = [sub0, sub1]; 49 let HWEncoding = 104; 50} 51 52// SGPR registers 53foreach Index = 0-101 in { 54 def SGPR#Index : SIReg <"SGPR"#Index, Index>; 55} 56 57// VGPR registers 58foreach Index = 0-255 in { 59 def VGPR#Index : SIReg <"VGPR"#Index, Index> { 60 let HWEncoding{8} = 1; 61 } 62} 63 64//===----------------------------------------------------------------------===// 65// Groupings using register classes and tuples 66//===----------------------------------------------------------------------===// 67 68// SGPR 32-bit registers 69def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, 70 (add (sequence "SGPR%u", 0, 101))>; 71 72// SGPR 64-bit registers 73def SGPR_64Regs : RegisterTuples<[sub0, sub1], 74 [(add (decimate (trunc SGPR_32, 101), 2)), 75 (add (decimate (shl SGPR_32, 1), 2))]>; 76 77// SGPR 128-bit registers 78def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3], 79 [(add (decimate (trunc SGPR_32, 99), 4)), 80 (add (decimate (shl SGPR_32, 1), 4)), 81 (add (decimate (shl SGPR_32, 2), 4)), 82 (add (decimate (shl SGPR_32, 3), 4))]>; 83 84// SGPR 256-bit registers 85def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], 86 [(add (decimate (trunc SGPR_32, 95), 4)), 87 (add (decimate (shl SGPR_32, 1), 4)), 88 (add (decimate (shl SGPR_32, 2), 4)), 89 (add (decimate (shl SGPR_32, 3), 4)), 90 (add (decimate (shl SGPR_32, 4), 4)), 91 (add (decimate (shl SGPR_32, 5), 4)), 92 (add (decimate (shl SGPR_32, 6), 4)), 93 (add (decimate (shl SGPR_32, 7), 4))]>; 94 95// SGPR 512-bit registers 96def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, 97 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15], 98 [(add (decimate (trunc SGPR_32, 87), 4)), 99 (add (decimate (shl SGPR_32, 1), 4)), 100 (add (decimate (shl SGPR_32, 2), 4)), 101 (add (decimate (shl SGPR_32, 3), 4)), 102 (add (decimate (shl SGPR_32, 4), 4)), 103 (add (decimate (shl SGPR_32, 5), 4)), 104 (add (decimate (shl SGPR_32, 6), 4)), 105 (add (decimate (shl SGPR_32, 7), 4)), 106 (add (decimate (shl SGPR_32, 8), 4)), 107 (add (decimate (shl SGPR_32, 9), 4)), 108 (add (decimate (shl SGPR_32, 10), 4)), 109 (add (decimate (shl SGPR_32, 11), 4)), 110 (add (decimate (shl SGPR_32, 12), 4)), 111 (add (decimate (shl SGPR_32, 13), 4)), 112 (add (decimate (shl SGPR_32, 14), 4)), 113 (add (decimate (shl SGPR_32, 15), 4))]>; 114 115// VGPR 32-bit registers 116def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, 117 (add (sequence "VGPR%u", 0, 255))>; 118 119// VGPR 64-bit registers 120def VGPR_64 : RegisterTuples<[sub0, sub1], 121 [(add (trunc VGPR_32, 255)), 122 (add (shl VGPR_32, 1))]>; 123 124// VGPR 96-bit registers 125def VGPR_96 : RegisterTuples<[sub0, sub1, sub2], 126 [(add (trunc VGPR_32, 254)), 127 (add (shl VGPR_32, 1)), 128 (add (shl VGPR_32, 2))]>; 129 130// VGPR 128-bit registers 131def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3], 132 [(add (trunc VGPR_32, 253)), 133 (add (shl VGPR_32, 1)), 134 (add (shl VGPR_32, 2)), 135 (add (shl VGPR_32, 3))]>; 136 137// VGPR 256-bit registers 138def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], 139 [(add (trunc VGPR_32, 249)), 140 (add (shl VGPR_32, 1)), 141 (add (shl VGPR_32, 2)), 142 (add (shl VGPR_32, 3)), 143 (add (shl VGPR_32, 4)), 144 (add (shl VGPR_32, 5)), 145 (add (shl VGPR_32, 6)), 146 (add (shl VGPR_32, 7))]>; 147 148// VGPR 512-bit registers 149def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, 150 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15], 151 [(add (trunc VGPR_32, 241)), 152 (add (shl VGPR_32, 1)), 153 (add (shl VGPR_32, 2)), 154 (add (shl VGPR_32, 3)), 155 (add (shl VGPR_32, 4)), 156 (add (shl VGPR_32, 5)), 157 (add (shl VGPR_32, 6)), 158 (add (shl VGPR_32, 7)), 159 (add (shl VGPR_32, 8)), 160 (add (shl VGPR_32, 9)), 161 (add (shl VGPR_32, 10)), 162 (add (shl VGPR_32, 11)), 163 (add (shl VGPR_32, 12)), 164 (add (shl VGPR_32, 13)), 165 (add (shl VGPR_32, 14)), 166 (add (shl VGPR_32, 15))]>; 167 168//===----------------------------------------------------------------------===// 169// Register classes used as source and destination 170//===----------------------------------------------------------------------===// 171 172// Special register classes for predicates and the M0 register 173def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> { 174 let CopyCost = -1; // Theoretically it is possible to read from SCC, 175 // but it should never be necessary. 176} 177 178def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>; 179def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>; 180def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>; 181 182// Register class for all scalar registers (SGPRs + Special Registers) 183def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, 184 (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI) 185>; 186 187def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>; 188 189def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 64, 190 (add SGPR_64, VCCReg, EXECReg, FLAT_SCR) 191>; 192 193def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>; 194 195def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>; 196 197def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>; 198 199// Register class for all vector registers (VGPRs + Interploation Registers) 200def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>; 201 202def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> { 203 let Size = 96; 204} 205 206def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>; 207 208def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>; 209 210def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>; 211 212def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> { 213 let Size = 32; 214} 215 216class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> { 217 let OperandNamespace = "AMDGPU"; 218 let OperandType = "OPERAND_REG_IMM32"; 219} 220 221class RegInlineOperand <RegisterClass rc> : RegisterOperand<rc> { 222 let OperandNamespace = "AMDGPU"; 223 let OperandType = "OPERAND_REG_INLINE_C"; 224} 225 226//===----------------------------------------------------------------------===// 227// SSrc_* Operands with an SGPR or a 32-bit immediate 228//===----------------------------------------------------------------------===// 229 230def SSrc_32 : RegImmOperand<SReg_32>; 231 232def SSrc_64 : RegImmOperand<SReg_64>; 233 234//===----------------------------------------------------------------------===// 235// SCSrc_* Operands with an SGPR or a inline constant 236//===----------------------------------------------------------------------===// 237 238def SCSrc_32 : RegInlineOperand<SReg_32>; 239 240//===----------------------------------------------------------------------===// 241// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 242//===----------------------------------------------------------------------===// 243 244def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>; 245 246def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>; 247 248def VSrc_32 : RegImmOperand<VS_32>; 249 250def VSrc_64 : RegImmOperand<VS_64>; 251 252//===----------------------------------------------------------------------===// 253// VCSrc_* Operands with an SGPR, VGPR or an inline constant 254//===----------------------------------------------------------------------===// 255 256def VCSrc_32 : RegInlineOperand<VS_32>; 257 258def VCSrc_64 : RegInlineOperand<VS_64>; 259 260//===----------------------------------------------------------------------===// 261// SGPR and VGPR register classes 262//===----------------------------------------------------------------------===// 263 264def VSrc_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, 265 (add VReg_128, SReg_128)>; 266