1//===-- SISchedule.td - SI Scheduling definitons -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// MachineModel definitions for Southern Islands (SI)
11//
12//===----------------------------------------------------------------------===//
13
14def WriteBranch : SchedWrite;
15def WriteExport : SchedWrite;
16def WriteLDS    : SchedWrite;
17def WriteSALU   : SchedWrite;
18def WriteSMEM   : SchedWrite;
19def WriteVMEM   : SchedWrite;
20
21// Vector ALU instructions
22def Write32Bit         : SchedWrite;
23def WriteQuarterRate32 : SchedWrite;
24
25def WriteFloatFMA   : SchedWrite;
26
27def WriteDouble     : SchedWrite;
28def WriteDoubleAdd  : SchedWrite;
29
30def SIFullSpeedModel : SchedMachineModel;
31def SIQuarterSpeedModel : SchedMachineModel;
32
33// BufferSize = 0 means the processors are in-order.
34let BufferSize = 0 in {
35
36// XXX: Are the resource counts correct?
37def HWBranch : ProcResource<1>;
38def HWExport : ProcResource<7>;   // Taken from S_WAITCNT
39def HWLGKM   : ProcResource<31>;  // Taken from S_WAITCNT
40def HWSALU   : ProcResource<1>;
41def HWVMEM   : ProcResource<15>;  // Taken from S_WAITCNT
42def HWVALU   : ProcResource<1>;
43
44}
45
46class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
47                 int latency> : WriteRes<write, resources> {
48  let Latency = latency;
49}
50
51class HWVALUWriteRes<SchedWrite write, int latency> :
52  HWWriteRes<write, [HWVALU], latency>;
53
54
55// The latency numbers are taken from AMD Accelerated Parallel Processing
56// guide.  They may not be acurate.
57
58// The latency values are 1 / (operations / cycle) / 4.
59multiclass SICommonWriteRes {
60
61  def : HWWriteRes<WriteBranch,  [HWBranch], 100>; // XXX: Guessed ???
62  def : HWWriteRes<WriteExport,  [HWExport], 100>; // XXX: Guessed ???
63  def : HWWriteRes<WriteLDS,     [HWLGKM],    32>; // 2 - 64
64  def : HWWriteRes<WriteSALU,    [HWSALU],     1>;
65  def : HWWriteRes<WriteSMEM,    [HWLGKM],    10>; // XXX: Guessed ???
66  def : HWWriteRes<WriteVMEM,    [HWVMEM],   450>; // 300 - 600
67
68  def : HWVALUWriteRes<Write32Bit,         1>;
69  def : HWVALUWriteRes<WriteQuarterRate32, 4>;
70}
71
72
73let SchedModel = SIFullSpeedModel in {
74
75defm : SICommonWriteRes;
76
77def : HWVALUWriteRes<WriteFloatFMA,   1>;
78def : HWVALUWriteRes<WriteDouble,     4>;
79def : HWVALUWriteRes<WriteDoubleAdd,  2>;
80
81} // End SchedModel = SIFullSpeedModel
82
83let SchedModel = SIQuarterSpeedModel in {
84
85defm : SICommonWriteRes;
86
87def : HWVALUWriteRes<WriteFloatFMA, 16>;
88def : HWVALUWriteRes<WriteDouble,   16>;
89def : HWVALUWriteRes<WriteDoubleAdd, 8>;
90
91}  // End SchedModel = SIQuarterSpeedModel
92