1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
11          : Instruction {
12  field bits<32> Inst;
13
14  let Namespace = "SP";
15
16  bits<2> op;
17  let Inst{31-30} = op;               // Top two bits are the 'op' field
18
19  dag OutOperandList = outs;
20  dag InOperandList = ins;
21  let AsmString   = asmstr;
22  let Pattern = pattern;
23}
24
25//===----------------------------------------------------------------------===//
26// Format #2 instruction classes in the Sparc
27//===----------------------------------------------------------------------===//
28
29// Format 2 instructions
30class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
31   : InstSP<outs, ins, asmstr, pattern> {
32  bits<3>  op2;
33  bits<22> imm22;
34  let op          = 0;    // op = 0
35  let Inst{24-22} = op2;
36  let Inst{21-0}  = imm22;
37}
38
39// Specific F2 classes: SparcV8 manual, page 44
40//
41class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
42   : F2<outs, ins, asmstr, pattern> {
43  bits<5>  rd;
44
45  let op2         = op2Val;
46
47  let Inst{29-25} = rd;
48}
49
50class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
51           list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
52  bits<4>   cond;
53  bit       annul = 0;     // currently unused
54
55  let op2         = op2Val;
56
57  let Inst{29}    = annul;
58  let Inst{28-25} = cond;
59}
60
61//===----------------------------------------------------------------------===//
62// Format #3 instruction classes in the Sparc
63//===----------------------------------------------------------------------===//
64
65class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
66    : InstSP<outs, ins, asmstr, pattern> {
67  bits<5> rd;
68  bits<6> op3;
69  bits<5> rs1;
70  let op{1} = 1;   // Op = 2 or 3
71  let Inst{29-25} = rd;
72  let Inst{24-19} = op3;
73  let Inst{18-14} = rs1;
74}
75
76// Specific F3 classes: SparcV8 manual, page 44
77//
78class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
79           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
80  bits<8> asi = 0; // asi not currently used
81  bits<5> rs2;
82
83  let op         = opVal;
84  let op3        = op3val;
85
86  let Inst{13}   = 0;     // i field = 0
87  let Inst{12-5} = asi;   // address space identifier
88  let Inst{4-0}  = rs2;
89}
90
91class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
92           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
93  bits<13> simm13;
94
95  let op         = opVal;
96  let op3        = op3val;
97
98  let Inst{13}   = 1;     // i field = 1
99  let Inst{12-0} = simm13;
100}
101
102// floating-point
103class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
104           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
105  bits<5> rs2;
106
107  let op         = opVal;
108  let op3        = op3val;
109
110  let Inst{13-5} = opfval;   // fp opcode
111  let Inst{4-0}  = rs2;
112}
113
114// floating-point unary operations.
115class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
116           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
117  bits<5> rs2;
118
119  let op         = opVal;
120  let op3        = op3val;
121  let rs1        = 0;
122
123  let Inst{13-5} = opfval;   // fp opcode
124  let Inst{4-0}  = rs2;
125}
126
127// floating-point compares.
128class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
129           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
130  bits<5> rs2;
131
132  let op         = opVal;
133  let op3        = op3val;
134  let rd         = 0;
135
136  let Inst{13-5} = opfval;   // fp opcode
137  let Inst{4-0}  = rs2;
138}
139
140// Shift by register rs2.
141class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
142            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
143  bit x = xVal;           // 1 for 64-bit shifts.
144  bits<5> rs2;
145
146  let op         = opVal;
147  let op3        = op3val;
148
149  let Inst{13}   = 0;     // i field = 0
150  let Inst{12}   = x;     // extended registers.
151  let Inst{4-0}  = rs2;
152}
153
154// Shift by immediate.
155class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
156            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
157  bit x = xVal;           // 1 for 64-bit shifts.
158  bits<6> shcnt;          // shcnt32 / shcnt64.
159
160  let op         = opVal;
161  let op3        = op3val;
162
163  let Inst{13}   = 1;     // i field = 1
164  let Inst{12}   = x;     // extended registers.
165  let Inst{5-0}  = shcnt;
166}
167
168// Define rr and ri shift instructions with patterns.
169multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
170                ValueType VT, RegisterClass RC> {
171  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
172                 !strconcat(OpcStr, " $rs, $rs2, $rd"),
173                 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
174  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
175                 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
176                 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
177}
178
179class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
180      : InstSP<outs, ins, asmstr, pattern> {
181  bits<5> rd;
182
183  let op          = 2;
184  let Inst{29-25} = rd;
185  let Inst{24-19} = op3;
186}
187
188
189class F4_1<bits<6> op3, dag outs, dag ins,
190            string asmstr, list<dag> pattern>
191      : F4<op3, outs, ins, asmstr, pattern> {
192
193  bits<3> cc;
194  bits<4> cond;
195  bits<5> rs2;
196
197  let Inst{4-0}   = rs2;
198  let Inst{11}    = cc{0};
199  let Inst{12}    = cc{1};
200  let Inst{13}    = 0;
201  let Inst{17-14} = cond;
202  let Inst{18}    = cc{2};
203
204}
205
206class F4_2<bits<6> op3, dag outs, dag ins,
207            string asmstr, list<dag> pattern>
208      : F4<op3, outs, ins, asmstr, pattern> {
209  bits<3>  cc;
210  bits<4>  cond;
211  bits<11> simm11;
212
213  let Inst{10-0}  = simm11;
214  let Inst{11}    = cc{0};
215  let Inst{12}    = cc{1};
216  let Inst{13}    = 1;
217  let Inst{17-14} = cond;
218  let Inst{18}    = cc{2};
219}
220
221class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
222           string asmstr, list<dag> pattern>
223      : F4<op3, outs, ins, asmstr, pattern> {
224  bits<4> cond;
225  bits<3> opf_cc;
226  bits<5> rs2;
227
228  let Inst{18}     = 0;
229  let Inst{17-14}  = cond;
230  let Inst{13-11}  = opf_cc;
231  let Inst{10-5}   = opf_low;
232  let Inst{4-0}    = rs2;
233}
234