1 //===-- TargetSubtargetInfo.cpp - General Target Information ---------------==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the general parts of a Subtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/CommandLine.h" 15 #include "llvm/Target/TargetSubtargetInfo.h" 16 #include "llvm/ADT/SmallVector.h" 17 using namespace llvm; 18 19 //--------------------------------------------------------------------------- 20 // TargetSubtargetInfo Class 21 // 22 TargetSubtargetInfo::TargetSubtargetInfo() {} 23 24 TargetSubtargetInfo::~TargetSubtargetInfo() {} 25 26 // Temporary option to compare overall performance change when moving from the 27 // SD scheduler to the MachineScheduler pass pipeline. It should be removed 28 // before 3.4. The normal way to enable/disable the MachineScheduling pass 29 // itself is by using -enable-misched. For targets that already use MI sched 30 // (via MySubTarget::enableMachineScheduler()) -misched-bench=false negates the 31 // subtarget hook. 32 static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden, 33 cl::desc("Migrate from the target's default SD scheduler to MI scheduler")); 34 35 bool TargetSubtargetInfo::useMachineScheduler() const { 36 if (BenchMachineSched.getNumOccurrences()) 37 return BenchMachineSched; 38 return enableMachineScheduler(); 39 } 40 41 bool TargetSubtargetInfo::enableMachineScheduler() const { 42 return false; 43 } 44 45 bool TargetSubtargetInfo::enablePostRAScheduler( 46 CodeGenOpt::Level OptLevel, 47 AntiDepBreakMode& Mode, 48 RegClassVector& CriticalPathRCs) const { 49 Mode = ANTIDEP_NONE; 50 CriticalPathRCs.clear(); 51 return false; 52 } 53 54 bool TargetSubtargetInfo::useAA() const { 55 return false; 56 } 57