1// Group template arguments that can be derived from the vector type (EltNum x 2// EltVT). These are things like the register class for the writemask, etc. 3// The idea is to pass one of these as the template argument rather than the 4// individual arguments. 5// The template is also used for scalar types, in this case numelts is 1. 6class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc, 7 string suffix = ""> { 8 RegisterClass RC = rc; 9 ValueType EltVT = eltvt; 10 int NumElts = numelts; 11 12 // Corresponding mask register class. 13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts); 14 15 // Corresponding write-mask register class. 16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM"); 17 18 // The GPR register class that can hold the write mask. Use GR8 for fewer 19 // than 8 elements. Use shift-right and equal to work around the lack of 20 // !lt in tablegen. 21 RegisterClass MRC = 22 !cast<RegisterClass>("GR" # 23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts)); 24 25 // Suffix used in the instruction mnemonic. 26 string Suffix = suffix; 27 28 // VTName is a string name for vector VT. For vector types it will be 29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32 30 // It is a little bit complex for scalar types, where NumElts = 1. 31 // In this case we build v4f32 or v2f64 32 string VTName = "v" # !if (!eq (NumElts, 1), 33 !if (!eq (EltVT.Size, 32), 4, 34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT; 35 36 // The vector VT. 37 ValueType VT = !cast<ValueType>(VTName); 38 39 string EltTypeName = !cast<string>(EltVT); 40 // Size of the element type in bits, e.g. 32 for v16i32. 41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName)); 42 int EltSize = EltVT.Size; 43 44 // "i" for integer types and "f" for floating-point types 45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName); 46 47 // Size of RC in bits, e.g. 512 for VR512. 48 int Size = VT.Size; 49 50 // The corresponding memory operand, e.g. i512mem for VR512. 51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem"); 52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem"); 53 54 // Load patterns 55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64 56 // due to load promotion during legalization 57 PatFrag LdFrag = !cast<PatFrag>("load" # 58 !if (!eq (TypeVariantName, "i"), 59 !if (!eq (Size, 128), "v2i64", 60 !if (!eq (Size, 256), "v4i64", 61 VTName)), VTName)); 62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT); 63 64 // Load patterns used for memory operands. We only have this defined in 65 // case of i64 element types for sub-512 integer vectors. For now, keep 66 // MemOpFrag undefined in these cases. 67 PatFrag MemOpFrag = 68 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"), 69 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"), 70 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName), 71 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName), 72 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?))))); 73 74 // The corresponding float type, e.g. v16f32 for v16i32 75 // Note: For EltSize < 32, FloatVT is illegal and TableGen 76 // fails to compile, so we choose FloatVT = VT 77 ValueType FloatVT = !cast<ValueType>( 78 !if (!eq (!srl(EltSize,5),0), 79 VTName, 80 !if (!eq(TypeVariantName, "i"), 81 "v" # NumElts # "f" # EltSize, 82 VTName))); 83 84 // The string to specify embedded broadcast in assembly. 85 string BroadcastStr = "{1to" # NumElts # "}"; 86 87 // 8-bit compressed displacement tuple/subvector format. This is only 88 // defined for NumElts <= 8. 89 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0), 90 !cast<CD8VForm>("CD8VT" # NumElts), ?); 91 92 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm, 93 !if (!eq (Size, 256), sub_ymm, ?)); 94 95 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle, 96 !if (!eq (EltTypeName, "f64"), SSEPackedDouble, 97 SSEPackedInt)); 98 99 // A vector type of the same width with element type i32. This is used to 100 // create the canonical constant zero node ImmAllZerosV. 101 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32"); 102 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV))); 103} 104 105def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">; 106def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">; 107def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">; 108def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">; 109def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">; 110def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">; 111 112// "x" in v32i8x_info means RC = VR256X 113def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">; 114def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">; 115def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">; 116def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">; 117def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">; 118def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">; 119 120def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">; 121def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">; 122def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">; 123def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">; 124def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">; 125def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">; 126 127// We map scalar types to the smallest (128-bit) vector type 128// with the appropriate element type. This allows to use the same masking logic. 129def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">; 130def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">; 131 132class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256, 133 X86VectorVTInfo i128> { 134 X86VectorVTInfo info512 = i512; 135 X86VectorVTInfo info256 = i256; 136 X86VectorVTInfo info128 = i128; 137} 138 139def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info, 140 v16i8x_info>; 141def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info, 142 v8i16x_info>; 143def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info, 144 v4i32x_info>; 145def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info, 146 v2i64x_info>; 147def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info, 148 v4f32x_info>; 149def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info, 150 v2f64x_info>; 151 152// This multiclass generates the masking variants from the non-masking 153// variant. It only provides the assembly pieces for the masking variants. 154// It assumes custom ISel patterns for masking which can be provided as 155// template arguments. 156multiclass AVX512_maskable_custom<bits<8> O, Format F, 157 dag Outs, 158 dag Ins, dag MaskingIns, dag ZeroMaskingIns, 159 string OpcodeStr, 160 string AttSrcAsm, string IntelSrcAsm, 161 list<dag> Pattern, 162 list<dag> MaskingPattern, 163 list<dag> ZeroMaskingPattern, 164 string Round = "", 165 string MaskingConstraint = "", 166 InstrItinClass itin = NoItinerary, 167 bit IsCommutable = 0> { 168 let isCommutable = IsCommutable in 169 def NAME: AVX512<O, F, Outs, Ins, 170 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"# 171 "$dst "#Round#", "#IntelSrcAsm#"}", 172 Pattern, itin>; 173 174 // Prefer over VMOV*rrk Pat<> 175 let AddedComplexity = 20 in 176 def NAME#k: AVX512<O, F, Outs, MaskingIns, 177 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"# 178 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}", 179 MaskingPattern, itin>, 180 EVEX_K { 181 // In case of the 3src subclass this is overridden with a let. 182 string Constraints = MaskingConstraint; 183 } 184 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<> 185 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns, 186 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"# 187 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}", 188 ZeroMaskingPattern, 189 itin>, 190 EVEX_KZ; 191} 192 193 194// Common base class of AVX512_maskable and AVX512_maskable_3src. 195multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _, 196 dag Outs, 197 dag Ins, dag MaskingIns, dag ZeroMaskingIns, 198 string OpcodeStr, 199 string AttSrcAsm, string IntelSrcAsm, 200 dag RHS, dag MaskingRHS, 201 SDNode Select = vselect, string Round = "", 202 string MaskingConstraint = "", 203 InstrItinClass itin = NoItinerary, 204 bit IsCommutable = 0> : 205 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr, 206 AttSrcAsm, IntelSrcAsm, 207 [(set _.RC:$dst, RHS)], 208 [(set _.RC:$dst, MaskingRHS)], 209 [(set _.RC:$dst, 210 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))], 211 Round, MaskingConstraint, NoItinerary, IsCommutable>; 212 213// This multiclass generates the unconditional/non-masking, the masking and 214// the zero-masking variant of the vector instruction. In the masking case, the 215// perserved vector elements come from a new dummy input operand tied to $dst. 216multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _, 217 dag Outs, dag Ins, string OpcodeStr, 218 string AttSrcAsm, string IntelSrcAsm, 219 dag RHS, string Round = "", 220 InstrItinClass itin = NoItinerary, 221 bit IsCommutable = 0> : 222 AVX512_maskable_common<O, F, _, Outs, Ins, 223 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins), 224 !con((ins _.KRCWM:$mask), Ins), 225 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS, 226 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect, 227 Round, "$src0 = $dst", itin, IsCommutable>; 228 229// This multiclass generates the unconditional/non-masking, the masking and 230// the zero-masking variant of the scalar instruction. 231multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _, 232 dag Outs, dag Ins, string OpcodeStr, 233 string AttSrcAsm, string IntelSrcAsm, 234 dag RHS, string Round = "", 235 InstrItinClass itin = NoItinerary, 236 bit IsCommutable = 0> : 237 AVX512_maskable_common<O, F, _, Outs, Ins, 238 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins), 239 !con((ins _.KRCWM:$mask), Ins), 240 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS, 241 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select, 242 Round, "$src0 = $dst", itin, IsCommutable>; 243 244// Similar to AVX512_maskable but in this case one of the source operands 245// ($src1) is already tied to $dst so we just use that for the preserved 246// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude 247// $src1. 248multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _, 249 dag Outs, dag NonTiedIns, string OpcodeStr, 250 string AttSrcAsm, string IntelSrcAsm, 251 dag RHS> : 252 AVX512_maskable_common<O, F, _, Outs, 253 !con((ins _.RC:$src1), NonTiedIns), 254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns), 255 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns), 256 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS, 257 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>; 258 259 260multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _, 261 dag Outs, dag Ins, 262 string OpcodeStr, 263 string AttSrcAsm, string IntelSrcAsm, 264 list<dag> Pattern> : 265 AVX512_maskable_custom<O, F, Outs, Ins, 266 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins), 267 !con((ins _.KRCWM:$mask), Ins), 268 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "", 269 "$src0 = $dst">; 270 271// Bitcasts between 512-bit vector types. Return the original type since 272// no instruction is needed for the conversion 273let Predicates = [HasAVX512] in { 274 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>; 275 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>; 276 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>; 277 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>; 278 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>; 279 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>; 280 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>; 281 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>; 282 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>; 283 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>; 284 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>; 285 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>; 286 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>; 287 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>; 288 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>; 289 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>; 290 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>; 291 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>; 292 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>; 293 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>; 294 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>; 295 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>; 296 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>; 297 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>; 298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>; 299 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>; 300 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>; 301 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>; 302 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>; 303 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>; 304 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>; 305 306 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>; 307 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>; 308 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>; 309 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>; 310 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>; 311 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>; 312 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>; 313 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>; 314 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>; 315 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>; 316 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>; 317 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>; 318 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>; 319 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>; 320 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>; 321 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>; 322 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>; 323 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>; 324 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>; 325 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>; 326 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>; 327 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>; 328 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>; 329 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>; 330 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>; 331 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>; 332 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>; 333 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>; 334 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>; 335 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>; 336 337// Bitcasts between 256-bit vector types. Return the original type since 338// no instruction is needed for the conversion 339 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>; 340 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>; 341 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>; 342 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>; 343 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>; 344 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>; 345 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>; 346 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>; 347 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>; 348 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>; 349 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>; 350 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>; 351 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>; 352 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>; 353 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>; 354 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>; 355 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>; 356 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>; 357 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>; 358 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>; 359 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>; 360 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>; 361 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>; 362 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>; 363 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>; 364 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>; 365 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>; 366 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>; 367 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>; 368 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>; 369} 370 371// 372// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros. 373// 374 375let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, 376 isPseudo = 1, Predicates = [HasAVX512] in { 377def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "", 378 [(set VR512:$dst, (v16f32 immAllZerosV))]>; 379} 380 381let Predicates = [HasAVX512] in { 382def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>; 383def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>; 384def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>; 385} 386 387//===----------------------------------------------------------------------===// 388// AVX-512 - VECTOR INSERT 389// 390 391multiclass vinsert_for_size_no_alt<int Opcode, 392 X86VectorVTInfo From, X86VectorVTInfo To, 393 PatFrag vinsert_insert, 394 SDNodeXForm INSERT_get_vinsert_imm> { 395 let hasSideEffects = 0, ExeDomain = To.ExeDomain in { 396 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst), 397 (ins VR512:$src1, From.RC:$src2, i8imm:$src3), 398 "vinsert" # From.EltTypeName # "x" # From.NumElts # 399 "\t{$src3, $src2, $src1, $dst|" 400 "$dst, $src1, $src2, $src3}", 401 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1), 402 (From.VT From.RC:$src2), 403 (iPTR imm)))]>, 404 EVEX_4V, EVEX_V512; 405 406 let mayLoad = 1 in 407 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst), 408 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3), 409 "vinsert" # From.EltTypeName # "x" # From.NumElts # 410 "\t{$src3, $src2, $src1, $dst|" 411 "$dst, $src1, $src2, $src3}", 412 []>, 413 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>; 414 } 415} 416 417multiclass vinsert_for_size<int Opcode, 418 X86VectorVTInfo From, X86VectorVTInfo To, 419 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo, 420 PatFrag vinsert_insert, 421 SDNodeXForm INSERT_get_vinsert_imm> : 422 vinsert_for_size_no_alt<Opcode, From, To, 423 vinsert_insert, INSERT_get_vinsert_imm> { 424 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for 425 // vinserti32x4. Only add this if 64x2 and friends are not supported 426 // natively via AVX512DQ. 427 let Predicates = [NoDQI] in 428 def : Pat<(vinsert_insert:$ins 429 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)), 430 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr") 431 VR512:$src1, From.RC:$src2, 432 (INSERT_get_vinsert_imm VR512:$ins)))>; 433} 434 435multiclass vinsert_for_type<ValueType EltVT32, int Opcode128, 436 ValueType EltVT64, int Opcode256> { 437 defm NAME # "32x4" : vinsert_for_size<Opcode128, 438 X86VectorVTInfo< 4, EltVT32, VR128X>, 439 X86VectorVTInfo<16, EltVT32, VR512>, 440 X86VectorVTInfo< 2, EltVT64, VR128X>, 441 X86VectorVTInfo< 8, EltVT64, VR512>, 442 vinsert128_insert, 443 INSERT_get_vinsert128_imm>; 444 let Predicates = [HasDQI] in 445 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128, 446 X86VectorVTInfo< 2, EltVT64, VR128X>, 447 X86VectorVTInfo< 8, EltVT64, VR512>, 448 vinsert128_insert, 449 INSERT_get_vinsert128_imm>, VEX_W; 450 defm NAME # "64x4" : vinsert_for_size<Opcode256, 451 X86VectorVTInfo< 4, EltVT64, VR256X>, 452 X86VectorVTInfo< 8, EltVT64, VR512>, 453 X86VectorVTInfo< 8, EltVT32, VR256>, 454 X86VectorVTInfo<16, EltVT32, VR512>, 455 vinsert256_insert, 456 INSERT_get_vinsert256_imm>, VEX_W; 457 let Predicates = [HasDQI] in 458 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256, 459 X86VectorVTInfo< 8, EltVT32, VR256X>, 460 X86VectorVTInfo<16, EltVT32, VR512>, 461 vinsert256_insert, 462 INSERT_get_vinsert256_imm>; 463} 464 465defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>; 466defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>; 467 468// vinsertps - insert f32 to XMM 469def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst), 470 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3), 471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 472 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>, 473 EVEX_4V; 474def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst), 475 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3), 476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 477 [(set VR128X:$dst, (X86insertps VR128X:$src1, 478 (v4f32 (scalar_to_vector (loadf32 addr:$src2))), 479 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>; 480 481//===----------------------------------------------------------------------===// 482// AVX-512 VECTOR EXTRACT 483//--- 484 485multiclass vextract_for_size<int Opcode, 486 X86VectorVTInfo From, X86VectorVTInfo To, 487 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo, 488 PatFrag vextract_extract, 489 SDNodeXForm EXTRACT_get_vextract_imm> { 490 let hasSideEffects = 0, ExeDomain = To.ExeDomain in { 491 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst), 492 (ins VR512:$src1, i8imm:$idx), 493 "vextract" # To.EltTypeName # "x4", 494 "$idx, $src1", "$src1, $idx", 495 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1), 496 (iPTR imm)))]>, 497 AVX512AIi8Base, EVEX, EVEX_V512; 498 let mayStore = 1 in 499 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs), 500 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2), 501 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|" 502 "$dst, $src1, $src2}", 503 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>; 504 } 505 506 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for 507 // vextracti32x4 508 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)), 509 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr") 510 VR512:$src1, 511 (EXTRACT_get_vextract_imm To.RC:$ext)))>; 512 513 // A 128/256-bit subvector extract from the first 512-bit vector position is 514 // a subregister copy that needs no instruction. 515 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))), 516 (To.VT 517 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>; 518 519 // And for the alternative types. 520 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))), 521 (AltTo.VT 522 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>; 523 524 // Intrinsic call with masking. 525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName # 526 "x4_512") 527 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask), 528 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0, 529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)), 530 VR512:$src1, imm:$idx)>; 531 532 // Intrinsic call with zero-masking. 533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName # 534 "x4_512") 535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask), 536 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz") 537 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)), 538 VR512:$src1, imm:$idx)>; 539 540 // Intrinsic call without masking. 541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName # 542 "x4_512") 543 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)), 544 (!cast<Instruction>(NAME # To.EltSize # "x4rr") 545 VR512:$src1, imm:$idx)>; 546} 547 548multiclass vextract_for_type<ValueType EltVT32, int Opcode32, 549 ValueType EltVT64, int Opcode64> { 550 defm NAME # "32x4" : vextract_for_size<Opcode32, 551 X86VectorVTInfo<16, EltVT32, VR512>, 552 X86VectorVTInfo< 4, EltVT32, VR128X>, 553 X86VectorVTInfo< 8, EltVT64, VR512>, 554 X86VectorVTInfo< 2, EltVT64, VR128X>, 555 vextract128_extract, 556 EXTRACT_get_vextract128_imm>; 557 defm NAME # "64x4" : vextract_for_size<Opcode64, 558 X86VectorVTInfo< 8, EltVT64, VR512>, 559 X86VectorVTInfo< 4, EltVT64, VR256X>, 560 X86VectorVTInfo<16, EltVT32, VR512>, 561 X86VectorVTInfo< 8, EltVT32, VR256>, 562 vextract256_extract, 563 EXTRACT_get_vextract256_imm>, VEX_W; 564} 565 566defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>; 567defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>; 568 569// A 128-bit subvector insert to the first 512-bit vector position 570// is a subregister copy that needs no instruction. 571def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)), 572 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), 573 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 574 sub_ymm)>; 575def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)), 576 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), 577 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 578 sub_ymm)>; 579def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)), 580 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), 581 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 582 sub_ymm)>; 583def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)), 584 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), 585 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 586 sub_ymm)>; 587 588def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)), 589 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 590def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)), 591 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 592def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)), 593 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 594def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)), 595 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 596 597// vextractps - extract 32 bits from XMM 598def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst), 599 (ins VR128X:$src1, i32i8imm:$src2), 600 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 601 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>, 602 EVEX; 603 604def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs), 605 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2), 606 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 607 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2), 608 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>; 609 610//===---------------------------------------------------------------------===// 611// AVX-512 BROADCAST 612//--- 613multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC, 614 ValueType svt, X86VectorVTInfo _> { 615 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 616 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix), 617 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>, 618 T8PD, EVEX; 619 620 let mayLoad = 1 in { 621 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 622 (ins _.ScalarMemOp:$src), 623 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src", 624 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>, 625 T8PD, EVEX; 626 } 627} 628 629multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode, 630 AVX512VLVectorVTInfo _> { 631 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>, 632 EVEX_V512; 633 634 let Predicates = [HasVLX] in { 635 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>, 636 EVEX_V256; 637 } 638} 639 640let ExeDomain = SSEPackedSingle in { 641 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast, 642 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>; 643 let Predicates = [HasVLX] in { 644 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X, 645 v4f32, v4f32x_info>, EVEX_V128, 646 EVEX_CD8<32, CD8VT1>; 647 } 648} 649 650let ExeDomain = SSEPackedDouble in { 651 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast, 652 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>; 653} 654 655// avx512_broadcast_pat introduces patterns for broadcast with a scalar argument. 656// Later, we can canonize broadcast instructions before ISel phase and 657// eliminate additional patterns on ISel. 658// SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar 659// representations of source 660multiclass avx512_broadcast_pat<string InstName, SDNode OpNode, 661 X86VectorVTInfo _, RegisterClass SrcRC_v, 662 RegisterClass SrcRC_s> { 663 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))), 664 (!cast<Instruction>(InstName##"r") 665 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>; 666 667 let AddedComplexity = 30 in { 668 def : Pat<(_.VT (vselect _.KRCWM:$mask, 669 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)), 670 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask, 671 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>; 672 673 def : Pat<(_.VT(vselect _.KRCWM:$mask, 674 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)), 675 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask, 676 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>; 677 } 678} 679 680defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info, 681 VR128X, FR32X>; 682defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info, 683 VR128X, FR64X>; 684 685let Predicates = [HasVLX] in { 686 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast, 687 v8f32x_info, VR128X, FR32X>; 688 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast, 689 v4f32x_info, VR128X, FR32X>; 690 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast, 691 v4f64x_info, VR128X, FR64X>; 692} 693 694def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))), 695 (VBROADCASTSSZm addr:$src)>; 696def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))), 697 (VBROADCASTSDZm addr:$src)>; 698 699def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src), 700 (VBROADCASTSSZm addr:$src)>; 701def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src), 702 (VBROADCASTSDZm addr:$src)>; 703 704multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _, 705 RegisterClass SrcRC> { 706 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst), 707 (ins SrcRC:$src), "vpbroadcast"##_.Suffix, 708 "$src", "$src", []>, T8PD, EVEX; 709} 710 711multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _, 712 RegisterClass SrcRC, Predicate prd> { 713 let Predicates = [prd] in 714 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512; 715 let Predicates = [prd, HasVLX] in { 716 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256; 717 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128; 718 } 719} 720 721defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32, 722 HasBWI>; 723defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32, 724 HasBWI>; 725defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32, 726 HasAVX512>; 727defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64, 728 HasAVX512>, VEX_W; 729 730def : Pat <(v16i32 (X86vzext VK16WM:$mask)), 731 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>; 732 733def : Pat <(v8i64 (X86vzext VK8WM:$mask)), 734 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>; 735 736def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))), 737 (VPBROADCASTDrZr GR32:$src)>; 738def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))), 739 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>; 740def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))), 741 (VPBROADCASTQrZr GR64:$src)>; 742def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))), 743 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>; 744 745def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))), 746 (VPBROADCASTDrZr GR32:$src)>; 747def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))), 748 (VPBROADCASTQrZr GR64:$src)>; 749 750def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src), 751 (v16i32 immAllZerosV), (i16 GR16:$mask))), 752 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>; 753def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src), 754 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))), 755 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>; 756 757multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr, 758 X86MemOperand x86memop, PatFrag ld_frag, 759 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT, 760 RegisterClass KRC> { 761 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src), 762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 763 [(set DstRC:$dst, 764 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX; 765 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask, 766 VR128X:$src), 767 !strconcat(OpcodeStr, 768 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 769 [(set DstRC:$dst, 770 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>, 771 EVEX, EVEX_KZ; 772 let mayLoad = 1 in { 773 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 775 [(set DstRC:$dst, 776 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX; 777 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask, 778 x86memop:$src), 779 !strconcat(OpcodeStr, 780 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 781 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask, 782 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ; 783 } 784} 785 786defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem, 787 loadi32, VR512, v16i32, v4i32, VK16WM>, 788 EVEX_V512, EVEX_CD8<32, CD8VT1>; 789defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem, 790 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W, 791 EVEX_CD8<64, CD8VT1>; 792 793multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr, 794 X86MemOperand x86memop, PatFrag ld_frag, 795 RegisterClass KRC> { 796 let mayLoad = 1 in { 797 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src), 798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 799 []>, EVEX; 800 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask, 801 x86memop:$src), 802 !strconcat(OpcodeStr, 803 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 804 []>, EVEX, EVEX_KZ; 805 } 806} 807 808defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4", 809 i128mem, loadv2i64, VK16WM>, 810 EVEX_V512, EVEX_CD8<32, CD8VT4>; 811defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4", 812 i256mem, loadv4i64, VK16WM>, VEX_W, 813 EVEX_V512, EVEX_CD8<64, CD8VT4>; 814 815def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))), 816 (VPBROADCASTDZrr VR128X:$src)>; 817def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))), 818 (VPBROADCASTQZrr VR128X:$src)>; 819 820def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))), 821 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>; 822def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))), 823 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>; 824 825def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))), 826 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>; 827def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))), 828 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>; 829 830def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))), 831 (VBROADCASTSSZr VR128X:$src)>; 832def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))), 833 (VBROADCASTSDZr VR128X:$src)>; 834 835// Provide fallback in case the load node that is used in the patterns above 836// is used by additional users, which prevents the pattern selection. 837def : Pat<(v16f32 (X86VBroadcast FR32X:$src)), 838 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>; 839def : Pat<(v8f64 (X86VBroadcast FR64X:$src)), 840 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>; 841 842 843let Predicates = [HasAVX512] in { 844def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))), 845 (EXTRACT_SUBREG 846 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM), 847 addr:$src)), sub_ymm)>; 848} 849//===----------------------------------------------------------------------===// 850// AVX-512 BROADCAST MASK TO VECTOR REGISTER 851//--- 852 853multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr, 854 RegisterClass KRC> { 855let Predicates = [HasCDI] in 856def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src), 857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 858 []>, EVEX, EVEX_V512; 859 860let Predicates = [HasCDI, HasVLX] in { 861def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src), 862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 863 []>, EVEX, EVEX_V128; 864def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src), 865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 866 []>, EVEX, EVEX_V256; 867} 868} 869 870let Predicates = [HasCDI] in { 871defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", 872 VK16>; 873defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", 874 VK8>, VEX_W; 875} 876 877//===----------------------------------------------------------------------===// 878// AVX-512 - VPERM 879// 880// -- immediate form -- 881multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode, 882 X86VectorVTInfo _> { 883 let ExeDomain = _.ExeDomain in { 884 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst), 885 (ins _.RC:$src1, i8imm:$src2), 886 !strconcat(OpcodeStr, 887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 888 [(set _.RC:$dst, 889 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>, 890 EVEX; 891 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst), 892 (ins _.MemOp:$src1, i8imm:$src2), 893 !strconcat(OpcodeStr, 894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 895 [(set _.RC:$dst, 896 (_.VT (OpNode (_.MemOpFrag addr:$src1), 897 (i8 imm:$src2))))]>, 898 EVEX, EVEX_CD8<_.EltSize, CD8VF>; 899} 900} 901 902multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _, 903 X86VectorVTInfo Ctrl> : 904 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> { 905 let ExeDomain = _.ExeDomain in { 906 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst), 907 (ins _.RC:$src1, _.RC:$src2), 908 !strconcat("vpermil" # _.Suffix, 909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 910 [(set _.RC:$dst, 911 (_.VT (X86VPermilpv _.RC:$src1, 912 (Ctrl.VT Ctrl.RC:$src2))))]>, 913 EVEX_4V; 914 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst), 915 (ins _.RC:$src1, Ctrl.MemOp:$src2), 916 !strconcat("vpermil" # _.Suffix, 917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 918 [(set _.RC:$dst, 919 (_.VT (X86VPermilpv _.RC:$src1, 920 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>, 921 EVEX_4V; 922 } 923} 924 925defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>, 926 EVEX_V512, VEX_W; 927defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>, 928 EVEX_V512, VEX_W; 929 930defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>, 931 EVEX_V512; 932defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>, 933 EVEX_V512, VEX_W; 934 935def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))), 936 (VPERMILPSZri VR512:$src1, imm:$imm)>; 937def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))), 938 (VPERMILPDZri VR512:$src1, imm:$imm)>; 939 940// -- VPERM - register form -- 941multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC, 942 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> { 943 944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 945 (ins RC:$src1, RC:$src2), 946 !strconcat(OpcodeStr, 947 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 948 [(set RC:$dst, 949 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V; 950 951 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 952 (ins RC:$src1, x86memop:$src2), 953 !strconcat(OpcodeStr, 954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 955 [(set RC:$dst, 956 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>, 957 EVEX_4V; 958} 959 960defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem, 961 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 962defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem, 963 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 964let ExeDomain = SSEPackedSingle in 965defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem, 966 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 967let ExeDomain = SSEPackedDouble in 968defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem, 969 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 970 971// -- VPERM2I - 3 source operands form -- 972multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC, 973 PatFrag mem_frag, X86MemOperand x86memop, 974 SDNode OpNode, ValueType OpVT, RegisterClass KRC> { 975let Constraints = "$src1 = $dst" in { 976 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 977 (ins RC:$src1, RC:$src2, RC:$src3), 978 !strconcat(OpcodeStr, 979 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 980 [(set RC:$dst, 981 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, 982 EVEX_4V; 983 984 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 985 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3), 986 !strconcat(OpcodeStr, 987 "\t{$src3, $src2, $dst {${mask}}|" 988 "$dst {${mask}}, $src2, $src3}"), 989 [(set RC:$dst, (OpVT (vselect KRC:$mask, 990 (OpNode RC:$src1, RC:$src2, 991 RC:$src3), 992 RC:$src1)))]>, 993 EVEX_4V, EVEX_K; 994 995 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<> 996 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 997 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3), 998 !strconcat(OpcodeStr, 999 "\t{$src3, $src2, $dst {${mask}} {z} |", 1000 "$dst {${mask}} {z}, $src2, $src3}"), 1001 [(set RC:$dst, (OpVT (vselect KRC:$mask, 1002 (OpNode RC:$src1, RC:$src2, 1003 RC:$src3), 1004 (OpVT (bitconvert 1005 (v16i32 immAllZerosV))))))]>, 1006 EVEX_4V, EVEX_KZ; 1007 1008 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 1009 (ins RC:$src1, RC:$src2, x86memop:$src3), 1010 !strconcat(OpcodeStr, 1011 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 1012 [(set RC:$dst, 1013 (OpVT (OpNode RC:$src1, RC:$src2, 1014 (mem_frag addr:$src3))))]>, EVEX_4V; 1015 1016 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 1017 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3), 1018 !strconcat(OpcodeStr, 1019 "\t{$src3, $src2, $dst {${mask}}|" 1020 "$dst {${mask}}, $src2, $src3}"), 1021 [(set RC:$dst, 1022 (OpVT (vselect KRC:$mask, 1023 (OpNode RC:$src1, RC:$src2, 1024 (mem_frag addr:$src3)), 1025 RC:$src1)))]>, 1026 EVEX_4V, EVEX_K; 1027 1028 let AddedComplexity = 10 in // Prefer over the rrkz variant 1029 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 1030 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3), 1031 !strconcat(OpcodeStr, 1032 "\t{$src3, $src2, $dst {${mask}} {z}|" 1033 "$dst {${mask}} {z}, $src2, $src3}"), 1034 [(set RC:$dst, 1035 (OpVT (vselect KRC:$mask, 1036 (OpNode RC:$src1, RC:$src2, 1037 (mem_frag addr:$src3)), 1038 (OpVT (bitconvert 1039 (v16i32 immAllZerosV))))))]>, 1040 EVEX_4V, EVEX_KZ; 1041 } 1042} 1043defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, 1044 i512mem, X86VPermiv3, v16i32, VK16WM>, 1045 EVEX_V512, EVEX_CD8<32, CD8VF>; 1046defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, 1047 i512mem, X86VPermiv3, v8i64, VK8WM>, 1048 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1049defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, 1050 i512mem, X86VPermiv3, v16f32, VK16WM>, 1051 EVEX_V512, EVEX_CD8<32, CD8VF>; 1052defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, 1053 i512mem, X86VPermiv3, v8f64, VK8WM>, 1054 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1055 1056multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC, 1057 PatFrag mem_frag, X86MemOperand x86memop, 1058 SDNode OpNode, ValueType OpVT, RegisterClass KRC, 1059 ValueType MaskVT, RegisterClass MRC> : 1060 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode, 1061 OpVT, KRC> { 1062 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512") 1063 VR512:$idx, VR512:$src1, VR512:$src2, -1)), 1064 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>; 1065 1066 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512") 1067 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)), 1068 (!cast<Instruction>(NAME#rrk) VR512:$src1, 1069 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>; 1070} 1071 1072defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem, 1073 X86VPermv3, v16i32, VK16WM, v16i1, GR16>, 1074 EVEX_V512, EVEX_CD8<32, CD8VF>; 1075defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem, 1076 X86VPermv3, v8i64, VK8WM, v8i1, GR8>, 1077 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1078defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem, 1079 X86VPermv3, v16f32, VK16WM, v16i1, GR16>, 1080 EVEX_V512, EVEX_CD8<32, CD8VF>; 1081defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem, 1082 X86VPermv3, v8f64, VK8WM, v8i1, GR8>, 1083 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1084 1085//===----------------------------------------------------------------------===// 1086// AVX-512 - BLEND using mask 1087// 1088multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> { 1089 let ExeDomain = _.ExeDomain in { 1090 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst), 1091 (ins _.RC:$src1, _.RC:$src2), 1092 !strconcat(OpcodeStr, 1093 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"), 1094 []>, EVEX_4V; 1095 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst), 1096 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), 1097 !strconcat(OpcodeStr, 1098 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"), 1099 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1), 1100 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K; 1101 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst), 1102 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), 1103 !strconcat(OpcodeStr, 1104 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"), 1105 []>, EVEX_4V, EVEX_KZ; 1106 let mayLoad = 1 in { 1107 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst), 1108 (ins _.RC:$src1, _.MemOp:$src2), 1109 !strconcat(OpcodeStr, 1110 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"), 1111 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>; 1112 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst), 1113 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2), 1114 !strconcat(OpcodeStr, 1115 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"), 1116 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1), 1117 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>, 1118 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>; 1119 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst), 1120 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2), 1121 !strconcat(OpcodeStr, 1122 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"), 1123 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>; 1124 } 1125 } 1126} 1127multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> { 1128 1129 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst), 1130 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2), 1131 !strconcat(OpcodeStr, 1132 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|", 1133 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"), 1134 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1), 1135 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>, 1136 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>; 1137 1138 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst), 1139 (ins _.RC:$src1, _.ScalarMemOp:$src2), 1140 !strconcat(OpcodeStr, 1141 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|", 1142 "$dst, $src1, ${src2}", _.BroadcastStr, "}"), 1143 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>; 1144 1145} 1146 1147multiclass blendmask_dq <bits<8> opc, string OpcodeStr, 1148 AVX512VLVectorVTInfo VTInfo> { 1149 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, 1150 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512; 1151 1152 let Predicates = [HasVLX] in { 1153 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>, 1154 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256; 1155 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>, 1156 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128; 1157 } 1158} 1159 1160multiclass blendmask_bw <bits<8> opc, string OpcodeStr, 1161 AVX512VLVectorVTInfo VTInfo> { 1162 let Predicates = [HasBWI] in 1163 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512; 1164 1165 let Predicates = [HasBWI, HasVLX] in { 1166 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256; 1167 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128; 1168 } 1169} 1170 1171 1172defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>; 1173defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W; 1174defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>; 1175defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W; 1176defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>; 1177defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W; 1178 1179 1180let Predicates = [HasAVX512] in { 1181def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1), 1182 (v8f32 VR256X:$src2))), 1183 (EXTRACT_SUBREG 1184 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM), 1185 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 1186 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>; 1187 1188def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1), 1189 (v8i32 VR256X:$src2))), 1190 (EXTRACT_SUBREG 1191 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM), 1192 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 1193 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>; 1194} 1195//===----------------------------------------------------------------------===// 1196// Compare Instructions 1197//===----------------------------------------------------------------------===// 1198 1199// avx512_cmp_scalar - AVX512 CMPSS and CMPSD 1200multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop, 1201 Operand CC, SDNode OpNode, ValueType VT, 1202 PatFrag ld_frag, string asm, string asm_alt> { 1203 def rr : AVX512Ii8<0xC2, MRMSrcReg, 1204 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, 1205 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))], 1206 IIC_SSE_ALU_F32S_RR>, EVEX_4V; 1207 def rm : AVX512Ii8<0xC2, MRMSrcMem, 1208 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, 1209 [(set VK1:$dst, (OpNode (VT RC:$src1), 1210 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V; 1211 let isAsmParserOnly = 1, hasSideEffects = 0 in { 1212 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg, 1213 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), 1214 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V; 1215 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem, 1216 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), 1217 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V; 1218 } 1219} 1220 1221let Predicates = [HasAVX512] in { 1222defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32, 1223 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", 1224 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 1225 XS; 1226defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64, 1227 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 1228 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 1229 XD, VEX_W; 1230} 1231 1232multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode, 1233 X86VectorVTInfo _> { 1234 def rr : AVX512BI<opc, MRMSrcReg, 1235 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2), 1236 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1237 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))], 1238 IIC_SSE_ALU_F32P_RR>, EVEX_4V; 1239 let mayLoad = 1 in 1240 def rm : AVX512BI<opc, MRMSrcMem, 1241 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2), 1242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1243 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), 1244 (_.VT (bitconvert (_.LdFrag addr:$src2)))))], 1245 IIC_SSE_ALU_F32P_RM>, EVEX_4V; 1246 def rrk : AVX512BI<opc, MRMSrcReg, 1247 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), 1248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|", 1249 "$dst {${mask}}, $src1, $src2}"), 1250 [(set _.KRC:$dst, (and _.KRCWM:$mask, 1251 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))], 1252 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K; 1253 let mayLoad = 1 in 1254 def rmk : AVX512BI<opc, MRMSrcMem, 1255 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2), 1256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|", 1257 "$dst {${mask}}, $src1, $src2}"), 1258 [(set _.KRC:$dst, (and _.KRCWM:$mask, 1259 (OpNode (_.VT _.RC:$src1), 1260 (_.VT (bitconvert 1261 (_.LdFrag addr:$src2))))))], 1262 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K; 1263} 1264 1265multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode, 1266 X86VectorVTInfo _> : 1267 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> { 1268 let mayLoad = 1 in { 1269 def rmb : AVX512BI<opc, MRMSrcMem, 1270 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2), 1271 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst", 1272 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"), 1273 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), 1274 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))], 1275 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B; 1276 def rmbk : AVX512BI<opc, MRMSrcMem, 1277 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, 1278 _.ScalarMemOp:$src2), 1279 !strconcat(OpcodeStr, 1280 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|", 1281 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"), 1282 [(set _.KRC:$dst, (and _.KRCWM:$mask, 1283 (OpNode (_.VT _.RC:$src1), 1284 (X86VBroadcast 1285 (_.ScalarLdFrag addr:$src2)))))], 1286 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B; 1287 } 1288} 1289 1290multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode, 1291 AVX512VLVectorVTInfo VTInfo, Predicate prd> { 1292 let Predicates = [prd] in 1293 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>, 1294 EVEX_V512; 1295 1296 let Predicates = [prd, HasVLX] in { 1297 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>, 1298 EVEX_V256; 1299 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>, 1300 EVEX_V128; 1301 } 1302} 1303 1304multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr, 1305 SDNode OpNode, AVX512VLVectorVTInfo VTInfo, 1306 Predicate prd> { 1307 let Predicates = [prd] in 1308 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>, 1309 EVEX_V512; 1310 1311 let Predicates = [prd, HasVLX] in { 1312 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>, 1313 EVEX_V256; 1314 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>, 1315 EVEX_V128; 1316 } 1317} 1318 1319defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm, 1320 avx512vl_i8_info, HasBWI>, 1321 EVEX_CD8<8, CD8VF>; 1322 1323defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm, 1324 avx512vl_i16_info, HasBWI>, 1325 EVEX_CD8<16, CD8VF>; 1326 1327defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm, 1328 avx512vl_i32_info, HasAVX512>, 1329 EVEX_CD8<32, CD8VF>; 1330 1331defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm, 1332 avx512vl_i64_info, HasAVX512>, 1333 T8PD, VEX_W, EVEX_CD8<64, CD8VF>; 1334 1335defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm, 1336 avx512vl_i8_info, HasBWI>, 1337 EVEX_CD8<8, CD8VF>; 1338 1339defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm, 1340 avx512vl_i16_info, HasBWI>, 1341 EVEX_CD8<16, CD8VF>; 1342 1343defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm, 1344 avx512vl_i32_info, HasAVX512>, 1345 EVEX_CD8<32, CD8VF>; 1346 1347defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm, 1348 avx512vl_i64_info, HasAVX512>, 1349 T8PD, VEX_W, EVEX_CD8<64, CD8VF>; 1350 1351def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), 1352 (COPY_TO_REGCLASS (VPCMPGTDZrr 1353 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 1354 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>; 1355 1356def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), 1357 (COPY_TO_REGCLASS (VPCMPEQDZrr 1358 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 1359 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>; 1360 1361multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode, 1362 X86VectorVTInfo _> { 1363 def rri : AVX512AIi8<opc, MRMSrcReg, 1364 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), 1365 !strconcat("vpcmp${cc}", Suffix, 1366 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1367 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), 1368 imm:$cc))], 1369 IIC_SSE_ALU_F32P_RR>, EVEX_4V; 1370 let mayLoad = 1 in 1371 def rmi : AVX512AIi8<opc, MRMSrcMem, 1372 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc), 1373 !strconcat("vpcmp${cc}", Suffix, 1374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1375 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), 1376 (_.VT (bitconvert (_.LdFrag addr:$src2))), 1377 imm:$cc))], 1378 IIC_SSE_ALU_F32P_RM>, EVEX_4V; 1379 def rrik : AVX512AIi8<opc, MRMSrcReg, 1380 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2, 1381 AVXCC:$cc), 1382 !strconcat("vpcmp${cc}", Suffix, 1383 "\t{$src2, $src1, $dst {${mask}}|", 1384 "$dst {${mask}}, $src1, $src2}"), 1385 [(set _.KRC:$dst, (and _.KRCWM:$mask, 1386 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), 1387 imm:$cc)))], 1388 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K; 1389 let mayLoad = 1 in 1390 def rmik : AVX512AIi8<opc, MRMSrcMem, 1391 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2, 1392 AVXCC:$cc), 1393 !strconcat("vpcmp${cc}", Suffix, 1394 "\t{$src2, $src1, $dst {${mask}}|", 1395 "$dst {${mask}}, $src1, $src2}"), 1396 [(set _.KRC:$dst, (and _.KRCWM:$mask, 1397 (OpNode (_.VT _.RC:$src1), 1398 (_.VT (bitconvert (_.LdFrag addr:$src2))), 1399 imm:$cc)))], 1400 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K; 1401 1402 // Accept explicit immediate argument form instead of comparison code. 1403 let isAsmParserOnly = 1, hasSideEffects = 0 in { 1404 def rri_alt : AVX512AIi8<opc, MRMSrcReg, 1405 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc), 1406 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|", 1407 "$dst, $src1, $src2, $cc}"), 1408 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V; 1409 def rmi_alt : AVX512AIi8<opc, MRMSrcMem, 1410 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc), 1411 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|", 1412 "$dst, $src1, $src2, $cc}"), 1413 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V; 1414 def rrik_alt : AVX512AIi8<opc, MRMSrcReg, 1415 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2, 1416 i8imm:$cc), 1417 !strconcat("vpcmp", Suffix, 1418 "\t{$cc, $src2, $src1, $dst {${mask}}|", 1419 "$dst {${mask}}, $src1, $src2, $cc}"), 1420 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K; 1421 def rmik_alt : AVX512AIi8<opc, MRMSrcMem, 1422 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2, 1423 i8imm:$cc), 1424 !strconcat("vpcmp", Suffix, 1425 "\t{$cc, $src2, $src1, $dst {${mask}}|", 1426 "$dst {${mask}}, $src1, $src2, $cc}"), 1427 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K; 1428 } 1429} 1430 1431multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode, 1432 X86VectorVTInfo _> : 1433 avx512_icmp_cc<opc, Suffix, OpNode, _> { 1434 let mayLoad = 1 in { 1435 def rmib : AVX512AIi8<opc, MRMSrcMem, 1436 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2, 1437 AVXCC:$cc), 1438 !strconcat("vpcmp${cc}", Suffix, 1439 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|", 1440 "$dst, $src1, ${src2}", _.BroadcastStr, "}"), 1441 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), 1442 (X86VBroadcast (_.ScalarLdFrag addr:$src2)), 1443 imm:$cc))], 1444 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B; 1445 def rmibk : AVX512AIi8<opc, MRMSrcMem, 1446 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, 1447 _.ScalarMemOp:$src2, AVXCC:$cc), 1448 !strconcat("vpcmp${cc}", Suffix, 1449 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|", 1450 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"), 1451 [(set _.KRC:$dst, (and _.KRCWM:$mask, 1452 (OpNode (_.VT _.RC:$src1), 1453 (X86VBroadcast (_.ScalarLdFrag addr:$src2)), 1454 imm:$cc)))], 1455 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B; 1456 } 1457 1458 // Accept explicit immediate argument form instead of comparison code. 1459 let isAsmParserOnly = 1, hasSideEffects = 0 in { 1460 def rmib_alt : AVX512AIi8<opc, MRMSrcMem, 1461 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2, 1462 i8imm:$cc), 1463 !strconcat("vpcmp", Suffix, 1464 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|", 1465 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"), 1466 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B; 1467 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem, 1468 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, 1469 _.ScalarMemOp:$src2, i8imm:$cc), 1470 !strconcat("vpcmp", Suffix, 1471 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|", 1472 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"), 1473 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B; 1474 } 1475} 1476 1477multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode, 1478 AVX512VLVectorVTInfo VTInfo, Predicate prd> { 1479 let Predicates = [prd] in 1480 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512; 1481 1482 let Predicates = [prd, HasVLX] in { 1483 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256; 1484 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128; 1485 } 1486} 1487 1488multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode, 1489 AVX512VLVectorVTInfo VTInfo, Predicate prd> { 1490 let Predicates = [prd] in 1491 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>, 1492 EVEX_V512; 1493 1494 let Predicates = [prd, HasVLX] in { 1495 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>, 1496 EVEX_V256; 1497 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>, 1498 EVEX_V128; 1499 } 1500} 1501 1502defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info, 1503 HasBWI>, EVEX_CD8<8, CD8VF>; 1504defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info, 1505 HasBWI>, EVEX_CD8<8, CD8VF>; 1506 1507defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info, 1508 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>; 1509defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info, 1510 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>; 1511 1512defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info, 1513 HasAVX512>, EVEX_CD8<32, CD8VF>; 1514defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info, 1515 HasAVX512>, EVEX_CD8<32, CD8VF>; 1516 1517defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info, 1518 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; 1519defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info, 1520 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; 1521 1522// avx512_cmp_packed - compare packed instructions 1523multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC, 1524 X86MemOperand x86memop, ValueType vt, 1525 string suffix, Domain d> { 1526 def rri : AVX512PIi8<0xC2, MRMSrcReg, 1527 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc), 1528 !strconcat("vcmp${cc}", suffix, 1529 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1530 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>; 1531 def rrib: AVX512PIi8<0xC2, MRMSrcReg, 1532 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc), 1533 !strconcat("vcmp${cc}", suffix, 1534 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"), 1535 [], d>, EVEX_B; 1536 def rmi : AVX512PIi8<0xC2, MRMSrcMem, 1537 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc), 1538 !strconcat("vcmp${cc}", suffix, 1539 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"), 1540 [(set KRC:$dst, 1541 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>; 1542 1543 // Accept explicit immediate argument form instead of comparison code. 1544 let isAsmParserOnly = 1, hasSideEffects = 0 in { 1545 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg, 1546 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), 1547 !strconcat("vcmp", suffix, 1548 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>; 1549 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem, 1550 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), 1551 !strconcat("vcmp", suffix, 1552 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>; 1553 } 1554} 1555 1556defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32, 1557 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512, 1558 EVEX_CD8<32, CD8VF>; 1559defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64, 1560 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512, 1561 EVEX_CD8<64, CD8VF>; 1562 1563def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)), 1564 (COPY_TO_REGCLASS (VCMPPSZrri 1565 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 1566 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 1567 imm:$cc), VK8)>; 1568def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)), 1569 (COPY_TO_REGCLASS (VPCMPDZrri 1570 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 1571 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 1572 imm:$cc), VK8)>; 1573def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)), 1574 (COPY_TO_REGCLASS (VPCMPUDZrri 1575 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 1576 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 1577 imm:$cc), VK8)>; 1578 1579def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1), 1580 (v16f32 VR512:$src2), i32immZExt5:$cc, (i16 -1), 1581 FROUND_NO_EXC)), 1582 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2, 1583 (I8Imm imm:$cc)), GR16)>; 1584 1585def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1), 1586 (v8f64 VR512:$src2), i32immZExt5:$cc, (i8 -1), 1587 FROUND_NO_EXC)), 1588 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2, 1589 (I8Imm imm:$cc)), GR8)>; 1590 1591def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1), 1592 (v16f32 VR512:$src2), i32immZExt5:$cc, (i16 -1), 1593 FROUND_CURRENT)), 1594 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2, 1595 (I8Imm imm:$cc)), GR16)>; 1596 1597def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1), 1598 (v8f64 VR512:$src2), i32immZExt5:$cc, (i8 -1), 1599 FROUND_CURRENT)), 1600 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2, 1601 (I8Imm imm:$cc)), GR8)>; 1602 1603// Mask register copy, including 1604// - copy between mask registers 1605// - load/store mask registers 1606// - copy from GPR to mask register and vice versa 1607// 1608multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk, 1609 string OpcodeStr, RegisterClass KRC, 1610 ValueType vvt, ValueType ivt, X86MemOperand x86memop> { 1611 let hasSideEffects = 0 in { 1612 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src), 1613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>; 1614 let mayLoad = 1 in 1615 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src), 1616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 1617 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>; 1618 let mayStore = 1 in 1619 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src), 1620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>; 1621 } 1622} 1623 1624multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk, 1625 string OpcodeStr, 1626 RegisterClass KRC, RegisterClass GRC> { 1627 let hasSideEffects = 0 in { 1628 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src), 1629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>; 1630 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src), 1631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>; 1632 } 1633} 1634 1635let Predicates = [HasDQI] in 1636 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8, 1637 i8mem>, 1638 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>, 1639 VEX, PD; 1640 1641let Predicates = [HasAVX512] in 1642 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16, 1643 i16mem>, 1644 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>, 1645 VEX, PS; 1646 1647let Predicates = [HasBWI] in { 1648 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32, 1649 i32mem>, VEX, PD, VEX_W; 1650 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>, 1651 VEX, XD; 1652} 1653 1654let Predicates = [HasBWI] in { 1655 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64, 1656 i64mem>, VEX, PS, VEX_W; 1657 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>, 1658 VEX, XD, VEX_W; 1659} 1660 1661// GR from/to mask register 1662let Predicates = [HasDQI] in { 1663 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))), 1664 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>; 1665 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), 1666 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>; 1667} 1668let Predicates = [HasAVX512] in { 1669 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))), 1670 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>; 1671 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))), 1672 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>; 1673} 1674let Predicates = [HasBWI] in { 1675 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>; 1676 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>; 1677} 1678let Predicates = [HasBWI] in { 1679 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>; 1680 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>; 1681} 1682 1683// Load/store kreg 1684let Predicates = [HasDQI] in { 1685 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst), 1686 (KMOVBmk addr:$dst, VK8:$src)>; 1687} 1688let Predicates = [HasAVX512] in { 1689 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst), 1690 (KMOVWmk addr:$dst, VK16:$src)>; 1691 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst), 1692 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>; 1693 def : Pat<(i1 (load addr:$src)), 1694 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>; 1695 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))), 1696 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>; 1697} 1698let Predicates = [HasBWI] in { 1699 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst), 1700 (KMOVDmk addr:$dst, VK32:$src)>; 1701} 1702let Predicates = [HasBWI] in { 1703 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst), 1704 (KMOVQmk addr:$dst, VK64:$src)>; 1705} 1706 1707let Predicates = [HasAVX512] in { 1708 def : Pat<(i1 (trunc (i64 GR64:$src))), 1709 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit), 1710 (i32 1))), VK1)>; 1711 1712 def : Pat<(i1 (trunc (i32 GR32:$src))), 1713 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>; 1714 1715 def : Pat<(i1 (trunc (i8 GR8:$src))), 1716 (COPY_TO_REGCLASS 1717 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))), 1718 VK1)>; 1719 def : Pat<(i1 (trunc (i16 GR16:$src))), 1720 (COPY_TO_REGCLASS 1721 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))), 1722 VK1)>; 1723 1724 def : Pat<(i32 (zext VK1:$src)), 1725 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>; 1726 def : Pat<(i8 (zext VK1:$src)), 1727 (EXTRACT_SUBREG 1728 (AND32ri (KMOVWrk 1729 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>; 1730 def : Pat<(i64 (zext VK1:$src)), 1731 (AND64ri8 (SUBREG_TO_REG (i64 0), 1732 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>; 1733 def : Pat<(i16 (zext VK1:$src)), 1734 (EXTRACT_SUBREG 1735 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), 1736 sub_16bit)>; 1737 def : Pat<(v16i1 (scalar_to_vector VK1:$src)), 1738 (COPY_TO_REGCLASS VK1:$src, VK16)>; 1739 def : Pat<(v8i1 (scalar_to_vector VK1:$src)), 1740 (COPY_TO_REGCLASS VK1:$src, VK8)>; 1741} 1742let Predicates = [HasBWI] in { 1743 def : Pat<(v32i1 (scalar_to_vector VK1:$src)), 1744 (COPY_TO_REGCLASS VK1:$src, VK32)>; 1745 def : Pat<(v64i1 (scalar_to_vector VK1:$src)), 1746 (COPY_TO_REGCLASS VK1:$src, VK64)>; 1747} 1748 1749 1750// With AVX-512 only, 8-bit mask is promoted to 16-bit mask. 1751let Predicates = [HasAVX512] in { 1752 // GR from/to 8-bit mask without native support 1753 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))), 1754 (COPY_TO_REGCLASS 1755 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), 1756 VK8)>; 1757 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), 1758 (EXTRACT_SUBREG 1759 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)), 1760 sub_8bit)>; 1761 1762 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))), 1763 (COPY_TO_REGCLASS VK16:$src, VK1)>; 1764 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))), 1765 (COPY_TO_REGCLASS VK8:$src, VK1)>; 1766} 1767let Predicates = [HasBWI] in { 1768 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))), 1769 (COPY_TO_REGCLASS VK32:$src, VK1)>; 1770 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))), 1771 (COPY_TO_REGCLASS VK64:$src, VK1)>; 1772} 1773 1774// Mask unary operation 1775// - KNOT 1776multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr, 1777 RegisterClass KRC, SDPatternOperator OpNode, 1778 Predicate prd> { 1779 let Predicates = [prd] in 1780 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src), 1781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 1782 [(set KRC:$dst, (OpNode KRC:$src))]>; 1783} 1784 1785multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr, 1786 SDPatternOperator OpNode> { 1787 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode, 1788 HasDQI>, VEX, PD; 1789 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode, 1790 HasAVX512>, VEX, PS; 1791 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode, 1792 HasBWI>, VEX, PD, VEX_W; 1793 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode, 1794 HasBWI>, VEX, PS, VEX_W; 1795} 1796 1797defm KNOT : avx512_mask_unop_all<0x44, "knot", not>; 1798 1799multiclass avx512_mask_unop_int<string IntName, string InstName> { 1800 let Predicates = [HasAVX512] in 1801 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w") 1802 (i16 GR16:$src)), 1803 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr") 1804 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>; 1805} 1806defm : avx512_mask_unop_int<"knot", "KNOT">; 1807 1808let Predicates = [HasDQI] in 1809def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>; 1810let Predicates = [HasAVX512] in 1811def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>; 1812let Predicates = [HasBWI] in 1813def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>; 1814let Predicates = [HasBWI] in 1815def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>; 1816 1817// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit 1818let Predicates = [HasAVX512] in { 1819def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), 1820 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>; 1821 1822def : Pat<(not VK8:$src), 1823 (COPY_TO_REGCLASS 1824 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>; 1825} 1826 1827// Mask binary operation 1828// - KAND, KANDN, KOR, KXNOR, KXOR 1829multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr, 1830 RegisterClass KRC, SDPatternOperator OpNode, 1831 Predicate prd> { 1832 let Predicates = [prd] in 1833 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2), 1834 !strconcat(OpcodeStr, 1835 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1836 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>; 1837} 1838 1839multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr, 1840 SDPatternOperator OpNode> { 1841 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode, 1842 HasDQI>, VEX_4V, VEX_L, PD; 1843 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode, 1844 HasAVX512>, VEX_4V, VEX_L, PS; 1845 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode, 1846 HasBWI>, VEX_4V, VEX_L, VEX_W, PD; 1847 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode, 1848 HasBWI>, VEX_4V, VEX_L, VEX_W, PS; 1849} 1850 1851def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>; 1852def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>; 1853 1854let isCommutable = 1 in { 1855 defm KAND : avx512_mask_binop_all<0x41, "kand", and>; 1856 defm KOR : avx512_mask_binop_all<0x45, "kor", or>; 1857 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>; 1858 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>; 1859} 1860let isCommutable = 0 in 1861 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>; 1862 1863def : Pat<(xor VK1:$src1, VK1:$src2), 1864 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1865 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; 1866 1867def : Pat<(or VK1:$src1, VK1:$src2), 1868 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1869 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; 1870 1871def : Pat<(and VK1:$src1, VK1:$src2), 1872 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1873 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; 1874 1875multiclass avx512_mask_binop_int<string IntName, string InstName> { 1876 let Predicates = [HasAVX512] in 1877 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w") 1878 (i16 GR16:$src1), (i16 GR16:$src2)), 1879 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr") 1880 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)), 1881 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>; 1882} 1883 1884defm : avx512_mask_binop_int<"kand", "KAND">; 1885defm : avx512_mask_binop_int<"kandn", "KANDN">; 1886defm : avx512_mask_binop_int<"kor", "KOR">; 1887defm : avx512_mask_binop_int<"kxnor", "KXNOR">; 1888defm : avx512_mask_binop_int<"kxor", "KXOR">; 1889 1890// With AVX-512, 8-bit mask is promoted to 16-bit mask. 1891multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> { 1892 let Predicates = [HasAVX512] in 1893 def : Pat<(OpNode VK8:$src1, VK8:$src2), 1894 (COPY_TO_REGCLASS 1895 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16), 1896 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>; 1897} 1898 1899defm : avx512_binop_pat<and, KANDWrr>; 1900defm : avx512_binop_pat<andn, KANDNWrr>; 1901defm : avx512_binop_pat<or, KORWrr>; 1902defm : avx512_binop_pat<xnor, KXNORWrr>; 1903defm : avx512_binop_pat<xor, KXORWrr>; 1904 1905// Mask unpacking 1906multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr, 1907 RegisterClass KRC> { 1908 let Predicates = [HasAVX512] in 1909 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2), 1910 !strconcat(OpcodeStr, 1911 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>; 1912} 1913 1914multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> { 1915 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>, 1916 VEX_4V, VEX_L, PD; 1917} 1918 1919defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">; 1920def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))), 1921 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16), 1922 (COPY_TO_REGCLASS VK8:$src1, VK16))>; 1923 1924 1925multiclass avx512_mask_unpck_int<string IntName, string InstName> { 1926 let Predicates = [HasAVX512] in 1927 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw") 1928 (i16 GR16:$src1), (i16 GR16:$src2)), 1929 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr") 1930 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)), 1931 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>; 1932} 1933defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">; 1934 1935// Mask bit testing 1936multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC, 1937 SDNode OpNode> { 1938 let Predicates = [HasAVX512], Defs = [EFLAGS] in 1939 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2), 1940 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"), 1941 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>; 1942} 1943 1944multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> { 1945 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>, 1946 VEX, PS; 1947} 1948 1949defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>; 1950 1951def : Pat<(X86cmp VK1:$src1, (i1 0)), 1952 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1953 (COPY_TO_REGCLASS VK1:$src1, VK16))>; 1954 1955// Mask shift 1956multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC, 1957 SDNode OpNode> { 1958 let Predicates = [HasAVX512] in 1959 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm), 1960 !strconcat(OpcodeStr, 1961 "\t{$imm, $src, $dst|$dst, $src, $imm}"), 1962 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>; 1963} 1964 1965multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr, 1966 SDNode OpNode> { 1967 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>, 1968 VEX, TAPD, VEX_W; 1969} 1970 1971defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>; 1972defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>; 1973 1974// Mask setting all 0s or 1s 1975multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> { 1976 let Predicates = [HasAVX512] in 1977 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in 1978 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "", 1979 [(set KRC:$dst, (VT Val))]>; 1980} 1981 1982multiclass avx512_mask_setop_w<PatFrag Val> { 1983 defm B : avx512_mask_setop<VK8, v8i1, Val>; 1984 defm W : avx512_mask_setop<VK16, v16i1, Val>; 1985} 1986 1987defm KSET0 : avx512_mask_setop_w<immAllZerosV>; 1988defm KSET1 : avx512_mask_setop_w<immAllOnesV>; 1989 1990// With AVX-512 only, 8-bit mask is promoted to 16-bit mask. 1991let Predicates = [HasAVX512] in { 1992 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>; 1993 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>; 1994 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>; 1995 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>; 1996 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>; 1997} 1998def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))), 1999 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>; 2000 2001def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))), 2002 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>; 2003 2004def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))), 2005 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>; 2006 2007let Predicates = [HasVLX] in { 2008 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))), 2009 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>; 2010 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))), 2011 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>; 2012 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))), 2013 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>; 2014 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))), 2015 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>; 2016} 2017 2018def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))), 2019 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>; 2020 2021def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))), 2022 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>; 2023//===----------------------------------------------------------------------===// 2024// AVX-512 - Aligned and unaligned load and store 2025// 2026 2027multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag, 2028 RegisterClass KRC, RegisterClass RC, 2029 ValueType vt, ValueType zvt, X86MemOperand memop, 2030 Domain d, bit IsReMaterializable = 1> { 2031let hasSideEffects = 0 in { 2032 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 2033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], 2034 d>, EVEX; 2035 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src), 2036 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|", 2037 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ; 2038 } 2039 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable, 2040 SchedRW = [WriteLoad] in 2041 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src), 2042 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 2043 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))], 2044 d>, EVEX; 2045 2046 let AddedComplexity = 20 in { 2047 let Constraints = "$src0 = $dst", hasSideEffects = 0 in { 2048 let hasSideEffects = 0 in 2049 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), 2050 (ins RC:$src0, KRC:$mask, RC:$src1), 2051 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|", 2052 "${dst} {${mask}}, $src1}"), 2053 [(set RC:$dst, (vt (vselect KRC:$mask, 2054 (vt RC:$src1), 2055 (vt RC:$src0))))], 2056 d>, EVEX, EVEX_K; 2057 let mayLoad = 1, SchedRW = [WriteLoad] in 2058 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), 2059 (ins RC:$src0, KRC:$mask, memop:$src1), 2060 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|", 2061 "${dst} {${mask}}, $src1}"), 2062 [(set RC:$dst, (vt 2063 (vselect KRC:$mask, 2064 (vt (bitconvert (ld_frag addr:$src1))), 2065 (vt RC:$src0))))], 2066 d>, EVEX, EVEX_K; 2067 } 2068 let mayLoad = 1, SchedRW = [WriteLoad] in 2069 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), 2070 (ins KRC:$mask, memop:$src), 2071 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|", 2072 "${dst} {${mask}} {z}, $src}"), 2073 [(set RC:$dst, (vt 2074 (vselect KRC:$mask, 2075 (vt (bitconvert (ld_frag addr:$src))), 2076 (vt (bitconvert (zvt immAllZerosV))))))], 2077 d>, EVEX, EVEX_KZ; 2078 } 2079} 2080 2081multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat, 2082 string elty, string elsz, string vsz512, 2083 string vsz256, string vsz128, Domain d, 2084 Predicate prd, bit IsReMaterializable = 1> { 2085 let Predicates = [prd] in 2086 defm Z : avx512_load<opc, OpcodeStr, 2087 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz), 2088 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512, 2089 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32, 2090 !cast<X86MemOperand>(elty##"512mem"), d, 2091 IsReMaterializable>, EVEX_V512; 2092 2093 let Predicates = [prd, HasVLX] in { 2094 defm Z256 : avx512_load<opc, OpcodeStr, 2095 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"), 2096 "v"##vsz256##elty##elsz, "v4i64")), 2097 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X, 2098 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32, 2099 !cast<X86MemOperand>(elty##"256mem"), d, 2100 IsReMaterializable>, EVEX_V256; 2101 2102 defm Z128 : avx512_load<opc, OpcodeStr, 2103 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"), 2104 "v"##vsz128##elty##elsz, "v2i64")), 2105 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X, 2106 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32, 2107 !cast<X86MemOperand>(elty##"128mem"), d, 2108 IsReMaterializable>, EVEX_V128; 2109 } 2110} 2111 2112 2113multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag, 2114 ValueType OpVT, RegisterClass KRC, RegisterClass RC, 2115 X86MemOperand memop, Domain d> { 2116 let isAsmParserOnly = 1, hasSideEffects = 0 in { 2117 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src), 2118 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>, 2119 EVEX; 2120 let Constraints = "$src1 = $dst" in 2121 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), 2122 (ins RC:$src1, KRC:$mask, RC:$src2), 2123 !strconcat(OpcodeStr, 2124 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>, 2125 EVEX, EVEX_K; 2126 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), 2127 (ins KRC:$mask, RC:$src), 2128 !strconcat(OpcodeStr, 2129 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 2130 [], d>, EVEX, EVEX_KZ; 2131 } 2132 let mayStore = 1 in { 2133 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src), 2134 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 2135 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX; 2136 def mrk : AVX512PI<opc, MRMDestMem, (outs), 2137 (ins memop:$dst, KRC:$mask, RC:$src), 2138 !strconcat(OpcodeStr, 2139 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"), 2140 [], d>, EVEX, EVEX_K; 2141 } 2142} 2143 2144 2145multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat, 2146 string st_suff_512, string st_suff_256, 2147 string st_suff_128, string elty, string elsz, 2148 string vsz512, string vsz256, string vsz128, 2149 Domain d, Predicate prd> { 2150 let Predicates = [prd] in 2151 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512), 2152 !cast<ValueType>("v"##vsz512##elty##elsz), 2153 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512, 2154 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512; 2155 2156 let Predicates = [prd, HasVLX] in { 2157 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256), 2158 !cast<ValueType>("v"##vsz256##elty##elsz), 2159 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X, 2160 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256; 2161 2162 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128), 2163 !cast<ValueType>("v"##vsz128##elty##elsz), 2164 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X, 2165 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128; 2166 } 2167} 2168 2169defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32", 2170 "16", "8", "4", SSEPackedSingle, HasAVX512>, 2171 avx512_store_vl<0x29, "vmovaps", "alignedstore", 2172 "512", "256", "", "f", "32", "16", "8", "4", 2173 SSEPackedSingle, HasAVX512>, 2174 PS, EVEX_CD8<32, CD8VF>; 2175 2176defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64", 2177 "8", "4", "2", SSEPackedDouble, HasAVX512>, 2178 avx512_store_vl<0x29, "vmovapd", "alignedstore", 2179 "512", "256", "", "f", "64", "8", "4", "2", 2180 SSEPackedDouble, HasAVX512>, 2181 PD, VEX_W, EVEX_CD8<64, CD8VF>; 2182 2183defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32", 2184 "16", "8", "4", SSEPackedSingle, HasAVX512>, 2185 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32", 2186 "16", "8", "4", SSEPackedSingle, HasAVX512>, 2187 PS, EVEX_CD8<32, CD8VF>; 2188 2189defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64", 2190 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>, 2191 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64", 2192 "8", "4", "2", SSEPackedDouble, HasAVX512>, 2193 PD, VEX_W, EVEX_CD8<64, CD8VF>; 2194 2195def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr, 2196 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)), 2197 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>; 2198 2199def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr, 2200 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)), 2201 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>; 2202 2203def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src), 2204 GR16:$mask), 2205 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), 2206 VR512:$src)>; 2207def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src), 2208 GR8:$mask), 2209 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), 2210 VR512:$src)>; 2211 2212def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)), 2213 (VMOVUPSZmrk addr:$ptr, 2214 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), 2215 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>; 2216 2217def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)), 2218 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz 2219 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>; 2220 2221def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)), 2222 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>; 2223 2224def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)), 2225 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>; 2226 2227def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)), 2228 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>; 2229 2230def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, 2231 (bc_v16f32 (v16i32 immAllZerosV)))), 2232 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>; 2233 2234def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))), 2235 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>; 2236 2237def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)), 2238 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>; 2239 2240def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, 2241 (bc_v8f64 (v16i32 immAllZerosV)))), 2242 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>; 2243 2244def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))), 2245 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>; 2246 2247def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))), 2248 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk 2249 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm), 2250 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>; 2251 2252defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32", 2253 "16", "8", "4", SSEPackedInt, HasAVX512>, 2254 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore", 2255 "512", "256", "", "i", "32", "16", "8", "4", 2256 SSEPackedInt, HasAVX512>, 2257 PD, EVEX_CD8<32, CD8VF>; 2258 2259defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64", 2260 "8", "4", "2", SSEPackedInt, HasAVX512>, 2261 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore", 2262 "512", "256", "", "i", "64", "8", "4", "2", 2263 SSEPackedInt, HasAVX512>, 2264 PD, VEX_W, EVEX_CD8<64, CD8VF>; 2265 2266defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8", 2267 "64", "32", "16", SSEPackedInt, HasBWI>, 2268 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "", 2269 "i", "8", "64", "32", "16", SSEPackedInt, 2270 HasBWI>, XD, EVEX_CD8<8, CD8VF>; 2271 2272defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16", 2273 "32", "16", "8", SSEPackedInt, HasBWI>, 2274 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "", 2275 "i", "16", "32", "16", "8", SSEPackedInt, 2276 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>; 2277 2278defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32", 2279 "16", "8", "4", SSEPackedInt, HasAVX512>, 2280 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "", 2281 "i", "32", "16", "8", "4", SSEPackedInt, 2282 HasAVX512>, XS, EVEX_CD8<32, CD8VF>; 2283 2284defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64", 2285 "8", "4", "2", SSEPackedInt, HasAVX512>, 2286 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "", 2287 "i", "64", "8", "4", "2", SSEPackedInt, 2288 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>; 2289 2290def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr, 2291 (v16i32 immAllZerosV), GR16:$mask)), 2292 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>; 2293 2294def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr, 2295 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)), 2296 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>; 2297 2298def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src), 2299 GR16:$mask), 2300 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), 2301 VR512:$src)>; 2302def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src), 2303 GR8:$mask), 2304 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), 2305 VR512:$src)>; 2306 2307let AddedComplexity = 20 in { 2308def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src), 2309 (bc_v8i64 (v16i32 immAllZerosV)))), 2310 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>; 2311 2312def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)), 2313 (v8i64 VR512:$src))), 2314 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)), 2315 VK8), VR512:$src)>; 2316 2317def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src), 2318 (v16i32 immAllZerosV))), 2319 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>; 2320 2321def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV), 2322 (v16i32 VR512:$src))), 2323 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>; 2324} 2325 2326def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))), 2327 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>; 2328 2329def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)), 2330 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>; 2331 2332def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))), 2333 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>; 2334 2335def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, 2336 (bc_v8i64 (v16i32 immAllZerosV)))), 2337 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>; 2338 2339def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)), 2340 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>; 2341 2342def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))), 2343 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>; 2344 2345def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)), 2346 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>; 2347 2348def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)), 2349 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>; 2350 2351// SKX replacement 2352def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)), 2353 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>; 2354 2355// KNL replacement 2356def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)), 2357 (VMOVDQU32Zmrk addr:$ptr, 2358 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), 2359 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>; 2360 2361def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)), 2362 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz 2363 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>; 2364 2365 2366// Move Int Doubleword to Packed Double Int 2367// 2368def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src), 2369 "vmovd\t{$src, $dst|$dst, $src}", 2370 [(set VR128X:$dst, 2371 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>, 2372 EVEX, VEX_LIG; 2373def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src), 2374 "vmovd\t{$src, $dst|$dst, $src}", 2375 [(set VR128X:$dst, 2376 (v4i32 (scalar_to_vector (loadi32 addr:$src))))], 2377 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2378def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src), 2379 "vmovq\t{$src, $dst|$dst, $src}", 2380 [(set VR128X:$dst, 2381 (v2i64 (scalar_to_vector GR64:$src)))], 2382 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG; 2383let isCodeGenOnly = 1 in { 2384def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), 2385 "vmovq\t{$src, $dst|$dst, $src}", 2386 [(set FR64:$dst, (bitconvert GR64:$src))], 2387 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>; 2388def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), 2389 "vmovq\t{$src, $dst|$dst, $src}", 2390 [(set GR64:$dst, (bitconvert FR64:$src))], 2391 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>; 2392} 2393def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), 2394 "vmovq\t{$src, $dst|$dst, $src}", 2395 [(store (i64 (bitconvert FR64:$src)), addr:$dst)], 2396 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>, 2397 EVEX_CD8<64, CD8VT1>; 2398 2399// Move Int Doubleword to Single Scalar 2400// 2401let isCodeGenOnly = 1 in { 2402def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src), 2403 "vmovd\t{$src, $dst|$dst, $src}", 2404 [(set FR32X:$dst, (bitconvert GR32:$src))], 2405 IIC_SSE_MOVDQ>, EVEX, VEX_LIG; 2406 2407def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src), 2408 "vmovd\t{$src, $dst|$dst, $src}", 2409 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))], 2410 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2411} 2412 2413// Move doubleword from xmm register to r/m32 2414// 2415def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src), 2416 "vmovd\t{$src, $dst|$dst, $src}", 2417 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src), 2418 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, 2419 EVEX, VEX_LIG; 2420def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), 2421 (ins i32mem:$dst, VR128X:$src), 2422 "vmovd\t{$src, $dst|$dst, $src}", 2423 [(store (i32 (vector_extract (v4i32 VR128X:$src), 2424 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>, 2425 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2426 2427// Move quadword from xmm1 register to r/m64 2428// 2429def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src), 2430 "vmovq\t{$src, $dst|$dst, $src}", 2431 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src), 2432 (iPTR 0)))], 2433 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W, 2434 Requires<[HasAVX512, In64BitMode]>; 2435 2436def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs), 2437 (ins i64mem:$dst, VR128X:$src), 2438 "vmovq\t{$src, $dst|$dst, $src}", 2439 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)), 2440 addr:$dst)], IIC_SSE_MOVDQ>, 2441 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>, 2442 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>; 2443 2444// Move Scalar Single to Double Int 2445// 2446let isCodeGenOnly = 1 in { 2447def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), 2448 (ins FR32X:$src), 2449 "vmovd\t{$src, $dst|$dst, $src}", 2450 [(set GR32:$dst, (bitconvert FR32X:$src))], 2451 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG; 2452def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), 2453 (ins i32mem:$dst, FR32X:$src), 2454 "vmovd\t{$src, $dst|$dst, $src}", 2455 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)], 2456 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2457} 2458 2459// Move Quadword Int to Packed Quadword Int 2460// 2461def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), 2462 (ins i64mem:$src), 2463 "vmovq\t{$src, $dst|$dst, $src}", 2464 [(set VR128X:$dst, 2465 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, 2466 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 2467 2468//===----------------------------------------------------------------------===// 2469// AVX-512 MOVSS, MOVSD 2470//===----------------------------------------------------------------------===// 2471 2472multiclass avx512_move_scalar <string asm, RegisterClass RC, 2473 SDNode OpNode, ValueType vt, 2474 X86MemOperand x86memop, PatFrag mem_pat> { 2475 let hasSideEffects = 0 in { 2476 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2), 2477 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2478 [(set VR128X:$dst, (vt (OpNode VR128X:$src1, 2479 (scalar_to_vector RC:$src2))))], 2480 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG; 2481 let Constraints = "$src1 = $dst" in 2482 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst), 2483 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3), 2484 !strconcat(asm, 2485 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"), 2486 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K; 2487 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 2488 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), 2489 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>, 2490 EVEX, VEX_LIG; 2491 let mayStore = 1 in { 2492 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src), 2493 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), 2494 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>, 2495 EVEX, VEX_LIG; 2496 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src), 2497 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), 2498 [], IIC_SSE_MOV_S_MR>, 2499 EVEX, VEX_LIG, EVEX_K; 2500 } // mayStore 2501 } //hasSideEffects = 0 2502} 2503 2504let ExeDomain = SSEPackedSingle in 2505defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem, 2506 loadf32>, XS, EVEX_CD8<32, CD8VT1>; 2507 2508let ExeDomain = SSEPackedDouble in 2509defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem, 2510 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>; 2511 2512def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))), 2513 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X), 2514 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>; 2515 2516def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), 2517 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X), 2518 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>; 2519 2520def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask), 2521 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)), 2522 (COPY_TO_REGCLASS VR128X:$src, FR32X))>; 2523 2524// For the disassembler 2525let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 2526 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst), 2527 (ins VR128X:$src1, FR32X:$src2), 2528 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [], 2529 IIC_SSE_MOV_S_RR>, 2530 XS, EVEX_4V, VEX_LIG; 2531 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst), 2532 (ins VR128X:$src1, FR64X:$src2), 2533 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [], 2534 IIC_SSE_MOV_S_RR>, 2535 XD, EVEX_4V, VEX_LIG, VEX_W; 2536} 2537 2538let Predicates = [HasAVX512] in { 2539 let AddedComplexity = 15 in { 2540 // Move scalar to XMM zero-extended, zeroing a VR128X then do a 2541 // MOVS{S,D} to the lower bits. 2542 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))), 2543 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>; 2544 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))), 2545 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>; 2546 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))), 2547 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>; 2548 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))), 2549 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>; 2550 2551 // Move low f32 and clear high bits. 2552 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))), 2553 (SUBREG_TO_REG (i32 0), 2554 (VMOVSSZrr (v4f32 (V_SET0)), 2555 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>; 2556 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))), 2557 (SUBREG_TO_REG (i32 0), 2558 (VMOVSSZrr (v4i32 (V_SET0)), 2559 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>; 2560 } 2561 2562 let AddedComplexity = 20 in { 2563 // MOVSSrm zeros the high parts of the register; represent this 2564 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 2565 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), 2566 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; 2567 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))), 2568 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; 2569 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), 2570 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; 2571 2572 // MOVSDrm zeros the high parts of the register; represent this 2573 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 2574 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), 2575 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 2576 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))), 2577 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 2578 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), 2579 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 2580 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), 2581 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 2582 def : Pat<(v2f64 (X86vzload addr:$src)), 2583 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 2584 2585 // Represent the same patterns above but in the form they appear for 2586 // 256-bit types 2587 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, 2588 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), 2589 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>; 2590 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, 2591 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), 2592 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; 2593 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, 2594 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), 2595 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; 2596 } 2597 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, 2598 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))), 2599 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)), 2600 FR32X:$src)), sub_xmm)>; 2601 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, 2602 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))), 2603 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)), 2604 FR64X:$src)), sub_xmm)>; 2605 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, 2606 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))), 2607 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>; 2608 2609 // Move low f64 and clear high bits. 2610 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))), 2611 (SUBREG_TO_REG (i32 0), 2612 (VMOVSDZrr (v2f64 (V_SET0)), 2613 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>; 2614 2615 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))), 2616 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)), 2617 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>; 2618 2619 // Extract and store. 2620 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))), 2621 addr:$dst), 2622 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>; 2623 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))), 2624 addr:$dst), 2625 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>; 2626 2627 // Shuffle with VMOVSS 2628 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)), 2629 (VMOVSSZrr (v4i32 VR128X:$src1), 2630 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>; 2631 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)), 2632 (VMOVSSZrr (v4f32 VR128X:$src1), 2633 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>; 2634 2635 // 256-bit variants 2636 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)), 2637 (SUBREG_TO_REG (i32 0), 2638 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm), 2639 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)), 2640 sub_xmm)>; 2641 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)), 2642 (SUBREG_TO_REG (i32 0), 2643 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm), 2644 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)), 2645 sub_xmm)>; 2646 2647 // Shuffle with VMOVSD 2648 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)), 2649 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2650 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)), 2651 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2652 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)), 2653 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2654 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)), 2655 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2656 2657 // 256-bit variants 2658 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)), 2659 (SUBREG_TO_REG (i32 0), 2660 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm), 2661 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)), 2662 sub_xmm)>; 2663 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)), 2664 (SUBREG_TO_REG (i32 0), 2665 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm), 2666 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)), 2667 sub_xmm)>; 2668 2669 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)), 2670 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2671 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)), 2672 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2673 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)), 2674 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2675 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)), 2676 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 2677} 2678 2679let AddedComplexity = 15 in 2680def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst), 2681 (ins VR128X:$src), 2682 "vmovq\t{$src, $dst|$dst, $src}", 2683 [(set VR128X:$dst, (v2i64 (X86vzmovl 2684 (v2i64 VR128X:$src))))], 2685 IIC_SSE_MOVQ_RR>, EVEX, VEX_W; 2686 2687let AddedComplexity = 20 in 2688def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst), 2689 (ins i128mem:$src), 2690 "vmovq\t{$src, $dst|$dst, $src}", 2691 [(set VR128X:$dst, (v2i64 (X86vzmovl 2692 (loadv2i64 addr:$src))))], 2693 IIC_SSE_MOVDQ>, EVEX, VEX_W, 2694 EVEX_CD8<8, CD8VT8>; 2695 2696let Predicates = [HasAVX512] in { 2697 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part. 2698 let AddedComplexity = 20 in { 2699 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), 2700 (VMOVDI2PDIZrm addr:$src)>; 2701 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), 2702 (VMOV64toPQIZrr GR64:$src)>; 2703 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), 2704 (VMOVDI2PDIZrr GR32:$src)>; 2705 2706 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))), 2707 (VMOVDI2PDIZrm addr:$src)>; 2708 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), 2709 (VMOVDI2PDIZrm addr:$src)>; 2710 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), 2711 (VMOVZPQILo2PQIZrm addr:$src)>; 2712 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))), 2713 (VMOVZPQILo2PQIZrr VR128X:$src)>; 2714 def : Pat<(v2i64 (X86vzload addr:$src)), 2715 (VMOVZPQILo2PQIZrm addr:$src)>; 2716 } 2717 2718 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. 2719 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, 2720 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), 2721 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>; 2722 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, 2723 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), 2724 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>; 2725} 2726 2727def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))), 2728 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>; 2729 2730def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))), 2731 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>; 2732 2733def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))), 2734 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>; 2735 2736def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))), 2737 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>; 2738 2739//===----------------------------------------------------------------------===// 2740// AVX-512 - Non-temporals 2741//===----------------------------------------------------------------------===// 2742let SchedRW = [WriteLoad] in { 2743 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst), 2744 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}", 2745 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))], 2746 SSEPackedInt>, EVEX, T8PD, EVEX_V512, 2747 EVEX_CD8<64, CD8VF>; 2748 2749 let Predicates = [HasAVX512, HasVLX] in { 2750 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst), 2751 (ins i256mem:$src), 2752 "vmovntdqa\t{$src, $dst|$dst, $src}", [], 2753 SSEPackedInt>, EVEX, T8PD, EVEX_V256, 2754 EVEX_CD8<64, CD8VF>; 2755 2756 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst), 2757 (ins i128mem:$src), 2758 "vmovntdqa\t{$src, $dst|$dst, $src}", [], 2759 SSEPackedInt>, EVEX, T8PD, EVEX_V128, 2760 EVEX_CD8<64, CD8VF>; 2761 } 2762} 2763 2764multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag, 2765 ValueType OpVT, RegisterClass RC, X86MemOperand memop, 2766 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> { 2767 let SchedRW = [WriteStore], mayStore = 1, 2768 AddedComplexity = 400 in 2769 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src), 2770 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 2771 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX; 2772} 2773 2774multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag, 2775 string elty, string elsz, string vsz512, 2776 string vsz256, string vsz128, Domain d, 2777 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> { 2778 let Predicates = [prd] in 2779 defm Z : avx512_movnt<opc, OpcodeStr, st_frag, 2780 !cast<ValueType>("v"##vsz512##elty##elsz), VR512, 2781 !cast<X86MemOperand>(elty##"512mem"), d, itin>, 2782 EVEX_V512; 2783 2784 let Predicates = [prd, HasVLX] in { 2785 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag, 2786 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X, 2787 !cast<X86MemOperand>(elty##"256mem"), d, itin>, 2788 EVEX_V256; 2789 2790 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag, 2791 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X, 2792 !cast<X86MemOperand>(elty##"128mem"), d, itin>, 2793 EVEX_V128; 2794 } 2795} 2796 2797defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore, 2798 "i", "64", "8", "4", "2", SSEPackedInt, 2799 HasAVX512>, PD, EVEX_CD8<64, CD8VF>; 2800 2801defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore, 2802 "f", "64", "8", "4", "2", SSEPackedDouble, 2803 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>; 2804 2805defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore, 2806 "f", "32", "16", "8", "4", SSEPackedSingle, 2807 HasAVX512>, PS, EVEX_CD8<32, CD8VF>; 2808 2809//===----------------------------------------------------------------------===// 2810// AVX-512 - Integer arithmetic 2811// 2812multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, 2813 X86VectorVTInfo _, OpndItins itins, 2814 bit IsCommutable = 0> { 2815 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 2816 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix, 2817 "$src2, $src1", "$src1, $src2", 2818 (_.VT (OpNode _.RC:$src1, _.RC:$src2)), 2819 "", itins.rr, IsCommutable>, 2820 AVX512BIBase, EVEX_4V; 2821 2822 let mayLoad = 1 in 2823 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 2824 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix, 2825 "$src2, $src1", "$src1, $src2", 2826 (_.VT (OpNode _.RC:$src1, 2827 (bitconvert (_.LdFrag addr:$src2)))), 2828 "", itins.rm>, 2829 AVX512BIBase, EVEX_4V; 2830} 2831 2832multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode, 2833 X86VectorVTInfo _, OpndItins itins, 2834 bit IsCommutable = 0> : 2835 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> { 2836 let mayLoad = 1 in 2837 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 2838 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix, 2839 "${src2}"##_.BroadcastStr##", $src1", 2840 "$src1, ${src2}"##_.BroadcastStr, 2841 (_.VT (OpNode _.RC:$src1, 2842 (X86VBroadcast 2843 (_.ScalarLdFrag addr:$src2)))), 2844 "", itins.rm>, 2845 AVX512BIBase, EVEX_4V, EVEX_B; 2846} 2847 2848multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode, 2849 AVX512VLVectorVTInfo VTInfo, OpndItins itins, 2850 Predicate prd, bit IsCommutable = 0> { 2851 let Predicates = [prd] in 2852 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins, 2853 IsCommutable>, EVEX_V512; 2854 2855 let Predicates = [prd, HasVLX] in { 2856 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins, 2857 IsCommutable>, EVEX_V256; 2858 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins, 2859 IsCommutable>, EVEX_V128; 2860 } 2861} 2862 2863multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode, 2864 AVX512VLVectorVTInfo VTInfo, OpndItins itins, 2865 Predicate prd, bit IsCommutable = 0> { 2866 let Predicates = [prd] in 2867 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins, 2868 IsCommutable>, EVEX_V512; 2869 2870 let Predicates = [prd, HasVLX] in { 2871 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins, 2872 IsCommutable>, EVEX_V256; 2873 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins, 2874 IsCommutable>, EVEX_V128; 2875 } 2876} 2877 2878multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode, 2879 OpndItins itins, Predicate prd, 2880 bit IsCommutable = 0> { 2881 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info, 2882 itins, prd, IsCommutable>, 2883 VEX_W, EVEX_CD8<64, CD8VF>; 2884} 2885 2886multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode, 2887 OpndItins itins, Predicate prd, 2888 bit IsCommutable = 0> { 2889 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info, 2890 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>; 2891} 2892 2893multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode, 2894 OpndItins itins, Predicate prd, 2895 bit IsCommutable = 0> { 2896 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info, 2897 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>; 2898} 2899 2900multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode, 2901 OpndItins itins, Predicate prd, 2902 bit IsCommutable = 0> { 2903 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info, 2904 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>; 2905} 2906 2907multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr, 2908 SDNode OpNode, OpndItins itins, Predicate prd, 2909 bit IsCommutable = 0> { 2910 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd, 2911 IsCommutable>; 2912 2913 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd, 2914 IsCommutable>; 2915} 2916 2917multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr, 2918 SDNode OpNode, OpndItins itins, Predicate prd, 2919 bit IsCommutable = 0> { 2920 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd, 2921 IsCommutable>; 2922 2923 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd, 2924 IsCommutable>; 2925} 2926 2927multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w, 2928 bits<8> opc_d, bits<8> opc_q, 2929 string OpcodeStr, SDNode OpNode, 2930 OpndItins itins, bit IsCommutable = 0> { 2931 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode, 2932 itins, HasAVX512, IsCommutable>, 2933 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode, 2934 itins, HasBWI, IsCommutable>; 2935} 2936 2937multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT, 2938 ValueType SrcVT, RegisterClass KRC, RegisterClass RC, 2939 PatFrag memop_frag, X86MemOperand x86memop, 2940 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop, 2941 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> { 2942 let isCommutable = IsCommutable in 2943 { 2944 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 2945 (ins RC:$src1, RC:$src2), 2946 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2947 []>, EVEX_4V; 2948 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 2949 (ins KRC:$mask, RC:$src1, RC:$src2), 2950 !strconcat(OpcodeStr, 2951 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 2952 [], itins.rr>, EVEX_4V, EVEX_K; 2953 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 2954 (ins KRC:$mask, RC:$src1, RC:$src2), 2955 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" , 2956 "|$dst {${mask}} {z}, $src1, $src2}"), 2957 [], itins.rr>, EVEX_4V, EVEX_KZ; 2958 } 2959 let mayLoad = 1 in { 2960 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2961 (ins RC:$src1, x86memop:$src2), 2962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2963 []>, EVEX_4V; 2964 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2965 (ins KRC:$mask, RC:$src1, x86memop:$src2), 2966 !strconcat(OpcodeStr, 2967 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 2968 [], itins.rm>, EVEX_4V, EVEX_K; 2969 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2970 (ins KRC:$mask, RC:$src1, x86memop:$src2), 2971 !strconcat(OpcodeStr, 2972 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"), 2973 [], itins.rm>, EVEX_4V, EVEX_KZ; 2974 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2975 (ins RC:$src1, x86scalar_mop:$src2), 2976 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr, 2977 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"), 2978 [], itins.rm>, EVEX_4V, EVEX_B; 2979 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2980 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), 2981 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr, 2982 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", 2983 BrdcstStr, "}"), 2984 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K; 2985 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2986 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), 2987 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr, 2988 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}", 2989 BrdcstStr, "}"), 2990 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ; 2991 } 2992} 2993 2994defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add, 2995 SSE_INTALU_ITINS_P, 1>; 2996defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub, 2997 SSE_INTALU_ITINS_P, 0>; 2998defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul, 2999 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD; 3000defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul, 3001 SSE_INTALU_ITINS_P, HasBWI, 1>; 3002defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul, 3003 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD; 3004 3005defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512, 3006 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 3007 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, 3008 EVEX_CD8<64, CD8VF>, VEX_W; 3009 3010defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512, 3011 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 3012 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W; 3013 3014def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))), 3015 (VPMULUDQZrr VR512:$src1, VR512:$src2)>; 3016 3017def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1), 3018 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 3019 (VPMULUDQZrr VR512:$src1, VR512:$src2)>; 3020def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1), 3021 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 3022 (VPMULDQZrr VR512:$src1, VR512:$src2)>; 3023 3024defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax, 3025 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD; 3026defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax, 3027 SSE_INTALU_ITINS_P, HasBWI, 1>; 3028defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax, 3029 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD; 3030 3031defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax, 3032 SSE_INTALU_ITINS_P, HasBWI, 1>; 3033defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax, 3034 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD; 3035defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax, 3036 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD; 3037 3038defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin, 3039 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD; 3040defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin, 3041 SSE_INTALU_ITINS_P, HasBWI, 1>; 3042defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin, 3043 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD; 3044 3045defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin, 3046 SSE_INTALU_ITINS_P, HasBWI, 1>; 3047defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin, 3048 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD; 3049defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin, 3050 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD; 3051 3052def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1), 3053 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 3054 (VPMAXSDZrr VR512:$src1, VR512:$src2)>; 3055def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1), 3056 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 3057 (VPMAXUDZrr VR512:$src1, VR512:$src2)>; 3058def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1), 3059 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 3060 (VPMAXSQZrr VR512:$src1, VR512:$src2)>; 3061def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1), 3062 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 3063 (VPMAXUQZrr VR512:$src1, VR512:$src2)>; 3064def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1), 3065 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 3066 (VPMINSDZrr VR512:$src1, VR512:$src2)>; 3067def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1), 3068 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 3069 (VPMINUDZrr VR512:$src1, VR512:$src2)>; 3070def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1), 3071 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 3072 (VPMINSQZrr VR512:$src1, VR512:$src2)>; 3073def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1), 3074 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 3075 (VPMINUQZrr VR512:$src1, VR512:$src2)>; 3076//===----------------------------------------------------------------------===// 3077// AVX-512 - Unpack Instructions 3078//===----------------------------------------------------------------------===// 3079 3080multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt, 3081 PatFrag mem_frag, RegisterClass RC, 3082 X86MemOperand x86memop, string asm, 3083 Domain d> { 3084 def rr : AVX512PI<opc, MRMSrcReg, 3085 (outs RC:$dst), (ins RC:$src1, RC:$src2), 3086 asm, [(set RC:$dst, 3087 (vt (OpNode RC:$src1, RC:$src2)))], 3088 d>, EVEX_4V; 3089 def rm : AVX512PI<opc, MRMSrcMem, 3090 (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 3091 asm, [(set RC:$dst, 3092 (vt (OpNode RC:$src1, 3093 (bitconvert (mem_frag addr:$src2)))))], 3094 d>, EVEX_4V; 3095} 3096 3097defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64, 3098 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3099 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 3100defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64, 3101 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3102 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 3103defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64, 3104 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3105 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 3106defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64, 3107 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3108 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 3109 3110multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode, 3111 ValueType OpVT, RegisterClass RC, PatFrag memop_frag, 3112 X86MemOperand x86memop> { 3113 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 3114 (ins RC:$src1, RC:$src2), 3115 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3116 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))], 3117 IIC_SSE_UNPCK>, EVEX_4V; 3118 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 3119 (ins RC:$src1, x86memop:$src2), 3120 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3121 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), 3122 (bitconvert (memop_frag addr:$src2)))))], 3123 IIC_SSE_UNPCK>, EVEX_4V; 3124} 3125defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32, 3126 VR512, memopv16i32, i512mem>, EVEX_V512, 3127 EVEX_CD8<32, CD8VF>; 3128defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64, 3129 VR512, memopv8i64, i512mem>, EVEX_V512, 3130 VEX_W, EVEX_CD8<64, CD8VF>; 3131defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32, 3132 VR512, memopv16i32, i512mem>, EVEX_V512, 3133 EVEX_CD8<32, CD8VF>; 3134defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64, 3135 VR512, memopv8i64, i512mem>, EVEX_V512, 3136 VEX_W, EVEX_CD8<64, CD8VF>; 3137//===----------------------------------------------------------------------===// 3138// AVX-512 - PSHUFD 3139// 3140 3141multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC, 3142 SDNode OpNode, PatFrag mem_frag, 3143 X86MemOperand x86memop, ValueType OpVT> { 3144 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst), 3145 (ins RC:$src1, i8imm:$src2), 3146 !strconcat(OpcodeStr, 3147 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3148 [(set RC:$dst, 3149 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>, 3150 EVEX; 3151 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst), 3152 (ins x86memop:$src1, i8imm:$src2), 3153 !strconcat(OpcodeStr, 3154 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3155 [(set RC:$dst, 3156 (OpVT (OpNode (mem_frag addr:$src1), 3157 (i8 imm:$src2))))]>, EVEX; 3158} 3159 3160defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32, 3161 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 3162 3163//===----------------------------------------------------------------------===// 3164// AVX-512 Logical Instructions 3165//===----------------------------------------------------------------------===// 3166 3167defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and, 3168 SSE_INTALU_ITINS_P, HasAVX512, 1>; 3169defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or, 3170 SSE_INTALU_ITINS_P, HasAVX512, 1>; 3171defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, 3172 SSE_INTALU_ITINS_P, HasAVX512, 1>; 3173defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp, 3174 SSE_INTALU_ITINS_P, HasAVX512, 1>; 3175 3176//===----------------------------------------------------------------------===// 3177// AVX-512 FP arithmetic 3178//===----------------------------------------------------------------------===// 3179 3180multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode, 3181 SizeItins itins> { 3182 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X, 3183 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG, 3184 EVEX_CD8<32, CD8VT1>; 3185 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X, 3186 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG, 3187 EVEX_CD8<64, CD8VT1>; 3188} 3189 3190let isCommutable = 1 in { 3191defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>; 3192defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>; 3193defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>; 3194defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>; 3195} 3196let isCommutable = 0 in { 3197defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>; 3198defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>; 3199} 3200 3201multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode, 3202 X86VectorVTInfo _, bit IsCommutable> { 3203 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 3204 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix, 3205 "$src2, $src1", "$src1, $src2", 3206 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V; 3207 let mayLoad = 1 in { 3208 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 3209 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix, 3210 "$src2, $src1", "$src1, $src2", 3211 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V; 3212 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 3213 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix, 3214 "${src2}"##_.BroadcastStr##", $src1", 3215 "$src1, ${src2}"##_.BroadcastStr, 3216 (OpNode _.RC:$src1, (_.VT (X86VBroadcast 3217 (_.ScalarLdFrag addr:$src2))))>, 3218 EVEX_4V, EVEX_B; 3219 }//let mayLoad = 1 3220} 3221 3222multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode, 3223 bit IsCommutable = 0> { 3224 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info, 3225 IsCommutable>, EVEX_V512, PS, 3226 EVEX_CD8<32, CD8VF>; 3227 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info, 3228 IsCommutable>, EVEX_V512, PD, VEX_W, 3229 EVEX_CD8<64, CD8VF>; 3230 3231 // Define only if AVX512VL feature is present. 3232 let Predicates = [HasVLX] in { 3233 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info, 3234 IsCommutable>, EVEX_V128, PS, 3235 EVEX_CD8<32, CD8VF>; 3236 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info, 3237 IsCommutable>, EVEX_V256, PS, 3238 EVEX_CD8<32, CD8VF>; 3239 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info, 3240 IsCommutable>, EVEX_V128, PD, VEX_W, 3241 EVEX_CD8<64, CD8VF>; 3242 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info, 3243 IsCommutable>, EVEX_V256, PD, VEX_W, 3244 EVEX_CD8<64, CD8VF>; 3245 } 3246} 3247 3248defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>; 3249defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>; 3250defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>; 3251defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>; 3252defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>; 3253defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>; 3254 3255def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1), 3256 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)), 3257 (i16 -1), FROUND_CURRENT)), 3258 (VMAXPSZrr VR512:$src1, VR512:$src2)>; 3259 3260def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1), 3261 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)), 3262 (i8 -1), FROUND_CURRENT)), 3263 (VMAXPDZrr VR512:$src1, VR512:$src2)>; 3264 3265def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1), 3266 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)), 3267 (i16 -1), FROUND_CURRENT)), 3268 (VMINPSZrr VR512:$src1, VR512:$src2)>; 3269 3270def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1), 3271 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)), 3272 (i8 -1), FROUND_CURRENT)), 3273 (VMINPDZrr VR512:$src1, VR512:$src2)>; 3274//===----------------------------------------------------------------------===// 3275// AVX-512 VPTESTM instructions 3276//===----------------------------------------------------------------------===// 3277 3278multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC, 3279 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag, 3280 SDNode OpNode, ValueType vt> { 3281 def rr : AVX512PI<opc, MRMSrcReg, 3282 (outs KRC:$dst), (ins RC:$src1, RC:$src2), 3283 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3284 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))], 3285 SSEPackedInt>, EVEX_4V; 3286 def rm : AVX512PI<opc, MRMSrcMem, 3287 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2), 3288 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3289 [(set KRC:$dst, (OpNode (vt RC:$src1), 3290 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V; 3291} 3292 3293defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem, 3294 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512, 3295 EVEX_CD8<32, CD8VF>; 3296defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem, 3297 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W, 3298 EVEX_CD8<64, CD8VF>; 3299 3300let Predicates = [HasCDI] in { 3301defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem, 3302 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512, 3303 EVEX_CD8<32, CD8VF>; 3304defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem, 3305 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W, 3306 EVEX_CD8<64, CD8VF>; 3307} 3308 3309def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1), 3310 (v16i32 VR512:$src2), (i16 -1))), 3311 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>; 3312 3313def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1), 3314 (v8i64 VR512:$src2), (i8 -1))), 3315 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>; 3316 3317//===----------------------------------------------------------------------===// 3318// AVX-512 Shift instructions 3319//===----------------------------------------------------------------------===// 3320multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM, 3321 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> { 3322 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst), 3323 (ins _.RC:$src1, i8imm:$src2), OpcodeStr, 3324 "$src2, $src1", "$src1, $src2", 3325 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))), 3326 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V; 3327 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst), 3328 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr, 3329 "$src2, $src1", "$src1, $src2", 3330 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))), 3331 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V; 3332} 3333 3334multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode, 3335 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> { 3336 // src2 is always 128-bit 3337 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 3338 (ins _.RC:$src1, VR128X:$src2), OpcodeStr, 3339 "$src2, $src1", "$src1, $src2", 3340 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))), 3341 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V; 3342 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 3343 (ins _.RC:$src1, i128mem:$src2), OpcodeStr, 3344 "$src2, $src1", "$src1, $src2", 3345 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))), 3346 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V; 3347} 3348 3349multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode, 3350 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> { 3351 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512; 3352} 3353 3354multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr, 3355 SDNode OpNode> { 3356 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32, 3357 v16i32_info>, EVEX_CD8<32, CD8VQ>; 3358 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64, 3359 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W; 3360} 3361 3362defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli, 3363 v16i32_info>, 3364 EVEX_V512, EVEX_CD8<32, CD8VF>; 3365defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli, 3366 v8i64_info>, EVEX_V512, 3367 EVEX_CD8<64, CD8VF>, VEX_W; 3368 3369defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli, 3370 v16i32_info>, EVEX_V512, 3371 EVEX_CD8<32, CD8VF>; 3372defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli, 3373 v8i64_info>, EVEX_V512, 3374 EVEX_CD8<64, CD8VF>, VEX_W; 3375 3376defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai, 3377 v16i32_info>, 3378 EVEX_V512, EVEX_CD8<32, CD8VF>; 3379defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai, 3380 v8i64_info>, EVEX_V512, 3381 EVEX_CD8<64, CD8VF>, VEX_W; 3382 3383defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>; 3384defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>; 3385defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>; 3386 3387//===-------------------------------------------------------------------===// 3388// Variable Bit Shifts 3389//===-------------------------------------------------------------------===// 3390multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode, 3391 X86VectorVTInfo _> { 3392 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 3393 (ins _.RC:$src1, _.RC:$src2), OpcodeStr, 3394 "$src2, $src1", "$src1, $src2", 3395 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))), 3396 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V; 3397 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 3398 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr, 3399 "$src2, $src1", "$src1, $src2", 3400 (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2))), 3401 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V; 3402} 3403 3404multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode, 3405 AVX512VLVectorVTInfo _> { 3406 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512; 3407} 3408 3409multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr, 3410 SDNode OpNode> { 3411 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode, 3412 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>; 3413 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode, 3414 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W; 3415} 3416 3417defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>; 3418defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>; 3419defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>; 3420 3421//===----------------------------------------------------------------------===// 3422// AVX-512 - MOVDDUP 3423//===----------------------------------------------------------------------===// 3424 3425multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT, 3426 X86MemOperand x86memop, PatFrag memop_frag> { 3427def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 3428 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 3429 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX; 3430def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 3431 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 3432 [(set RC:$dst, 3433 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX; 3434} 3435 3436defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>, 3437 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 3438def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))), 3439 (VMOVDDUPZrm addr:$src)>; 3440 3441//===---------------------------------------------------------------------===// 3442// Replicate Single FP - MOVSHDUP and MOVSLDUP 3443//===---------------------------------------------------------------------===// 3444multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr, 3445 ValueType vt, RegisterClass RC, PatFrag mem_frag, 3446 X86MemOperand x86memop> { 3447 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 3448 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 3449 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX; 3450 let mayLoad = 1 in 3451 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 3452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 3453 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX; 3454} 3455 3456defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup", 3457 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512, 3458 EVEX_CD8<32, CD8VF>; 3459defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup", 3460 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512, 3461 EVEX_CD8<32, CD8VF>; 3462 3463def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>; 3464def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))), 3465 (VMOVSHDUPZrm addr:$src)>; 3466def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>; 3467def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))), 3468 (VMOVSLDUPZrm addr:$src)>; 3469 3470//===----------------------------------------------------------------------===// 3471// Move Low to High and High to Low packed FP Instructions 3472//===----------------------------------------------------------------------===// 3473def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst), 3474 (ins VR128X:$src1, VR128X:$src2), 3475 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3476 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))], 3477 IIC_SSE_MOV_LH>, EVEX_4V; 3478def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst), 3479 (ins VR128X:$src1, VR128X:$src2), 3480 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3481 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))], 3482 IIC_SSE_MOV_LH>, EVEX_4V; 3483 3484let Predicates = [HasAVX512] in { 3485 // MOVLHPS patterns 3486 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)), 3487 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>; 3488 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)), 3489 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>; 3490 3491 // MOVHLPS patterns 3492 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)), 3493 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>; 3494} 3495 3496//===----------------------------------------------------------------------===// 3497// FMA - Fused Multiply Operations 3498// 3499 3500let Constraints = "$src1 = $dst" in { 3501// Omitting the parameter OpNode (= null_frag) disables ISel pattern matching. 3502multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, 3503 SDPatternOperator OpNode = null_frag> { 3504 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst), 3505 (ins _.RC:$src2, _.RC:$src3), 3506 OpcodeStr, "$src3, $src2", "$src2, $src3", 3507 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, 3508 AVX512FMA3Base; 3509 3510 let mayLoad = 1 in 3511 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst), 3512 (ins _.RC:$src2, _.MemOp:$src3), 3513 OpcodeStr, "$src3, $src2", "$src2, $src3", 3514 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>, 3515 AVX512FMA3Base; 3516 3517 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst), 3518 (ins _.RC:$src2, _.ScalarMemOp:$src3), 3519 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ), 3520 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>, 3521 AVX512FMA3Base, EVEX_B; 3522 } 3523} // Constraints = "$src1 = $dst" 3524 3525multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231, 3526 string OpcodeStr, X86VectorVTInfo VTI, 3527 SDPatternOperator OpNode> { 3528 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix), 3529 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>; 3530 3531 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix), 3532 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>; 3533} 3534 3535multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231, 3536 string OpcodeStr, 3537 SDPatternOperator OpNode> { 3538let ExeDomain = SSEPackedSingle in { 3539 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr, 3540 v16f32_info, OpNode>, EVEX_V512; 3541 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr, 3542 v8f32x_info, OpNode>, EVEX_V256; 3543 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr, 3544 v4f32x_info, OpNode>, EVEX_V128; 3545 } 3546let ExeDomain = SSEPackedDouble in { 3547 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr, 3548 v8f64_info, OpNode>, EVEX_V512, VEX_W; 3549 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr, 3550 v4f64x_info, OpNode>, EVEX_V256, VEX_W; 3551 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr, 3552 v2f64x_info, OpNode>, EVEX_V128, VEX_W; 3553 } 3554} 3555 3556defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd>; 3557defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub>; 3558defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub>; 3559defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd>; 3560defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd>; 3561defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub>; 3562 3563let Constraints = "$src1 = $dst" in { 3564multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode, 3565 X86VectorVTInfo _> { 3566 let mayLoad = 1 in 3567 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst), 3568 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2), 3569 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"), 3570 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2), 3571 _.RC:$src3)))]>; 3572 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst), 3573 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2), 3574 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, 3575 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"), 3576 [(set _.RC:$dst, 3577 (OpNode _.RC:$src1, (_.VT (X86VBroadcast 3578 (_.ScalarLdFrag addr:$src2))), 3579 _.RC:$src3))]>, EVEX_B; 3580} 3581} // Constraints = "$src1 = $dst" 3582 3583 3584multiclass avx512_fma3p_m132_f<bits<8> opc, 3585 string OpcodeStr, 3586 SDNode OpNode> { 3587 3588let ExeDomain = SSEPackedSingle in { 3589 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps, 3590 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>; 3591 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps, 3592 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>; 3593 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps, 3594 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>; 3595 } 3596let ExeDomain = SSEPackedDouble in { 3597 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd, 3598 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>; 3599 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd, 3600 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>; 3601 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd, 3602 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>; 3603 } 3604} 3605 3606defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>; 3607defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>; 3608defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>; 3609defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>; 3610defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>; 3611defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>; 3612 3613 3614// Scalar FMA 3615let Constraints = "$src1 = $dst" in { 3616multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, 3617 RegisterClass RC, ValueType OpVT, 3618 X86MemOperand x86memop, Operand memop, 3619 PatFrag mem_frag> { 3620 let isCommutable = 1 in 3621 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst), 3622 (ins RC:$src1, RC:$src2, RC:$src3), 3623 !strconcat(OpcodeStr, 3624 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 3625 [(set RC:$dst, 3626 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>; 3627 let mayLoad = 1 in 3628 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst), 3629 (ins RC:$src1, RC:$src2, f128mem:$src3), 3630 !strconcat(OpcodeStr, 3631 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 3632 [(set RC:$dst, 3633 (OpVT (OpNode RC:$src2, RC:$src1, 3634 (mem_frag addr:$src3))))]>; 3635} 3636 3637} // Constraints = "$src1 = $dst" 3638 3639defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X, 3640 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 3641defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X, 3642 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 3643defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X, 3644 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 3645defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X, 3646 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 3647defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X, 3648 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 3649defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X, 3650 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 3651defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X, 3652 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 3653defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X, 3654 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 3655 3656//===----------------------------------------------------------------------===// 3657// AVX-512 Scalar convert from sign integer to float/double 3658//===----------------------------------------------------------------------===// 3659 3660multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 3661 X86MemOperand x86memop, string asm> { 3662let hasSideEffects = 0 in { 3663 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src), 3664 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, 3665 EVEX_4V; 3666 let mayLoad = 1 in 3667 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), 3668 (ins DstRC:$src1, x86memop:$src), 3669 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, 3670 EVEX_4V; 3671} // hasSideEffects = 0 3672} 3673let Predicates = [HasAVX512] in { 3674defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">, 3675 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>; 3676defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">, 3677 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 3678defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">, 3679 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; 3680defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">, 3681 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 3682 3683def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))), 3684 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 3685def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))), 3686 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 3687def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))), 3688 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 3689def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))), 3690 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 3691 3692def : Pat<(f32 (sint_to_fp GR32:$src)), 3693 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; 3694def : Pat<(f32 (sint_to_fp GR64:$src)), 3695 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; 3696def : Pat<(f64 (sint_to_fp GR32:$src)), 3697 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; 3698def : Pat<(f64 (sint_to_fp GR64:$src)), 3699 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; 3700 3701defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">, 3702 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>; 3703defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">, 3704 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 3705defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">, 3706 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; 3707defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">, 3708 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 3709 3710def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))), 3711 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 3712def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))), 3713 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 3714def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))), 3715 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 3716def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))), 3717 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 3718 3719def : Pat<(f32 (uint_to_fp GR32:$src)), 3720 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; 3721def : Pat<(f32 (uint_to_fp GR64:$src)), 3722 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; 3723def : Pat<(f64 (uint_to_fp GR32:$src)), 3724 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; 3725def : Pat<(f64 (uint_to_fp GR64:$src)), 3726 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; 3727} 3728 3729//===----------------------------------------------------------------------===// 3730// AVX-512 Scalar convert from float/double to integer 3731//===----------------------------------------------------------------------===// 3732multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 3733 Intrinsic Int, Operand memop, ComplexPattern mem_cpat, 3734 string asm> { 3735let hasSideEffects = 0 in { 3736 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 3737 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 3738 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG, 3739 Requires<[HasAVX512]>; 3740 let mayLoad = 1 in 3741 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src), 3742 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG, 3743 Requires<[HasAVX512]>; 3744} // hasSideEffects = 0 3745} 3746let Predicates = [HasAVX512] in { 3747// Convert float/double to signed/unsigned int 32/64 3748defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si, 3749 ssmem, sse_load_f32, "cvtss2si">, 3750 XS, EVEX_CD8<32, CD8VT1>; 3751defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64, 3752 ssmem, sse_load_f32, "cvtss2si">, 3753 XS, VEX_W, EVEX_CD8<32, CD8VT1>; 3754defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi, 3755 ssmem, sse_load_f32, "cvtss2usi">, 3756 XS, EVEX_CD8<32, CD8VT1>; 3757defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64, 3758 int_x86_avx512_cvtss2usi64, ssmem, 3759 sse_load_f32, "cvtss2usi">, XS, VEX_W, 3760 EVEX_CD8<32, CD8VT1>; 3761defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si, 3762 sdmem, sse_load_f64, "cvtsd2si">, 3763 XD, EVEX_CD8<64, CD8VT1>; 3764defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64, 3765 sdmem, sse_load_f64, "cvtsd2si">, 3766 XD, VEX_W, EVEX_CD8<64, CD8VT1>; 3767defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi, 3768 sdmem, sse_load_f64, "cvtsd2usi">, 3769 XD, EVEX_CD8<64, CD8VT1>; 3770defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64, 3771 int_x86_avx512_cvtsd2usi64, sdmem, 3772 sse_load_f64, "cvtsd2usi">, XD, VEX_W, 3773 EVEX_CD8<64, CD8VT1>; 3774 3775let isCodeGenOnly = 1 in { 3776 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 3777 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}", 3778 SSE_CVT_Scalar, 0>, XS, EVEX_4V; 3779 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 3780 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}", 3781 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W; 3782 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 3783 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}", 3784 SSE_CVT_Scalar, 0>, XD, EVEX_4V; 3785 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 3786 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}", 3787 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W; 3788 3789 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 3790 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}", 3791 SSE_CVT_Scalar, 0>, XS, EVEX_4V; 3792 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 3793 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}", 3794 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W; 3795 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 3796 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}", 3797 SSE_CVT_Scalar, 0>, XD, EVEX_4V; 3798 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 3799 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}", 3800 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W; 3801} // isCodeGenOnly = 1 3802 3803// Convert float/double to signed/unsigned int 32/64 with truncation 3804let isCodeGenOnly = 1 in { 3805 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si, 3806 ssmem, sse_load_f32, "cvttss2si">, 3807 XS, EVEX_CD8<32, CD8VT1>; 3808 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64, 3809 int_x86_sse_cvttss2si64, ssmem, sse_load_f32, 3810 "cvttss2si">, XS, VEX_W, 3811 EVEX_CD8<32, CD8VT1>; 3812 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si, 3813 sdmem, sse_load_f64, "cvttsd2si">, XD, 3814 EVEX_CD8<64, CD8VT1>; 3815 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64, 3816 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64, 3817 "cvttsd2si">, XD, VEX_W, 3818 EVEX_CD8<64, CD8VT1>; 3819 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32, 3820 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32, 3821 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>; 3822 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64, 3823 int_x86_avx512_cvttss2usi64, ssmem, 3824 sse_load_f32, "cvttss2usi">, XS, VEX_W, 3825 EVEX_CD8<32, CD8VT1>; 3826 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32, 3827 int_x86_avx512_cvttsd2usi, 3828 sdmem, sse_load_f64, "cvttsd2usi">, XD, 3829 EVEX_CD8<64, CD8VT1>; 3830 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64, 3831 int_x86_avx512_cvttsd2usi64, sdmem, 3832 sse_load_f64, "cvttsd2usi">, XD, VEX_W, 3833 EVEX_CD8<64, CD8VT1>; 3834} // isCodeGenOnly = 1 3835 3836multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 3837 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, 3838 string asm> { 3839 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 3840 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 3841 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX; 3842 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 3843 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 3844 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX; 3845} 3846 3847defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem, 3848 loadf32, "cvttss2si">, XS, 3849 EVEX_CD8<32, CD8VT1>; 3850defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem, 3851 loadf32, "cvttss2usi">, XS, 3852 EVEX_CD8<32, CD8VT1>; 3853defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem, 3854 loadf32, "cvttss2si">, XS, VEX_W, 3855 EVEX_CD8<32, CD8VT1>; 3856defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem, 3857 loadf32, "cvttss2usi">, XS, VEX_W, 3858 EVEX_CD8<32, CD8VT1>; 3859defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem, 3860 loadf64, "cvttsd2si">, XD, 3861 EVEX_CD8<64, CD8VT1>; 3862defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem, 3863 loadf64, "cvttsd2usi">, XD, 3864 EVEX_CD8<64, CD8VT1>; 3865defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem, 3866 loadf64, "cvttsd2si">, XD, VEX_W, 3867 EVEX_CD8<64, CD8VT1>; 3868defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem, 3869 loadf64, "cvttsd2usi">, XD, VEX_W, 3870 EVEX_CD8<64, CD8VT1>; 3871} // HasAVX512 3872//===----------------------------------------------------------------------===// 3873// AVX-512 Convert form float to double and back 3874//===----------------------------------------------------------------------===// 3875let hasSideEffects = 0 in { 3876def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst), 3877 (ins FR32X:$src1, FR32X:$src2), 3878 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3879 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>; 3880let mayLoad = 1 in 3881def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst), 3882 (ins FR32X:$src1, f32mem:$src2), 3883 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3884 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>, 3885 EVEX_CD8<32, CD8VT1>; 3886 3887// Convert scalar double to scalar single 3888def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst), 3889 (ins FR64X:$src1, FR64X:$src2), 3890 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3891 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>; 3892let mayLoad = 1 in 3893def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst), 3894 (ins FR64X:$src1, f64mem:$src2), 3895 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", 3896 []>, EVEX_4V, VEX_LIG, VEX_W, 3897 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>; 3898} 3899 3900def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>, 3901 Requires<[HasAVX512]>; 3902def : Pat<(fextend (loadf32 addr:$src)), 3903 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>; 3904 3905def : Pat<(extloadf32 addr:$src), 3906 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, 3907 Requires<[HasAVX512, OptForSize]>; 3908 3909def : Pat<(extloadf32 addr:$src), 3910 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>, 3911 Requires<[HasAVX512, OptForSpeed]>; 3912 3913def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>, 3914 Requires<[HasAVX512]>; 3915 3916multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC, 3917 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag, 3918 X86MemOperand x86memop, ValueType OpVT, ValueType InVT, 3919 Domain d> { 3920let hasSideEffects = 0 in { 3921 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 3922 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 3923 [(set DstRC:$dst, 3924 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX; 3925 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc), 3926 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), 3927 [], d>, EVEX, EVEX_B, EVEX_RC; 3928 let mayLoad = 1 in 3929 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 3930 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 3931 [(set DstRC:$dst, 3932 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX; 3933} // hasSideEffects = 0 3934} 3935 3936multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC, 3937 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag, 3938 X86MemOperand x86memop, ValueType OpVT, ValueType InVT, 3939 Domain d> { 3940let hasSideEffects = 0 in { 3941 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 3942 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 3943 [(set DstRC:$dst, 3944 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX; 3945 let mayLoad = 1 in 3946 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 3947 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 3948 [(set DstRC:$dst, 3949 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX; 3950} // hasSideEffects = 0 3951} 3952 3953defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround, 3954 memopv8f64, f512mem, v8f32, v8f64, 3955 SSEPackedSingle>, EVEX_V512, VEX_W, PD, 3956 EVEX_CD8<64, CD8VF>; 3957 3958defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend, 3959 memopv4f64, f256mem, v8f64, v8f32, 3960 SSEPackedDouble>, EVEX_V512, PS, 3961 EVEX_CD8<32, CD8VH>; 3962def : Pat<(v8f64 (extloadv8f32 addr:$src)), 3963 (VCVTPS2PDZrm addr:$src)>; 3964 3965def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src), 3966 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))), 3967 (VCVTPD2PSZrr VR512:$src)>; 3968 3969def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src), 3970 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)), 3971 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>; 3972 3973//===----------------------------------------------------------------------===// 3974// AVX-512 Vector convert from sign integer to float/double 3975//===----------------------------------------------------------------------===// 3976 3977defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp, 3978 memopv8i64, i512mem, v16f32, v16i32, 3979 SSEPackedSingle>, EVEX_V512, PS, 3980 EVEX_CD8<32, CD8VF>; 3981 3982defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp, 3983 memopv4i64, i256mem, v8f64, v8i32, 3984 SSEPackedDouble>, EVEX_V512, XS, 3985 EVEX_CD8<32, CD8VH>; 3986 3987defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint, 3988 memopv16f32, f512mem, v16i32, v16f32, 3989 SSEPackedSingle>, EVEX_V512, XS, 3990 EVEX_CD8<32, CD8VF>; 3991 3992defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint, 3993 memopv8f64, f512mem, v8i32, v8f64, 3994 SSEPackedDouble>, EVEX_V512, PD, VEX_W, 3995 EVEX_CD8<64, CD8VF>; 3996 3997defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint, 3998 memopv16f32, f512mem, v16i32, v16f32, 3999 SSEPackedSingle>, EVEX_V512, PS, 4000 EVEX_CD8<32, CD8VF>; 4001 4002// cvttps2udq (src, 0, mask-all-ones, sae-current) 4003def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src), 4004 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)), 4005 (VCVTTPS2UDQZrr VR512:$src)>; 4006 4007defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint, 4008 memopv8f64, f512mem, v8i32, v8f64, 4009 SSEPackedDouble>, EVEX_V512, PS, VEX_W, 4010 EVEX_CD8<64, CD8VF>; 4011 4012// cvttpd2udq (src, 0, mask-all-ones, sae-current) 4013def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src), 4014 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)), 4015 (VCVTTPD2UDQZrr VR512:$src)>; 4016 4017defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp, 4018 memopv4i64, f256mem, v8f64, v8i32, 4019 SSEPackedDouble>, EVEX_V512, XS, 4020 EVEX_CD8<32, CD8VH>; 4021 4022defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp, 4023 memopv16i32, f512mem, v16f32, v16i32, 4024 SSEPackedSingle>, EVEX_V512, XD, 4025 EVEX_CD8<32, CD8VF>; 4026 4027def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))), 4028 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr 4029 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>; 4030 4031def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))), 4032 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr 4033 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>; 4034 4035def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))), 4036 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr 4037 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>; 4038 4039def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))), 4040 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr 4041 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>; 4042 4043def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))), 4044 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr 4045 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>; 4046 4047def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src), 4048 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)), 4049 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>; 4050def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src), 4051 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 4052 (VCVTDQ2PDZrr VR256X:$src)>; 4053def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src), 4054 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)), 4055 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>; 4056def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src), 4057 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 4058 (VCVTUDQ2PDZrr VR256X:$src)>; 4059 4060multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC, 4061 RegisterClass DstRC, PatFrag mem_frag, 4062 X86MemOperand x86memop, Domain d> { 4063let hasSideEffects = 0 in { 4064 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 4065 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 4066 [], d>, EVEX; 4067 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc), 4068 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), 4069 [], d>, EVEX, EVEX_B, EVEX_RC; 4070 let mayLoad = 1 in 4071 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 4072 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), 4073 [], d>, EVEX; 4074} // hasSideEffects = 0 4075} 4076 4077defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512, 4078 memopv16f32, f512mem, SSEPackedSingle>, PD, 4079 EVEX_V512, EVEX_CD8<32, CD8VF>; 4080defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X, 4081 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W, 4082 EVEX_V512, EVEX_CD8<64, CD8VF>; 4083 4084def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src), 4085 (v16i32 immAllZerosV), (i16 -1), imm:$rc)), 4086 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>; 4087 4088def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src), 4089 (v8i32 immAllZerosV), (i8 -1), imm:$rc)), 4090 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>; 4091 4092defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512, 4093 memopv16f32, f512mem, SSEPackedSingle>, 4094 PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 4095defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X, 4096 memopv8f64, f512mem, SSEPackedDouble>, VEX_W, 4097 PS, EVEX_V512, EVEX_CD8<64, CD8VF>; 4098 4099def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src), 4100 (v16i32 immAllZerosV), (i16 -1), imm:$rc)), 4101 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>; 4102 4103def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src), 4104 (v8i32 immAllZerosV), (i8 -1), imm:$rc)), 4105 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>; 4106 4107let Predicates = [HasAVX512] in { 4108 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))), 4109 (VCVTPD2PSZrm addr:$src)>; 4110 def : Pat<(v8f64 (extloadv8f32 addr:$src)), 4111 (VCVTPS2PDZrm addr:$src)>; 4112} 4113 4114//===----------------------------------------------------------------------===// 4115// Half precision conversion instructions 4116//===----------------------------------------------------------------------===// 4117multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC, 4118 X86MemOperand x86memop> { 4119 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src), 4120 "vcvtph2ps\t{$src, $dst|$dst, $src}", 4121 []>, EVEX; 4122 let hasSideEffects = 0, mayLoad = 1 in 4123 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src), 4124 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX; 4125} 4126 4127multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC, 4128 X86MemOperand x86memop> { 4129 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst), 4130 (ins srcRC:$src1, i32i8imm:$src2), 4131 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", 4132 []>, EVEX; 4133 let hasSideEffects = 0, mayStore = 1 in 4134 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), 4135 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2), 4136 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX; 4137} 4138 4139defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512, 4140 EVEX_CD8<32, CD8VH>; 4141defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512, 4142 EVEX_CD8<32, CD8VH>; 4143 4144def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src), 4145 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))), 4146 (VCVTPS2PHZrr VR512:$src, imm:$rc)>; 4147 4148def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src), 4149 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))), 4150 (VCVTPH2PSZrr VR256X:$src)>; 4151 4152let Defs = [EFLAGS], Predicates = [HasAVX512] in { 4153 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32, 4154 "ucomiss">, PS, EVEX, VEX_LIG, 4155 EVEX_CD8<32, CD8VT1>; 4156 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64, 4157 "ucomisd">, PD, EVEX, 4158 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 4159 let Pattern = []<dag> in { 4160 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load, 4161 "comiss">, PS, EVEX, VEX_LIG, 4162 EVEX_CD8<32, CD8VT1>; 4163 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load, 4164 "comisd">, PD, EVEX, 4165 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 4166 } 4167 let isCodeGenOnly = 1 in { 4168 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem, 4169 load, "ucomiss">, PS, EVEX, VEX_LIG, 4170 EVEX_CD8<32, CD8VT1>; 4171 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem, 4172 load, "ucomisd">, PD, EVEX, 4173 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 4174 4175 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem, 4176 load, "comiss">, PS, EVEX, VEX_LIG, 4177 EVEX_CD8<32, CD8VT1>; 4178 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem, 4179 load, "comisd">, PD, EVEX, 4180 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 4181 } 4182} 4183 4184/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd 4185multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC, 4186 X86MemOperand x86memop> { 4187 let hasSideEffects = 0 in { 4188 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 4189 (ins RC:$src1, RC:$src2), 4190 !strconcat(OpcodeStr, 4191 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V; 4192 let mayLoad = 1 in { 4193 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 4194 (ins RC:$src1, x86memop:$src2), 4195 !strconcat(OpcodeStr, 4196 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V; 4197 } 4198} 4199} 4200 4201defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>, 4202 EVEX_CD8<32, CD8VT1>; 4203defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>, 4204 VEX_W, EVEX_CD8<64, CD8VT1>; 4205defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>, 4206 EVEX_CD8<32, CD8VT1>; 4207defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>, 4208 VEX_W, EVEX_CD8<64, CD8VT1>; 4209 4210def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1), 4211 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))), 4212 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X), 4213 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; 4214 4215def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1), 4216 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))), 4217 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X), 4218 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; 4219 4220def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1), 4221 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))), 4222 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X), 4223 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; 4224 4225def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1), 4226 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))), 4227 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X), 4228 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; 4229 4230/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd 4231multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode, 4232 X86VectorVTInfo _> { 4233 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 4234 (ins _.RC:$src), OpcodeStr, "$src", "$src", 4235 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD; 4236 let mayLoad = 1 in { 4237 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 4238 (ins _.MemOp:$src), OpcodeStr, "$src", "$src", 4239 (OpNode (_.FloatVT 4240 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD; 4241 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 4242 (ins _.ScalarMemOp:$src), OpcodeStr, 4243 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr, 4244 (OpNode (_.FloatVT 4245 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>, 4246 EVEX, T8PD, EVEX_B; 4247 } 4248} 4249 4250multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> { 4251 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>, 4252 EVEX_V512, EVEX_CD8<32, CD8VF>; 4253 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>, 4254 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 4255 4256 // Define only if AVX512VL feature is present. 4257 let Predicates = [HasVLX] in { 4258 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), 4259 OpNode, v4f32x_info>, 4260 EVEX_V128, EVEX_CD8<32, CD8VF>; 4261 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), 4262 OpNode, v8f32x_info>, 4263 EVEX_V256, EVEX_CD8<32, CD8VF>; 4264 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), 4265 OpNode, v2f64x_info>, 4266 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; 4267 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), 4268 OpNode, v4f64x_info>, 4269 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; 4270 } 4271} 4272 4273defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>; 4274defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>; 4275 4276def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src), 4277 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))), 4278 (VRSQRT14PSZr VR512:$src)>; 4279def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src), 4280 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 4281 (VRSQRT14PDZr VR512:$src)>; 4282 4283def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src), 4284 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))), 4285 (VRCP14PSZr VR512:$src)>; 4286def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src), 4287 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 4288 (VRCP14PDZr VR512:$src)>; 4289 4290/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd 4291multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _, 4292 SDNode OpNode> { 4293 4294 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), 4295 (ins _.RC:$src1, _.RC:$src2), OpcodeStr, 4296 "$src2, $src1", "$src1, $src2", 4297 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), 4298 (i32 FROUND_CURRENT))>; 4299 4300 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), 4301 (ins _.RC:$src1, _.RC:$src2), OpcodeStr, 4302 "$src2, $src1", "$src1, $src2", 4303 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), 4304 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B; 4305 4306 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst), 4307 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr, 4308 "$src2, $src1", "$src1, $src2", 4309 (OpNode (_.VT _.RC:$src1), 4310 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))), 4311 (i32 FROUND_CURRENT))>; 4312} 4313 4314multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> { 4315 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>, 4316 EVEX_CD8<32, CD8VT1>; 4317 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>, 4318 EVEX_CD8<64, CD8VT1>, VEX_W; 4319} 4320 4321let hasSideEffects = 0, Predicates = [HasERI] in { 4322 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V; 4323 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V; 4324} 4325/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd 4326 4327multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, 4328 SDNode OpNode> { 4329 4330 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 4331 (ins _.RC:$src), OpcodeStr, "$src", "$src", 4332 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>; 4333 4334 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 4335 (ins _.RC:$src), OpcodeStr, 4336 "$src", "$src", 4337 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)), 4338 "{sae}">, EVEX_B; 4339 4340 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 4341 (ins _.MemOp:$src), OpcodeStr, "$src", "$src", 4342 (OpNode (_.FloatVT 4343 (bitconvert (_.LdFrag addr:$src))), 4344 (i32 FROUND_CURRENT))>; 4345 4346 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 4347 (ins _.MemOp:$src), OpcodeStr, "$src", "$src", 4348 (OpNode (_.FloatVT 4349 (X86VBroadcast (_.ScalarLdFrag addr:$src))), 4350 (i32 FROUND_CURRENT))>, EVEX_B; 4351} 4352 4353multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> { 4354 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>, 4355 EVEX_CD8<32, CD8VF>; 4356 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>, 4357 VEX_W, EVEX_CD8<32, CD8VF>; 4358} 4359 4360let Predicates = [HasERI], hasSideEffects = 0 in { 4361 4362 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD; 4363 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD; 4364 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD; 4365} 4366 4367multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, 4368 SDNode OpNode, X86VectorVTInfo _>{ 4369 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), 4370 (ins _.RC:$src), OpcodeStr, "$src", "$src", 4371 (_.FloatVT (OpNode _.RC:$src))>, EVEX; 4372 let mayLoad = 1 in { 4373 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 4374 (ins _.MemOp:$src), OpcodeStr, "$src", "$src", 4375 (OpNode (_.FloatVT 4376 (bitconvert (_.LdFrag addr:$src))))>, EVEX; 4377 4378 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), 4379 (ins _.ScalarMemOp:$src), OpcodeStr, 4380 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr, 4381 (OpNode (_.FloatVT 4382 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>, 4383 EVEX, EVEX_B; 4384 } 4385} 4386 4387multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr, 4388 Intrinsic F32Int, Intrinsic F64Int, 4389 OpndItins itins_s, OpndItins itins_d> { 4390 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst), 4391 (ins FR32X:$src1, FR32X:$src2), 4392 !strconcat(OpcodeStr, 4393 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4394 [], itins_s.rr>, XS, EVEX_4V; 4395 let isCodeGenOnly = 1 in 4396 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst), 4397 (ins VR128X:$src1, VR128X:$src2), 4398 !strconcat(OpcodeStr, 4399 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4400 [(set VR128X:$dst, 4401 (F32Int VR128X:$src1, VR128X:$src2))], 4402 itins_s.rr>, XS, EVEX_4V; 4403 let mayLoad = 1 in { 4404 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst), 4405 (ins FR32X:$src1, f32mem:$src2), 4406 !strconcat(OpcodeStr, 4407 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4408 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>; 4409 let isCodeGenOnly = 1 in 4410 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst), 4411 (ins VR128X:$src1, ssmem:$src2), 4412 !strconcat(OpcodeStr, 4413 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4414 [(set VR128X:$dst, 4415 (F32Int VR128X:$src1, sse_load_f32:$src2))], 4416 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>; 4417 } 4418 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst), 4419 (ins FR64X:$src1, FR64X:$src2), 4420 !strconcat(OpcodeStr, 4421 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, 4422 XD, EVEX_4V, VEX_W; 4423 let isCodeGenOnly = 1 in 4424 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst), 4425 (ins VR128X:$src1, VR128X:$src2), 4426 !strconcat(OpcodeStr, 4427 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4428 [(set VR128X:$dst, 4429 (F64Int VR128X:$src1, VR128X:$src2))], 4430 itins_s.rr>, XD, EVEX_4V, VEX_W; 4431 let mayLoad = 1 in { 4432 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst), 4433 (ins FR64X:$src1, f64mem:$src2), 4434 !strconcat(OpcodeStr, 4435 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, 4436 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>; 4437 let isCodeGenOnly = 1 in 4438 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst), 4439 (ins VR128X:$src1, sdmem:$src2), 4440 !strconcat(OpcodeStr, 4441 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4442 [(set VR128X:$dst, 4443 (F64Int VR128X:$src1, sse_load_f64:$src2))]>, 4444 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>; 4445 } 4446} 4447 4448multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr, 4449 SDNode OpNode> { 4450 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, 4451 v16f32_info>, 4452 EVEX_V512, PS, EVEX_CD8<32, CD8VF>; 4453 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, 4454 v8f64_info>, 4455 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>; 4456 // Define only if AVX512VL feature is present. 4457 let Predicates = [HasVLX] in { 4458 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), 4459 OpNode, v4f32x_info>, 4460 EVEX_V128, PS, EVEX_CD8<32, CD8VF>; 4461 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), 4462 OpNode, v8f32x_info>, 4463 EVEX_V256, PS, EVEX_CD8<32, CD8VF>; 4464 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), 4465 OpNode, v2f64x_info>, 4466 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>; 4467 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), 4468 OpNode, v4f64x_info>, 4469 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>; 4470 } 4471} 4472 4473defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>; 4474 4475defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt", 4476 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd, 4477 SSE_SQRTSS, SSE_SQRTSD>; 4478 4479let Predicates = [HasAVX512] in { 4480 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1), 4481 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)), 4482 (VSQRTPSZr VR512:$src1)>; 4483 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1), 4484 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)), 4485 (VSQRTPDZr VR512:$src1)>; 4486 4487 def : Pat<(f32 (fsqrt FR32X:$src)), 4488 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>; 4489 def : Pat<(f32 (fsqrt (load addr:$src))), 4490 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>, 4491 Requires<[OptForSize]>; 4492 def : Pat<(f64 (fsqrt FR64X:$src)), 4493 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>; 4494 def : Pat<(f64 (fsqrt (load addr:$src))), 4495 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>, 4496 Requires<[OptForSize]>; 4497 4498 def : Pat<(f32 (X86frsqrt FR32X:$src)), 4499 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>; 4500 def : Pat<(f32 (X86frsqrt (load addr:$src))), 4501 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>, 4502 Requires<[OptForSize]>; 4503 4504 def : Pat<(f32 (X86frcp FR32X:$src)), 4505 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>; 4506 def : Pat<(f32 (X86frcp (load addr:$src))), 4507 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>, 4508 Requires<[OptForSize]>; 4509 4510 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src), 4511 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)), 4512 (COPY_TO_REGCLASS VR128X:$src, FR32)), 4513 VR128X)>; 4514 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src), 4515 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>; 4516 4517 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src), 4518 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)), 4519 (COPY_TO_REGCLASS VR128X:$src, FR64)), 4520 VR128X)>; 4521 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src), 4522 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>; 4523} 4524 4525 4526multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr, 4527 X86MemOperand x86memop, RegisterClass RC, 4528 PatFrag mem_frag32, PatFrag mem_frag64, 4529 Intrinsic V4F32Int, Intrinsic V2F64Int, 4530 CD8VForm VForm> { 4531let ExeDomain = SSEPackedSingle in { 4532 // Intrinsic operation, reg. 4533 // Vector intrinsic operation, reg 4534 def PSr : AVX512AIi8<opcps, MRMSrcReg, 4535 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2), 4536 !strconcat(OpcodeStr, 4537 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4538 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>; 4539 4540 // Vector intrinsic operation, mem 4541 def PSm : AVX512AIi8<opcps, MRMSrcMem, 4542 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2), 4543 !strconcat(OpcodeStr, 4544 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4545 [(set RC:$dst, 4546 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>, 4547 EVEX_CD8<32, VForm>; 4548} // ExeDomain = SSEPackedSingle 4549 4550let ExeDomain = SSEPackedDouble in { 4551 // Vector intrinsic operation, reg 4552 def PDr : AVX512AIi8<opcpd, MRMSrcReg, 4553 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2), 4554 !strconcat(OpcodeStr, 4555 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4556 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>; 4557 4558 // Vector intrinsic operation, mem 4559 def PDm : AVX512AIi8<opcpd, MRMSrcMem, 4560 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2), 4561 !strconcat(OpcodeStr, 4562 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4563 [(set RC:$dst, 4564 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>, 4565 EVEX_CD8<64, VForm>; 4566} // ExeDomain = SSEPackedDouble 4567} 4568 4569multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd, 4570 string OpcodeStr, 4571 Intrinsic F32Int, 4572 Intrinsic F64Int> { 4573let ExeDomain = GenericDomain in { 4574 // Operation, reg. 4575 let hasSideEffects = 0 in 4576 def SSr : AVX512AIi8<opcss, MRMSrcReg, 4577 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3), 4578 !strconcat(OpcodeStr, 4579 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4580 []>; 4581 4582 // Intrinsic operation, reg. 4583 let isCodeGenOnly = 1 in 4584 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg, 4585 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3), 4586 !strconcat(OpcodeStr, 4587 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4588 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>; 4589 4590 // Intrinsic operation, mem. 4591 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst), 4592 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3), 4593 !strconcat(OpcodeStr, 4594 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4595 [(set VR128X:$dst, (F32Int VR128X:$src1, 4596 sse_load_f32:$src2, imm:$src3))]>, 4597 EVEX_CD8<32, CD8VT1>; 4598 4599 // Operation, reg. 4600 let hasSideEffects = 0 in 4601 def SDr : AVX512AIi8<opcsd, MRMSrcReg, 4602 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3), 4603 !strconcat(OpcodeStr, 4604 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4605 []>, VEX_W; 4606 4607 // Intrinsic operation, reg. 4608 let isCodeGenOnly = 1 in 4609 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg, 4610 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3), 4611 !strconcat(OpcodeStr, 4612 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4613 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>, 4614 VEX_W; 4615 4616 // Intrinsic operation, mem. 4617 def SDm : AVX512AIi8<opcsd, MRMSrcMem, 4618 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3), 4619 !strconcat(OpcodeStr, 4620 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4621 [(set VR128X:$dst, 4622 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>, 4623 VEX_W, EVEX_CD8<64, CD8VT1>; 4624} // ExeDomain = GenericDomain 4625} 4626 4627multiclass avx512_rndscale<bits<8> opc, string OpcodeStr, 4628 X86MemOperand x86memop, RegisterClass RC, 4629 PatFrag mem_frag, Domain d> { 4630let ExeDomain = d in { 4631 // Intrinsic operation, reg. 4632 // Vector intrinsic operation, reg 4633 def r : AVX512AIi8<opc, MRMSrcReg, 4634 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2), 4635 !strconcat(OpcodeStr, 4636 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4637 []>, EVEX; 4638 4639 // Vector intrinsic operation, mem 4640 def m : AVX512AIi8<opc, MRMSrcMem, 4641 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2), 4642 !strconcat(OpcodeStr, 4643 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4644 []>, EVEX; 4645} // ExeDomain 4646} 4647 4648 4649defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512, 4650 memopv16f32, SSEPackedSingle>, EVEX_V512, 4651 EVEX_CD8<32, CD8VF>; 4652 4653def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1), 4654 imm:$src2, (v16f32 VR512:$src1), (i16 -1), 4655 FROUND_CURRENT)), 4656 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>; 4657 4658 4659defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512, 4660 memopv8f64, SSEPackedDouble>, EVEX_V512, 4661 VEX_W, EVEX_CD8<64, CD8VF>; 4662 4663def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1), 4664 imm:$src2, (v8f64 VR512:$src1), (i8 -1), 4665 FROUND_CURRENT)), 4666 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>; 4667 4668multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, 4669 Operand x86memop, RegisterClass RC, Domain d> { 4670let ExeDomain = d in { 4671 def r : AVX512AIi8<opc, MRMSrcReg, 4672 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3), 4673 !strconcat(OpcodeStr, 4674 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4675 []>, EVEX_4V; 4676 4677 def m : AVX512AIi8<opc, MRMSrcMem, 4678 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3), 4679 !strconcat(OpcodeStr, 4680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 4681 []>, EVEX_4V; 4682} // ExeDomain 4683} 4684 4685defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X, 4686 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>; 4687 4688defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X, 4689 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>; 4690 4691def : Pat<(ffloor FR32X:$src), 4692 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>; 4693def : Pat<(f64 (ffloor FR64X:$src)), 4694 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>; 4695def : Pat<(f32 (fnearbyint FR32X:$src)), 4696 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>; 4697def : Pat<(f64 (fnearbyint FR64X:$src)), 4698 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>; 4699def : Pat<(f32 (fceil FR32X:$src)), 4700 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>; 4701def : Pat<(f64 (fceil FR64X:$src)), 4702 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>; 4703def : Pat<(f32 (frint FR32X:$src)), 4704 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>; 4705def : Pat<(f64 (frint FR64X:$src)), 4706 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>; 4707def : Pat<(f32 (ftrunc FR32X:$src)), 4708 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>; 4709def : Pat<(f64 (ftrunc FR64X:$src)), 4710 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>; 4711 4712def : Pat<(v16f32 (ffloor VR512:$src)), 4713 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>; 4714def : Pat<(v16f32 (fnearbyint VR512:$src)), 4715 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>; 4716def : Pat<(v16f32 (fceil VR512:$src)), 4717 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>; 4718def : Pat<(v16f32 (frint VR512:$src)), 4719 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>; 4720def : Pat<(v16f32 (ftrunc VR512:$src)), 4721 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>; 4722 4723def : Pat<(v8f64 (ffloor VR512:$src)), 4724 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>; 4725def : Pat<(v8f64 (fnearbyint VR512:$src)), 4726 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>; 4727def : Pat<(v8f64 (fceil VR512:$src)), 4728 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>; 4729def : Pat<(v8f64 (frint VR512:$src)), 4730 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>; 4731def : Pat<(v8f64 (ftrunc VR512:$src)), 4732 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>; 4733 4734//------------------------------------------------- 4735// Integer truncate and extend operations 4736//------------------------------------------------- 4737 4738multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, 4739 RegisterClass dstRC, RegisterClass srcRC, 4740 RegisterClass KRC, X86MemOperand x86memop> { 4741 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst), 4742 (ins srcRC:$src), 4743 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 4744 []>, EVEX; 4745 4746 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst), 4747 (ins KRC:$mask, srcRC:$src), 4748 !strconcat(OpcodeStr, 4749 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"), 4750 []>, EVEX, EVEX_K; 4751 4752 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst), 4753 (ins KRC:$mask, srcRC:$src), 4754 !strconcat(OpcodeStr, 4755 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 4756 []>, EVEX, EVEX_KZ; 4757 4758 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src), 4759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 4760 []>, EVEX; 4761 4762 def mrk : AVX512XS8I<opc, MRMDestMem, (outs), 4763 (ins x86memop:$dst, KRC:$mask, srcRC:$src), 4764 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"), 4765 []>, EVEX, EVEX_K; 4766 4767} 4768defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM, 4769 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>; 4770defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM, 4771 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>; 4772defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM, 4773 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>; 4774defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM, 4775 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>; 4776defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM, 4777 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>; 4778defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM, 4779 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>; 4780defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM, 4781 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>; 4782defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM, 4783 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>; 4784defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM, 4785 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>; 4786defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM, 4787 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>; 4788defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM, 4789 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>; 4790defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM, 4791 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>; 4792defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM, 4793 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>; 4794defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM, 4795 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>; 4796defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM, 4797 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>; 4798 4799def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>; 4800def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>; 4801def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>; 4802def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>; 4803def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>; 4804 4805def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))), 4806 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>; 4807def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))), 4808 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>; 4809def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))), 4810 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>; 4811def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))), 4812 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>; 4813 4814 4815multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC, 4816 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode, 4817 PatFrag mem_frag, X86MemOperand x86memop, 4818 ValueType OpVT, ValueType InVT> { 4819 4820 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), 4821 (ins SrcRC:$src), 4822 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 4823 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX; 4824 4825 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), 4826 (ins KRC:$mask, SrcRC:$src), 4827 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"), 4828 []>, EVEX, EVEX_K; 4829 4830 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), 4831 (ins KRC:$mask, SrcRC:$src), 4832 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"), 4833 []>, EVEX, EVEX_KZ; 4834 4835 let mayLoad = 1 in { 4836 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), 4837 (ins x86memop:$src), 4838 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 4839 [(set DstRC:$dst, 4840 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>, 4841 EVEX; 4842 4843 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), 4844 (ins KRC:$mask, x86memop:$src), 4845 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"), 4846 []>, 4847 EVEX, EVEX_K; 4848 4849 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), 4850 (ins KRC:$mask, x86memop:$src), 4851 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"), 4852 []>, 4853 EVEX, EVEX_KZ; 4854 } 4855} 4856 4857defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext, 4858 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512, 4859 EVEX_CD8<8, CD8VQ>; 4860defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext, 4861 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512, 4862 EVEX_CD8<8, CD8VO>; 4863defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext, 4864 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512, 4865 EVEX_CD8<16, CD8VH>; 4866defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext, 4867 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512, 4868 EVEX_CD8<16, CD8VQ>; 4869defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext, 4870 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512, 4871 EVEX_CD8<32, CD8VH>; 4872 4873defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext, 4874 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512, 4875 EVEX_CD8<8, CD8VQ>; 4876defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext, 4877 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512, 4878 EVEX_CD8<8, CD8VO>; 4879defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext, 4880 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512, 4881 EVEX_CD8<16, CD8VH>; 4882defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext, 4883 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512, 4884 EVEX_CD8<16, CD8VQ>; 4885defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext, 4886 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512, 4887 EVEX_CD8<32, CD8VH>; 4888 4889//===----------------------------------------------------------------------===// 4890// GATHER - SCATTER Operations 4891 4892multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC, 4893 RegisterClass RC, X86MemOperand memop> { 4894let mayLoad = 1, 4895 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in 4896 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb), 4897 (ins RC:$src1, KRC:$mask, memop:$src2), 4898 !strconcat(OpcodeStr, 4899 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 4900 []>, EVEX, EVEX_K; 4901} 4902 4903let ExeDomain = SSEPackedDouble in { 4904defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>, 4905 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4906defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>, 4907 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4908} 4909 4910let ExeDomain = SSEPackedSingle in { 4911defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>, 4912 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4913defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>, 4914 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4915} 4916 4917defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>, 4918 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4919defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>, 4920 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4921 4922defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>, 4923 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4924defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>, 4925 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4926 4927multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC, 4928 RegisterClass RC, X86MemOperand memop> { 4929let mayStore = 1, Constraints = "$mask = $mask_wb" in 4930 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb), 4931 (ins memop:$dst, KRC:$mask, RC:$src2), 4932 !strconcat(OpcodeStr, 4933 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 4934 []>, EVEX, EVEX_K; 4935} 4936 4937let ExeDomain = SSEPackedDouble in { 4938defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>, 4939 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4940defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>, 4941 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4942} 4943 4944let ExeDomain = SSEPackedSingle in { 4945defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>, 4946 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4947defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>, 4948 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4949} 4950 4951defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>, 4952 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4953defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>, 4954 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4955 4956defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>, 4957 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4958defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>, 4959 EVEX_V512, EVEX_CD8<32, CD8VT1>; 4960 4961// prefetch 4962multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr, 4963 RegisterClass KRC, X86MemOperand memop> { 4964 let Predicates = [HasPFI], hasSideEffects = 1 in 4965 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src), 4966 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"), 4967 []>, EVEX, EVEX_K; 4968} 4969 4970defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps", 4971 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; 4972 4973defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps", 4974 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; 4975 4976defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd", 4977 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; 4978 4979defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd", 4980 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4981 4982defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps", 4983 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; 4984 4985defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps", 4986 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; 4987 4988defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd", 4989 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; 4990 4991defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd", 4992 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 4993 4994defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps", 4995 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; 4996 4997defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps", 4998 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; 4999 5000defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd", 5001 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; 5002 5003defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd", 5004 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 5005 5006defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps", 5007 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; 5008 5009defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps", 5010 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; 5011 5012defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd", 5013 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; 5014 5015defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd", 5016 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 5017//===----------------------------------------------------------------------===// 5018// VSHUFPS - VSHUFPD Operations 5019 5020multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop, 5021 ValueType vt, string OpcodeStr, PatFrag mem_frag, 5022 Domain d> { 5023 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst), 5024 (ins RC:$src1, x86memop:$src2, i8imm:$src3), 5025 !strconcat(OpcodeStr, 5026 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 5027 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2), 5028 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>, 5029 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>; 5030 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst), 5031 (ins RC:$src1, RC:$src2, i8imm:$src3), 5032 !strconcat(OpcodeStr, 5033 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 5034 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2, 5035 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>, 5036 EVEX_4V, Sched<[WriteShuffle]>; 5037} 5038 5039defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32, 5040 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 5041defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64, 5042 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 5043 5044def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))), 5045 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>; 5046def : Pat<(v16i32 (X86Shufp VR512:$src1, 5047 (memopv16i32 addr:$src2), (i8 imm:$imm))), 5048 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>; 5049 5050def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))), 5051 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>; 5052def : Pat<(v8i64 (X86Shufp VR512:$src1, 5053 (memopv8i64 addr:$src2), (i8 imm:$imm))), 5054 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>; 5055 5056multiclass avx512_valign<X86VectorVTInfo _> { 5057 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst), 5058 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3), 5059 "valign"##_.Suffix, 5060 "$src3, $src2, $src1", "$src1, $src2, $src3", 5061 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1, 5062 (i8 imm:$src3)))>, 5063 AVX512AIi8Base, EVEX_4V; 5064 5065 // Also match valign of packed floats. 5066 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))), 5067 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>; 5068 5069 let mayLoad = 1 in 5070 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst), 5071 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3), 5072 !strconcat("valign"##_.Suffix, 5073 "\t{$src3, $src2, $src1, $dst|" 5074 "$dst, $src1, $src2, $src3}"), 5075 []>, EVEX_4V; 5076} 5077defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>; 5078defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 5079 5080// Helper fragments to match sext vXi1 to vXiY. 5081def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>; 5082def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>; 5083 5084multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT, 5085 RegisterClass KRC, RegisterClass RC, 5086 X86MemOperand x86memop, X86MemOperand x86scalar_mop, 5087 string BrdcstStr> { 5088 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 5089 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 5090 []>, EVEX; 5091 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src), 5092 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), 5093 []>, EVEX, EVEX_K; 5094 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src), 5095 !strconcat(OpcodeStr, 5096 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"), 5097 []>, EVEX, EVEX_KZ; 5098 let mayLoad = 1 in { 5099 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 5100 (ins x86memop:$src), 5101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 5102 []>, EVEX; 5103 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 5104 (ins KRC:$mask, x86memop:$src), 5105 !strconcat(OpcodeStr, 5106 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), 5107 []>, EVEX, EVEX_K; 5108 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 5109 (ins KRC:$mask, x86memop:$src), 5110 !strconcat(OpcodeStr, 5111 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"), 5112 []>, EVEX, EVEX_KZ; 5113 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 5114 (ins x86scalar_mop:$src), 5115 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr, 5116 ", $dst|$dst, ${src}", BrdcstStr, "}"), 5117 []>, EVEX, EVEX_B; 5118 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 5119 (ins KRC:$mask, x86scalar_mop:$src), 5120 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr, 5121 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"), 5122 []>, EVEX, EVEX_B, EVEX_K; 5123 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 5124 (ins KRC:$mask, x86scalar_mop:$src), 5125 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr, 5126 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}", 5127 BrdcstStr, "}"), 5128 []>, EVEX, EVEX_B, EVEX_KZ; 5129 } 5130} 5131 5132defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512, 5133 i512mem, i32mem, "{1to16}">, EVEX_V512, 5134 EVEX_CD8<32, CD8VF>; 5135defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512, 5136 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W, 5137 EVEX_CD8<64, CD8VF>; 5138 5139def : Pat<(xor 5140 (bc_v16i32 (v16i1sextv16i32)), 5141 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))), 5142 (VPABSDZrr VR512:$src)>; 5143def : Pat<(xor 5144 (bc_v8i64 (v8i1sextv8i64)), 5145 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))), 5146 (VPABSQZrr VR512:$src)>; 5147 5148def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src), 5149 (v16i32 immAllZerosV), (i16 -1))), 5150 (VPABSDZrr VR512:$src)>; 5151def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src), 5152 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 5153 (VPABSQZrr VR512:$src)>; 5154 5155multiclass avx512_conflict<bits<8> opc, string OpcodeStr, 5156 RegisterClass RC, RegisterClass KRC, 5157 X86MemOperand x86memop, 5158 X86MemOperand x86scalar_mop, string BrdcstStr> { 5159 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 5160 (ins RC:$src), 5161 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"), 5162 []>, EVEX; 5163 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 5164 (ins x86memop:$src), 5165 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"), 5166 []>, EVEX; 5167 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 5168 (ins x86scalar_mop:$src), 5169 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr, 5170 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"), 5171 []>, EVEX, EVEX_B; 5172 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 5173 (ins KRC:$mask, RC:$src), 5174 !strconcat(OpcodeStr, 5175 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 5176 []>, EVEX, EVEX_KZ; 5177 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 5178 (ins KRC:$mask, x86memop:$src), 5179 !strconcat(OpcodeStr, 5180 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 5181 []>, EVEX, EVEX_KZ; 5182 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 5183 (ins KRC:$mask, x86scalar_mop:$src), 5184 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr, 5185 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}", 5186 BrdcstStr, "}"), 5187 []>, EVEX, EVEX_KZ, EVEX_B; 5188 5189 let Constraints = "$src1 = $dst" in { 5190 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 5191 (ins RC:$src1, KRC:$mask, RC:$src2), 5192 !strconcat(OpcodeStr, 5193 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 5194 []>, EVEX, EVEX_K; 5195 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 5196 (ins RC:$src1, KRC:$mask, x86memop:$src2), 5197 !strconcat(OpcodeStr, 5198 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 5199 []>, EVEX, EVEX_K; 5200 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 5201 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2), 5202 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr, 5203 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"), 5204 []>, EVEX, EVEX_K, EVEX_B; 5205 } 5206} 5207 5208let Predicates = [HasCDI] in { 5209defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM, 5210 i512mem, i32mem, "{1to16}">, 5211 EVEX_V512, EVEX_CD8<32, CD8VF>; 5212 5213 5214defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM, 5215 i512mem, i64mem, "{1to8}">, 5216 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 5217 5218} 5219 5220def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1, 5221 GR16:$mask), 5222 (VPCONFLICTDrrk VR512:$src1, 5223 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>; 5224 5225def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1, 5226 GR8:$mask), 5227 (VPCONFLICTQrrk VR512:$src1, 5228 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>; 5229 5230let Predicates = [HasCDI] in { 5231defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM, 5232 i512mem, i32mem, "{1to16}">, 5233 EVEX_V512, EVEX_CD8<32, CD8VF>; 5234 5235 5236defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM, 5237 i512mem, i64mem, "{1to8}">, 5238 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 5239 5240} 5241 5242def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1, 5243 GR16:$mask), 5244 (VPLZCNTDrrk VR512:$src1, 5245 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>; 5246 5247def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1, 5248 GR8:$mask), 5249 (VPLZCNTQrrk VR512:$src1, 5250 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>; 5251 5252def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))), 5253 (VPLZCNTDrm addr:$src)>; 5254def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))), 5255 (VPLZCNTDrr VR512:$src)>; 5256def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))), 5257 (VPLZCNTQrm addr:$src)>; 5258def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))), 5259 (VPLZCNTQrr VR512:$src)>; 5260 5261def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>; 5262def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>; 5263def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>; 5264 5265def : Pat<(store VK1:$src, addr:$dst), 5266 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>; 5267 5268def truncstorei1 : PatFrag<(ops node:$val, node:$ptr), 5269 (truncstore node:$val, node:$ptr), [{ 5270 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 5271}]>; 5272 5273def : Pat<(truncstorei1 GR8:$src, addr:$dst), 5274 (MOV8mr addr:$dst, GR8:$src)>; 5275 5276multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > { 5277def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src), 5278 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"), 5279 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX; 5280} 5281 5282multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo, 5283 string OpcodeStr, Predicate prd> { 5284let Predicates = [prd] in 5285 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512; 5286 5287 let Predicates = [prd, HasVLX] in { 5288 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256; 5289 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128; 5290 } 5291} 5292 5293multiclass avx512_convert_mask_to_vector<string OpcodeStr> { 5294 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr, 5295 HasBWI>; 5296 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr, 5297 HasBWI>, VEX_W; 5298 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr, 5299 HasDQI>; 5300 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr, 5301 HasDQI>, VEX_W; 5302} 5303 5304defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">; 5305 5306//===----------------------------------------------------------------------===// 5307// AVX-512 - COMPRESS and EXPAND 5308// 5309multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _, 5310 string OpcodeStr> { 5311 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst), 5312 (ins _.KRCWM:$mask, _.RC:$src), 5313 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}", 5314 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, 5315 _.ImmAllZerosV)))]>, EVEX_KZ; 5316 5317 let Constraints = "$src0 = $dst" in 5318 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst), 5319 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src), 5320 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}", 5321 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, 5322 _.RC:$src0)))]>, EVEX_K; 5323 5324 let mayStore = 1 in { 5325 def mrk : AVX5128I<opc, MRMDestMem, (outs), 5326 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src), 5327 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}", 5328 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)), 5329 addr:$dst)]>, 5330 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>; 5331 } 5332} 5333 5334multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr, 5335 AVX512VLVectorVTInfo VTInfo> { 5336 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512; 5337 5338 let Predicates = [HasVLX] in { 5339 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256; 5340 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128; 5341 } 5342} 5343 5344defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>, 5345 EVEX; 5346defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>, 5347 EVEX, VEX_W; 5348defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>, 5349 EVEX; 5350defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>, 5351 EVEX, VEX_W; 5352 5353// expand 5354multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _, 5355 string OpcodeStr> { 5356 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst), 5357 (ins _.KRCWM:$mask, _.RC:$src), 5358 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}", 5359 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src), 5360 _.ImmAllZerosV)))]>, EVEX_KZ; 5361 5362 let Constraints = "$src0 = $dst" in 5363 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst), 5364 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src), 5365 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}", 5366 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, 5367 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K; 5368 5369 let mayLoad = 1, Constraints = "$src0 = $dst" in 5370 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst), 5371 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src), 5372 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}", 5373 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, 5374 (_.VT (bitconvert 5375 (_.LdFrag addr:$src))), 5376 _.RC:$src0)))]>, 5377 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>; 5378 5379 let mayLoad = 1 in 5380 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst), 5381 (ins _.KRCWM:$mask, _.MemOp:$src), 5382 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}", 5383 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, 5384 (_.VT (bitconvert (_.LdFrag addr:$src))), 5385 _.ImmAllZerosV)))]>, 5386 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>; 5387 5388} 5389 5390multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr, 5391 AVX512VLVectorVTInfo VTInfo> { 5392 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512; 5393 5394 let Predicates = [HasVLX] in { 5395 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256; 5396 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128; 5397 } 5398} 5399 5400defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>, 5401 EVEX; 5402defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>, 5403 EVEX, VEX_W; 5404defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>, 5405 EVEX; 5406defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>, 5407 EVEX, VEX_W; 5408