1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue()); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue()); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), 47 "#ADJCALLSTACKDOWN", 48 [(X86callseq_start timm:$amt)]>, 49 Requires<[NotLP64]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[NotLP64]>; 54} 55 56// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 57// a stack adjustment and the codegen must know that they may modify the stack 58// pointer before prolog-epilog rewriting occurs. 59// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 60// sub / add which can clobber EFLAGS. 61let Defs = [RSP, EFLAGS], Uses = [RSP] in { 62def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt), 63 "#ADJCALLSTACKDOWN", 64 [(X86callseq_start timm:$amt)]>, 65 Requires<[IsLP64]>; 66def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 67 "#ADJCALLSTACKUP", 68 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 69 Requires<[IsLP64]>; 70} 71 72 73 74// x86-64 va_start lowering magic. 75let usesCustomInserter = 1, Defs = [EFLAGS] in { 76def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 77 (outs), 78 (ins GR8:$al, 79 i64imm:$regsavefi, i64imm:$offset, 80 variable_ops), 81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 82 [(X86vastart_save_xmm_regs GR8:$al, 83 imm:$regsavefi, 84 imm:$offset), 85 (implicit EFLAGS)]>; 86 87// The VAARG_64 pseudo-instruction takes the address of the va_list, 88// and places the address of the next argument into a register. 89let Defs = [EFLAGS] in 90def VAARG_64 : I<0, Pseudo, 91 (outs GR64:$dst), 92 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 93 "#VAARG_64 $dst, $ap, $size, $mode, $align", 94 [(set GR64:$dst, 95 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 96 (implicit EFLAGS)]>; 97 98// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 99// targets. These calls are needed to probe the stack when allocating more than 100// 4k bytes in one go. Touching the stack at 4K increments is necessary to 101// ensure that the guard pages used by the OS virtual memory manager are 102// allocated in correct sequence. 103// The main point of having separate instruction are extra unmodelled effects 104// (compared to ordinary calls) like stack pointer change. 105 106let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 107 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 108 "# dynamic stack allocation", 109 [(X86WinAlloca)]>; 110 111// When using segmented stacks these are lowered into instructions which first 112// check if the current stacklet has enough free memory. If it does, memory is 113// allocated by bumping the stack pointer. Otherwise memory is allocated from 114// the heap. 115 116let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 117def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 118 "# variable sized alloca for segmented stacks", 119 [(set GR32:$dst, 120 (X86SegAlloca GR32:$size))]>, 121 Requires<[NotLP64]>; 122 123let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 124def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 125 "# variable sized alloca for segmented stacks", 126 [(set GR64:$dst, 127 (X86SegAlloca GR64:$size))]>, 128 Requires<[In64BitMode]>; 129} 130 131// The MSVC runtime contains an _ftol2 routine for converting floating-point 132// to integer values. It has a strange calling convention: the input is 133// popped from the x87 stack, and the return value is given in EDX:EAX. ECX is 134// used as a temporary register. No other registers (aside from flags) are 135// touched. 136// Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80 137// variant is unnecessary. 138 139let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in { 140 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src), 141 "# win32 fptoui", 142 [(X86WinFTOL RFP32:$src)]>, 143 Requires<[Not64BitMode]>; 144 145 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src), 146 "# win32 fptoui", 147 [(X86WinFTOL RFP64:$src)]>, 148 Requires<[Not64BitMode]>; 149} 150 151//===----------------------------------------------------------------------===// 152// EH Pseudo Instructions 153// 154let SchedRW = [WriteSystem] in { 155let isTerminator = 1, isReturn = 1, isBarrier = 1, 156 hasCtrlDep = 1, isCodeGenOnly = 1 in { 157def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 158 "ret\t#eh_return, addr: $addr", 159 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 160 161} 162 163let isTerminator = 1, isReturn = 1, isBarrier = 1, 164 hasCtrlDep = 1, isCodeGenOnly = 1 in { 165def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 166 "ret\t#eh_return, addr: $addr", 167 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 168 169} 170 171let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 172 usesCustomInserter = 1 in { 173 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 174 "#EH_SJLJ_SETJMP32", 175 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 176 Requires<[Not64BitMode]>; 177 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 178 "#EH_SJLJ_SETJMP64", 179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 180 Requires<[In64BitMode]>; 181 let isTerminator = 1 in { 182 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 183 "#EH_SJLJ_LONGJMP32", 184 [(X86eh_sjlj_longjmp addr:$buf)]>, 185 Requires<[Not64BitMode]>; 186 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 187 "#EH_SJLJ_LONGJMP64", 188 [(X86eh_sjlj_longjmp addr:$buf)]>, 189 Requires<[In64BitMode]>; 190 } 191} 192} // SchedRW 193 194let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 195 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 196 "#EH_SjLj_Setup\t$dst", []>; 197} 198 199//===----------------------------------------------------------------------===// 200// Pseudo instructions used by unwind info. 201// 202let isPseudo = 1 in { 203 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 204 "#SEH_PushReg $reg", []>; 205 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 206 "#SEH_SaveReg $reg, $dst", []>; 207 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 208 "#SEH_SaveXMM $reg, $dst", []>; 209 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 210 "#SEH_StackAlloc $size", []>; 211 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 212 "#SEH_SetFrame $reg, $offset", []>; 213 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 214 "#SEH_PushFrame $mode", []>; 215 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 216 "#SEH_EndPrologue", []>; 217 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 218 "#SEH_Epilogue", []>; 219} 220 221//===----------------------------------------------------------------------===// 222// Pseudo instructions used by segmented stacks. 223// 224 225// This is lowered into a RET instruction by MCInstLower. We need 226// this so that we don't have to have a MachineBasicBlock which ends 227// with a RET and also has successors. 228let isPseudo = 1 in { 229def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 230 "", []>; 231 232// This instruction is lowered to a RET followed by a MOV. The two 233// instructions are not generated on a higher level since then the 234// verifier sees a MachineBasicBlock ending with a non-terminator. 235def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 236 "", []>; 237} 238 239//===----------------------------------------------------------------------===// 240// Alias Instructions 241//===----------------------------------------------------------------------===// 242 243// Alias instruction mapping movr0 to xor. 244// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 245let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 246 isPseudo = 1 in 247def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 248 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>; 249 250// Other widths can also make use of the 32-bit xor, which may have a smaller 251// encoding and avoid partial register updates. 252def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 253def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 254def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> { 255 let AddedComplexity = 20; 256} 257 258// Materialize i64 constant where top 32-bits are zero. This could theoretically 259// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 260// that would make it more difficult to rematerialize. 261let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 262 isCodeGenOnly = 1, hasSideEffects = 0 in 263def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src), 264 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>; 265 266// This 64-bit pseudo-move can be used for both a 64-bit constant that is 267// actually the zero-extension of a 32-bit constant, and for labels in the 268// x86-64 small code model. 269def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>; 270 271let AddedComplexity = 1 in 272def : Pat<(i64 mov64imm32:$src), 273 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; 274 275// Use sbb to materialize carry bit. 276let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { 277// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 278// However, Pat<> can't replicate the destination reg into the inputs of the 279// result. 280def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 281 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 282def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 283 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 284def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 285 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 286def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 287 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 288} // isCodeGenOnly 289 290 291def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 292 (SETB_C16r)>; 293def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 294 (SETB_C32r)>; 295def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 296 (SETB_C64r)>; 297 298def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 299 (SETB_C16r)>; 300def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 301 (SETB_C32r)>; 302def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 303 (SETB_C64r)>; 304 305// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 306// will be eliminated and that the sbb can be extended up to a wider type. When 307// this happens, it is great. However, if we are left with an 8-bit sbb and an 308// and, we might as well just match it as a setb. 309def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 310 (SETBr)>; 311 312// (add OP, SETB) -> (adc OP, 0) 313def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 314 (ADC8ri GR8:$op, 0)>; 315def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 316 (ADC32ri8 GR32:$op, 0)>; 317def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 318 (ADC64ri8 GR64:$op, 0)>; 319 320// (sub OP, SETB) -> (sbb OP, 0) 321def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 322 (SBB8ri GR8:$op, 0)>; 323def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 324 (SBB32ri8 GR32:$op, 0)>; 325def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 326 (SBB64ri8 GR64:$op, 0)>; 327 328// (sub OP, SETCC_CARRY) -> (adc OP, 0) 329def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 330 (ADC8ri GR8:$op, 0)>; 331def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 332 (ADC32ri8 GR32:$op, 0)>; 333def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 334 (ADC64ri8 GR64:$op, 0)>; 335 336//===----------------------------------------------------------------------===// 337// String Pseudo Instructions 338// 339let SchedRW = [WriteMicrocoded] in { 340let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 341def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 342 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 343 Requires<[Not64BitMode]>; 344def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 345 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 346 Requires<[Not64BitMode]>; 347def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 348 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 349 Requires<[Not64BitMode]>; 350} 351 352let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 353def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 354 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 355 Requires<[In64BitMode]>; 356def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 357 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 358 Requires<[In64BitMode]>; 359def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 360 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 361 Requires<[In64BitMode]>; 362def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 363 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 364 Requires<[In64BitMode]>; 365} 366 367// FIXME: Should use "(X86rep_stos AL)" as the pattern. 368let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 369 let Uses = [AL,ECX,EDI] in 370 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 371 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 372 Requires<[Not64BitMode]>; 373 let Uses = [AX,ECX,EDI] in 374 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 375 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 376 Requires<[Not64BitMode]>; 377 let Uses = [EAX,ECX,EDI] in 378 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 379 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 380 Requires<[Not64BitMode]>; 381} 382 383let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 384 let Uses = [AL,RCX,RDI] in 385 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 386 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 387 Requires<[In64BitMode]>; 388 let Uses = [AX,RCX,RDI] in 389 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 390 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 391 Requires<[In64BitMode]>; 392 let Uses = [RAX,RCX,RDI] in 393 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 394 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 395 Requires<[In64BitMode]>; 396 397 let Uses = [RAX,RCX,RDI] in 398 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 399 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 400 Requires<[In64BitMode]>; 401} 402} // SchedRW 403 404//===----------------------------------------------------------------------===// 405// Thread Local Storage Instructions 406// 407 408// ELF TLS Support 409// All calls clobber the non-callee saved registers. ESP is marked as 410// a use to prevent stack-pointer assignments that appear immediately 411// before calls from potentially appearing dead. 412let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 413 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 414 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 415 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 416 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 417 Uses = [ESP] in { 418def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 419 "# TLS_addr32", 420 [(X86tlsaddr tls32addr:$sym)]>, 421 Requires<[Not64BitMode]>; 422def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 423 "# TLS_base_addr32", 424 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 425 Requires<[Not64BitMode]>; 426} 427 428// All calls clobber the non-callee saved registers. RSP is marked as 429// a use to prevent stack-pointer assignments that appear immediately 430// before calls from potentially appearing dead. 431let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 432 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 433 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 434 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 435 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 436 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 437 Uses = [RSP] in { 438def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 439 "# TLS_addr64", 440 [(X86tlsaddr tls64addr:$sym)]>, 441 Requires<[In64BitMode]>; 442def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 443 "# TLS_base_addr64", 444 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 445 Requires<[In64BitMode]>; 446} 447 448// Darwin TLS Support 449// For i386, the address of the thunk is passed on the stack, on return the 450// address of the variable is in %eax. %ecx is trashed during the function 451// call. All other registers are preserved. 452let Defs = [EAX, ECX, EFLAGS], 453 Uses = [ESP], 454 usesCustomInserter = 1 in 455def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 456 "# TLSCall_32", 457 [(X86TLSCall addr:$sym)]>, 458 Requires<[Not64BitMode]>; 459 460// For x86_64, the address of the thunk is passed in %rdi, on return 461// the address of the variable is in %rax. All other registers are preserved. 462let Defs = [RAX, EFLAGS], 463 Uses = [RSP, RDI], 464 usesCustomInserter = 1 in 465def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 466 "# TLSCall_64", 467 [(X86TLSCall addr:$sym)]>, 468 Requires<[In64BitMode]>; 469 470 471//===----------------------------------------------------------------------===// 472// Conditional Move Pseudo Instructions 473 474// X86 doesn't have 8-bit conditional moves. Use a customInserter to 475// emit control flow. An alternative to this is to mark i8 SELECT as Promote, 476// however that requires promoting the operands, and can induce additional 477// i8 register pressure. 478let usesCustomInserter = 1, Uses = [EFLAGS] in { 479def CMOV_GR8 : I<0, Pseudo, 480 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), 481 "#CMOV_GR8 PSEUDO!", 482 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, 483 imm:$cond, EFLAGS))]>; 484 485let Predicates = [NoCMov] in { 486def CMOV_GR32 : I<0, Pseudo, 487 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond), 488 "#CMOV_GR32* PSEUDO!", 489 [(set GR32:$dst, 490 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>; 491def CMOV_GR16 : I<0, Pseudo, 492 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond), 493 "#CMOV_GR16* PSEUDO!", 494 [(set GR16:$dst, 495 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>; 496} // Predicates = [NoCMov] 497 498// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 499// SSE1. 500let Predicates = [FPStackf32] in 501def CMOV_RFP32 : I<0, Pseudo, 502 (outs RFP32:$dst), 503 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond), 504 "#CMOV_RFP32 PSEUDO!", 505 [(set RFP32:$dst, 506 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond, 507 EFLAGS))]>; 508// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 509// SSE2. 510let Predicates = [FPStackf64] in 511def CMOV_RFP64 : I<0, Pseudo, 512 (outs RFP64:$dst), 513 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond), 514 "#CMOV_RFP64 PSEUDO!", 515 [(set RFP64:$dst, 516 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond, 517 EFLAGS))]>; 518def CMOV_RFP80 : I<0, Pseudo, 519 (outs RFP80:$dst), 520 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond), 521 "#CMOV_RFP80 PSEUDO!", 522 [(set RFP80:$dst, 523 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond, 524 EFLAGS))]>; 525} // UsesCustomInserter = 1, Uses = [EFLAGS] 526 527 528//===----------------------------------------------------------------------===// 529// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 530//===----------------------------------------------------------------------===// 531 532// FIXME: Use normal instructions and add lock prefix dynamically. 533 534// Memory barriers 535 536// TODO: Get this to fold the constant into the instruction. 537let isCodeGenOnly = 1, Defs = [EFLAGS] in 538def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 539 "or{l}\t{$zero, $dst|$dst, $zero}", 540 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK, 541 Sched<[WriteALULd, WriteRMW]>; 542 543let hasSideEffects = 1 in 544def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 545 "#MEMBARRIER", 546 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 547 548// RegOpc corresponds to the mr version of the instruction 549// ImmOpc corresponds to the mi version of the instruction 550// ImmOpc8 corresponds to the mi8 version of the instruction 551// ImmMod corresponds to the instruction format of the mi and mi8 versions 552multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 553 Format ImmMod, string mnemonic> { 554let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 555 SchedRW = [WriteALULd, WriteRMW] in { 556 557def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 558 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 559 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 560 !strconcat(mnemonic, "{b}\t", 561 "{$src2, $dst|$dst, $src2}"), 562 [], IIC_ALU_NONMEM>, LOCK; 563def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 564 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 565 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 566 !strconcat(mnemonic, "{w}\t", 567 "{$src2, $dst|$dst, $src2}"), 568 [], IIC_ALU_NONMEM>, OpSize16, LOCK; 569def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 570 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 571 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 572 !strconcat(mnemonic, "{l}\t", 573 "{$src2, $dst|$dst, $src2}"), 574 [], IIC_ALU_NONMEM>, OpSize32, LOCK; 575def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 576 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 577 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 578 !strconcat(mnemonic, "{q}\t", 579 "{$src2, $dst|$dst, $src2}"), 580 [], IIC_ALU_NONMEM>, LOCK; 581 582def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 583 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 584 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 585 !strconcat(mnemonic, "{b}\t", 586 "{$src2, $dst|$dst, $src2}"), 587 [], IIC_ALU_MEM>, LOCK; 588 589def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 590 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 591 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 592 !strconcat(mnemonic, "{w}\t", 593 "{$src2, $dst|$dst, $src2}"), 594 [], IIC_ALU_MEM>, OpSize16, LOCK; 595 596def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 597 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 598 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 599 !strconcat(mnemonic, "{l}\t", 600 "{$src2, $dst|$dst, $src2}"), 601 [], IIC_ALU_MEM>, OpSize32, LOCK; 602 603def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 604 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 605 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 606 !strconcat(mnemonic, "{q}\t", 607 "{$src2, $dst|$dst, $src2}"), 608 [], IIC_ALU_MEM>, LOCK; 609 610def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 611 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 612 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 613 !strconcat(mnemonic, "{w}\t", 614 "{$src2, $dst|$dst, $src2}"), 615 [], IIC_ALU_MEM>, OpSize16, LOCK; 616def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 617 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 618 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 619 !strconcat(mnemonic, "{l}\t", 620 "{$src2, $dst|$dst, $src2}"), 621 [], IIC_ALU_MEM>, OpSize32, LOCK; 622def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 623 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 624 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 625 !strconcat(mnemonic, "{q}\t", 626 "{$src2, $dst|$dst, $src2}"), 627 [], IIC_ALU_MEM>, LOCK; 628 629} 630 631} 632 633defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; 634defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; 635defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; 636defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">; 637defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">; 638 639// Optimized codegen when the non-memory output is not used. 640multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 641 string mnemonic> { 642let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 643 SchedRW = [WriteALULd, WriteRMW] in { 644 645def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 646 !strconcat(mnemonic, "{b}\t$dst"), 647 [], IIC_UNARY_MEM>, LOCK; 648def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 649 !strconcat(mnemonic, "{w}\t$dst"), 650 [], IIC_UNARY_MEM>, OpSize16, LOCK; 651def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 652 !strconcat(mnemonic, "{l}\t$dst"), 653 [], IIC_UNARY_MEM>, OpSize32, LOCK; 654def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 655 !strconcat(mnemonic, "{q}\t$dst"), 656 [], IIC_UNARY_MEM>, LOCK; 657} 658} 659 660defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">; 661defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">; 662 663// Atomic compare and swap. 664multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 665 SDPatternOperator frag, X86MemOperand x86memop, 666 InstrItinClass itin> { 667let isCodeGenOnly = 1 in { 668 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 669 !strconcat(mnemonic, "\t$ptr"), 670 [(frag addr:$ptr)], itin>, TB, LOCK; 671} 672} 673 674multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 675 string mnemonic, SDPatternOperator frag, 676 InstrItinClass itin8, InstrItinClass itin> { 677let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { 678 let Defs = [AL, EFLAGS], Uses = [AL] in 679 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 680 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 681 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 682 let Defs = [AX, EFLAGS], Uses = [AX] in 683 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 684 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 685 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK; 686 let Defs = [EAX, EFLAGS], Uses = [EAX] in 687 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 688 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 689 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK; 690 let Defs = [RAX, EFLAGS], Uses = [RAX] in 691 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 692 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 693 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 694} 695} 696 697let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 698 SchedRW = [WriteALULd, WriteRMW] in { 699defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 700 X86cas8, i64mem, 701 IIC_CMPX_LOCK_8B>; 702} 703 704let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 705 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { 706defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 707 X86cas16, i128mem, 708 IIC_CMPX_LOCK_16B>, REX_W; 709} 710 711defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 712 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 713 714// Atomic exchange and add 715multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 716 string frag, 717 InstrItinClass itin8, InstrItinClass itin> { 718 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, 719 SchedRW = [WriteALULd, WriteRMW] in { 720 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 721 (ins GR8:$val, i8mem:$ptr), 722 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 723 [(set GR8:$dst, 724 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 725 itin8>; 726 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 727 (ins GR16:$val, i16mem:$ptr), 728 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 729 [(set 730 GR16:$dst, 731 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 732 itin>, OpSize16; 733 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 734 (ins GR32:$val, i32mem:$ptr), 735 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 736 [(set 737 GR32:$dst, 738 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 739 itin>, OpSize32; 740 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 741 (ins GR64:$val, i64mem:$ptr), 742 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 743 [(set 744 GR64:$dst, 745 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 746 itin>; 747 } 748} 749 750defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 751 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 752 TB, LOCK; 753 754/* The following multiclass tries to make sure that in code like 755 * x.store (immediate op x.load(acquire), release) 756 * an operation directly on memory is generated instead of wasting a register. 757 * It is not automatic as atomic_store/load are only lowered to MOV instructions 758 * extremely late to prevent them from being accidentally reordered in the backend 759 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 760 */ 761multiclass RELEASE_BINOP_MI<string op> { 762 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 763 "#RELEASE_BINOP PSEUDO!", 764 [(atomic_store_8 addr:$dst, (!cast<PatFrag>(op) 765 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>; 766 // NAME#16 is not generated as 16-bit arithmetic instructions are considered 767 // costly and avoided as far as possible by this backend anyway 768 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 769 "#RELEASE_BINOP PSEUDO!", 770 [(atomic_store_32 addr:$dst, (!cast<PatFrag>(op) 771 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>; 772 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 773 "#RELEASE_BINOP PSEUDO!", 774 [(atomic_store_64 addr:$dst, (!cast<PatFrag>(op) 775 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>; 776} 777defm RELEASE_ADD : RELEASE_BINOP_MI<"add">; 778defm RELEASE_AND : RELEASE_BINOP_MI<"and">; 779defm RELEASE_OR : RELEASE_BINOP_MI<"or">; 780defm RELEASE_XOR : RELEASE_BINOP_MI<"xor">; 781// Note: we don't deal with sub, because substractions of constants are 782// optimized into additions before this code can run 783 784multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> { 785 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst), 786 "#RELEASE_UNOP PSEUDO!", 787 [(atomic_store_8 addr:$dst, dag8)]>; 788 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst), 789 "#RELEASE_UNOP PSEUDO!", 790 [(atomic_store_16 addr:$dst, dag16)]>; 791 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst), 792 "#RELEASE_UNOP PSEUDO!", 793 [(atomic_store_32 addr:$dst, dag32)]>; 794 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst), 795 "#RELEASE_UNOP PSEUDO!", 796 [(atomic_store_64 addr:$dst, dag64)]>; 797} 798 799defm RELEASE_INC : RELEASE_UNOP< 800 (add (atomic_load_8 addr:$dst), (i8 1)), 801 (add (atomic_load_16 addr:$dst), (i16 1)), 802 (add (atomic_load_32 addr:$dst), (i32 1)), 803 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>; 804defm RELEASE_DEC : RELEASE_UNOP< 805 (add (atomic_load_8 addr:$dst), (i8 -1)), 806 (add (atomic_load_16 addr:$dst), (i16 -1)), 807 (add (atomic_load_32 addr:$dst), (i32 -1)), 808 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>; 809/* 810TODO: These don't work because the type inference of TableGen fails. 811TODO: find a way to fix it. 812defm RELEASE_NEG : RELEASE_UNOP< 813 (ineg (atomic_load_8 addr:$dst)), 814 (ineg (atomic_load_16 addr:$dst)), 815 (ineg (atomic_load_32 addr:$dst)), 816 (ineg (atomic_load_64 addr:$dst))>; 817defm RELEASE_NOT : RELEASE_UNOP< 818 (not (atomic_load_8 addr:$dst)), 819 (not (atomic_load_16 addr:$dst)), 820 (not (atomic_load_32 addr:$dst)), 821 (not (atomic_load_64 addr:$dst))>; 822*/ 823 824def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 825 "#RELEASE_MOV PSEUDO !", 826 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>; 827def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src), 828 "#RELEASE_MOV PSEUDO !", 829 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>; 830def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 831 "#RELEASE_MOV PSEUDO !", 832 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>; 833def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 834 "#RELEASE_MOV PSEUDO !", 835 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>; 836 837def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 838 "#RELEASE_MOV PSEUDO!", 839 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 840def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 841 "#RELEASE_MOV PSEUDO!", 842 [(atomic_store_16 addr:$dst, GR16:$src)]>; 843def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 844 "#RELEASE_MOV PSEUDO!", 845 [(atomic_store_32 addr:$dst, GR32:$src)]>; 846def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 847 "#RELEASE_MOV PSEUDO!", 848 [(atomic_store_64 addr:$dst, GR64:$src)]>; 849 850def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 851 "#ACQUIRE_MOV PSEUDO!", 852 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 853def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 854 "#ACQUIRE_MOV PSEUDO!", 855 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 856def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 857 "#ACQUIRE_MOV PSEUDO!", 858 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 859def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 860 "#ACQUIRE_MOV PSEUDO!", 861 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 862//===----------------------------------------------------------------------===// 863// Conditional Move Pseudo Instructions. 864//===----------------------------------------------------------------------===// 865 866// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after 867// instruction selection into a branch sequence. 868let Uses = [EFLAGS], usesCustomInserter = 1 in { 869 def CMOV_FR32 : I<0, Pseudo, 870 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), 871 "#CMOV_FR32 PSEUDO!", 872 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond, 873 EFLAGS))]>; 874 def CMOV_FR64 : I<0, Pseudo, 875 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), 876 "#CMOV_FR64 PSEUDO!", 877 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond, 878 EFLAGS))]>; 879 def CMOV_V4F32 : I<0, Pseudo, 880 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 881 "#CMOV_V4F32 PSEUDO!", 882 [(set VR128:$dst, 883 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, 884 EFLAGS)))]>; 885 def CMOV_V2F64 : I<0, Pseudo, 886 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 887 "#CMOV_V2F64 PSEUDO!", 888 [(set VR128:$dst, 889 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 890 EFLAGS)))]>; 891 def CMOV_V2I64 : I<0, Pseudo, 892 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 893 "#CMOV_V2I64 PSEUDO!", 894 [(set VR128:$dst, 895 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 896 EFLAGS)))]>; 897 def CMOV_V8F32 : I<0, Pseudo, 898 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 899 "#CMOV_V8F32 PSEUDO!", 900 [(set VR256:$dst, 901 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, 902 EFLAGS)))]>; 903 def CMOV_V4F64 : I<0, Pseudo, 904 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 905 "#CMOV_V4F64 PSEUDO!", 906 [(set VR256:$dst, 907 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 908 EFLAGS)))]>; 909 def CMOV_V4I64 : I<0, Pseudo, 910 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 911 "#CMOV_V4I64 PSEUDO!", 912 [(set VR256:$dst, 913 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 914 EFLAGS)))]>; 915 def CMOV_V8I64 : I<0, Pseudo, 916 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond), 917 "#CMOV_V8I64 PSEUDO!", 918 [(set VR512:$dst, 919 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond, 920 EFLAGS)))]>; 921 def CMOV_V8F64 : I<0, Pseudo, 922 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond), 923 "#CMOV_V8F64 PSEUDO!", 924 [(set VR512:$dst, 925 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond, 926 EFLAGS)))]>; 927 def CMOV_V16F32 : I<0, Pseudo, 928 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond), 929 "#CMOV_V16F32 PSEUDO!", 930 [(set VR512:$dst, 931 (v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond, 932 EFLAGS)))]>; 933} 934 935 936//===----------------------------------------------------------------------===// 937// DAG Pattern Matching Rules 938//===----------------------------------------------------------------------===// 939 940// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 941def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 942def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 943def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 944def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 945def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 946def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 947 948def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 949 (ADD32ri GR32:$src1, tconstpool:$src2)>; 950def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 951 (ADD32ri GR32:$src1, tjumptable:$src2)>; 952def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 953 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 954def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 955 (ADD32ri GR32:$src1, texternalsym:$src2)>; 956def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 957 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 958 959def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 960 (MOV32mi addr:$dst, tglobaladdr:$src)>; 961def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 962 (MOV32mi addr:$dst, texternalsym:$src)>; 963def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 964 (MOV32mi addr:$dst, tblockaddress:$src)>; 965 966// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 967// code model mode, should use 'movabs'. FIXME: This is really a hack, the 968// 'movabs' predicate should handle this sort of thing. 969def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 970 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 971def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 972 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 973def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 974 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 975def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 976 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 977def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 978 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 979 980// In kernel code model, we can get the address of a label 981// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 982// the MOV64ri32 should accept these. 983def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 984 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 985def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 986 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 987def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 988 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 989def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 990 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 991def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 992 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 993 994// If we have small model and -static mode, it is safe to store global addresses 995// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 996// for MOV64mi32 should handle this sort of thing. 997def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 998 (MOV64mi32 addr:$dst, tconstpool:$src)>, 999 Requires<[NearData, IsStatic]>; 1000def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1001 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1002 Requires<[NearData, IsStatic]>; 1003def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1004 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1005 Requires<[NearData, IsStatic]>; 1006def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1007 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1008 Requires<[NearData, IsStatic]>; 1009def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1010 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1011 Requires<[NearData, IsStatic]>; 1012 1013def : Pat<(i32 (X86RecoverFrameAlloc texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 1014def : Pat<(i64 (X86RecoverFrameAlloc texternalsym:$dst)), (MOV64ri texternalsym:$dst)>; 1015 1016// Calls 1017 1018// tls has some funny stuff here... 1019// This corresponds to movabs $foo@tpoff, %rax 1020def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1021 (MOV64ri32 tglobaltlsaddr :$dst)>; 1022// This corresponds to add $foo@tpoff, %rax 1023def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1024 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1025 1026 1027// Direct PC relative function call for small code model. 32-bit displacement 1028// sign extended to 64-bit. 1029def : Pat<(X86call (i64 tglobaladdr:$dst)), 1030 (CALL64pcrel32 tglobaladdr:$dst)>; 1031def : Pat<(X86call (i64 texternalsym:$dst)), 1032 (CALL64pcrel32 texternalsym:$dst)>; 1033 1034// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1035// can never use callee-saved registers. That is the purpose of the GR64_TC 1036// register classes. 1037// 1038// The only volatile register that is never used by the calling convention is 1039// %r11. This happens when calling a vararg function with 6 arguments. 1040// 1041// Match an X86tcret that uses less than 7 volatile registers. 1042def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1043 (X86tcret node:$ptr, node:$off), [{ 1044 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1045 unsigned NumRegs = 0; 1046 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1047 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1048 return false; 1049 return true; 1050}]>; 1051 1052def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1053 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1054 Requires<[Not64BitMode]>; 1055 1056// FIXME: This is disabled for 32-bit PIC mode because the global base 1057// register which is part of the address mode may be assigned a 1058// callee-saved register. 1059def : Pat<(X86tcret (load addr:$dst), imm:$off), 1060 (TCRETURNmi addr:$dst, imm:$off)>, 1061 Requires<[Not64BitMode, IsNotPIC]>; 1062 1063def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1064 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1065 Requires<[Not64BitMode]>; 1066 1067def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1068 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1069 Requires<[Not64BitMode]>; 1070 1071def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1072 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1073 Requires<[In64BitMode]>; 1074 1075// Don't fold loads into X86tcret requiring more than 6 regs. 1076// There wouldn't be enough scratch registers for base+index. 1077def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1078 (TCRETURNmi64 addr:$dst, imm:$off)>, 1079 Requires<[In64BitMode]>; 1080 1081def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1082 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1083 Requires<[In64BitMode]>; 1084 1085def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1086 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1087 Requires<[In64BitMode]>; 1088 1089// Normal calls, with various flavors of addresses. 1090def : Pat<(X86call (i32 tglobaladdr:$dst)), 1091 (CALLpcrel32 tglobaladdr:$dst)>; 1092def : Pat<(X86call (i32 texternalsym:$dst)), 1093 (CALLpcrel32 texternalsym:$dst)>; 1094def : Pat<(X86call (i32 imm:$dst)), 1095 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1096 1097// Comparisons. 1098 1099// TEST R,R is smaller than CMP R,0 1100def : Pat<(X86cmp GR8:$src1, 0), 1101 (TEST8rr GR8:$src1, GR8:$src1)>; 1102def : Pat<(X86cmp GR16:$src1, 0), 1103 (TEST16rr GR16:$src1, GR16:$src1)>; 1104def : Pat<(X86cmp GR32:$src1, 0), 1105 (TEST32rr GR32:$src1, GR32:$src1)>; 1106def : Pat<(X86cmp GR64:$src1, 0), 1107 (TEST64rr GR64:$src1, GR64:$src1)>; 1108 1109// Conditional moves with folded loads with operands swapped and conditions 1110// inverted. 1111multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1112 Instruction Inst64> { 1113 let Predicates = [HasCMov] in { 1114 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1115 (Inst16 GR16:$src2, addr:$src1)>; 1116 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1117 (Inst32 GR32:$src2, addr:$src1)>; 1118 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1119 (Inst64 GR64:$src2, addr:$src1)>; 1120 } 1121} 1122 1123defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1124defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1125defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1126defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1127defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1128defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1129defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1130defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1131defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1132defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1133defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1134defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1135defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1136defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1137defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1138defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1139 1140// zextload bool -> zextload byte 1141def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1142def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1143def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1144def : Pat<(zextloadi64i1 addr:$src), 1145 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1146 1147// extload bool -> extload byte 1148// When extloading from 16-bit and smaller memory locations into 64-bit 1149// registers, use zero-extending loads so that the entire 64-bit register is 1150// defined, avoiding partial-register updates. 1151 1152def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1153def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1154def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1155def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1156def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1157def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1158 1159// For other extloads, use subregs, since the high contents of the register are 1160// defined after an extload. 1161def : Pat<(extloadi64i1 addr:$src), 1162 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1163def : Pat<(extloadi64i8 addr:$src), 1164 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1165def : Pat<(extloadi64i16 addr:$src), 1166 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1167def : Pat<(extloadi64i32 addr:$src), 1168 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1169 1170// anyext. Define these to do an explicit zero-extend to 1171// avoid partial-register updates. 1172def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1173 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1174def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1175 1176// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1177def : Pat<(i32 (anyext GR16:$src)), 1178 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1179 1180def : Pat<(i64 (anyext GR8 :$src)), 1181 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1182def : Pat<(i64 (anyext GR16:$src)), 1183 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1184def : Pat<(i64 (anyext GR32:$src)), 1185 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1186 1187 1188// Any instruction that defines a 32-bit result leaves the high half of the 1189// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1190// be copying from a truncate. And x86's cmov doesn't do anything if the 1191// condition is false. But any other 32-bit operation will zero-extend 1192// up to 64 bits. 1193def def32 : PatLeaf<(i32 GR32:$src), [{ 1194 return N->getOpcode() != ISD::TRUNCATE && 1195 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1196 N->getOpcode() != ISD::CopyFromReg && 1197 N->getOpcode() != ISD::AssertSext && 1198 N->getOpcode() != X86ISD::CMOV; 1199}]>; 1200 1201// In the case of a 32-bit def that is known to implicitly zero-extend, 1202// we can use a SUBREG_TO_REG. 1203def : Pat<(i64 (zext def32:$src)), 1204 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1205 1206//===----------------------------------------------------------------------===// 1207// Pattern match OR as ADD 1208//===----------------------------------------------------------------------===// 1209 1210// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1211// 3-addressified into an LEA instruction to avoid copies. However, we also 1212// want to finally emit these instructions as an or at the end of the code 1213// generator to make the generated code easier to read. To do this, we select 1214// into "disjoint bits" pseudo ops. 1215 1216// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1217def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1218 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1219 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1220 1221 APInt KnownZero0, KnownOne0; 1222 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1223 APInt KnownZero1, KnownOne1; 1224 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1225 return (~KnownZero0 & ~KnownZero1) == 0; 1226}]>; 1227 1228 1229// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1230// Try this before the selecting to OR. 1231let AddedComplexity = 5, SchedRW = [WriteALU] in { 1232 1233let isConvertibleToThreeAddress = 1, 1234 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1235let isCommutable = 1 in { 1236def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1237 "", // orw/addw REG, REG 1238 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1239def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1240 "", // orl/addl REG, REG 1241 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1242def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1243 "", // orq/addq REG, REG 1244 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1245} // isCommutable 1246 1247// NOTE: These are order specific, we want the ri8 forms to be listed 1248// first so that they are slightly preferred to the ri forms. 1249 1250def ADD16ri8_DB : I<0, Pseudo, 1251 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1252 "", // orw/addw REG, imm8 1253 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1254def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1255 "", // orw/addw REG, imm 1256 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1257 1258def ADD32ri8_DB : I<0, Pseudo, 1259 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1260 "", // orl/addl REG, imm8 1261 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1262def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1263 "", // orl/addl REG, imm 1264 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1265 1266 1267def ADD64ri8_DB : I<0, Pseudo, 1268 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1269 "", // orq/addq REG, imm8 1270 [(set GR64:$dst, (or_is_add GR64:$src1, 1271 i64immSExt8:$src2))]>; 1272def ADD64ri32_DB : I<0, Pseudo, 1273 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1274 "", // orq/addq REG, imm 1275 [(set GR64:$dst, (or_is_add GR64:$src1, 1276 i64immSExt32:$src2))]>; 1277} 1278} // AddedComplexity, SchedRW 1279 1280 1281//===----------------------------------------------------------------------===// 1282// Some peepholes 1283//===----------------------------------------------------------------------===// 1284 1285// Odd encoding trick: -128 fits into an 8-bit immediate field while 1286// +128 doesn't, so in this special case use a sub instead of an add. 1287def : Pat<(add GR16:$src1, 128), 1288 (SUB16ri8 GR16:$src1, -128)>; 1289def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1290 (SUB16mi8 addr:$dst, -128)>; 1291 1292def : Pat<(add GR32:$src1, 128), 1293 (SUB32ri8 GR32:$src1, -128)>; 1294def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1295 (SUB32mi8 addr:$dst, -128)>; 1296 1297def : Pat<(add GR64:$src1, 128), 1298 (SUB64ri8 GR64:$src1, -128)>; 1299def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1300 (SUB64mi8 addr:$dst, -128)>; 1301 1302// The same trick applies for 32-bit immediate fields in 64-bit 1303// instructions. 1304def : Pat<(add GR64:$src1, 0x0000000080000000), 1305 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1306def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1307 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1308 1309// To avoid needing to materialize an immediate in a register, use a 32-bit and 1310// with implicit zero-extension instead of a 64-bit and if the immediate has at 1311// least 32 bits of leading zeros. If in addition the last 32 bits can be 1312// represented with a sign extension of a 8 bit constant, use that. 1313 1314def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1315 (SUBREG_TO_REG 1316 (i64 0), 1317 (AND32ri8 1318 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1319 (i32 (GetLo8XForm imm:$imm))), 1320 sub_32bit)>; 1321 1322def : Pat<(and GR64:$src, i64immZExt32:$imm), 1323 (SUBREG_TO_REG 1324 (i64 0), 1325 (AND32ri 1326 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1327 (i32 (GetLo32XForm imm:$imm))), 1328 sub_32bit)>; 1329 1330 1331// r & (2^16-1) ==> movz 1332def : Pat<(and GR32:$src1, 0xffff), 1333 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1334// r & (2^8-1) ==> movz 1335def : Pat<(and GR32:$src1, 0xff), 1336 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1337 GR32_ABCD)), 1338 sub_8bit))>, 1339 Requires<[Not64BitMode]>; 1340// r & (2^8-1) ==> movz 1341def : Pat<(and GR16:$src1, 0xff), 1342 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1343 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1344 sub_16bit)>, 1345 Requires<[Not64BitMode]>; 1346 1347// r & (2^32-1) ==> movz 1348def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1349 (SUBREG_TO_REG (i64 0), 1350 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1351 sub_32bit)>; 1352// r & (2^16-1) ==> movz 1353def : Pat<(and GR64:$src, 0xffff), 1354 (SUBREG_TO_REG (i64 0), 1355 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1356 sub_32bit)>; 1357// r & (2^8-1) ==> movz 1358def : Pat<(and GR64:$src, 0xff), 1359 (SUBREG_TO_REG (i64 0), 1360 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1361 sub_32bit)>; 1362// r & (2^8-1) ==> movz 1363def : Pat<(and GR32:$src1, 0xff), 1364 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1365 Requires<[In64BitMode]>; 1366// r & (2^8-1) ==> movz 1367def : Pat<(and GR16:$src1, 0xff), 1368 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1369 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1370 Requires<[In64BitMode]>; 1371 1372 1373// sext_inreg patterns 1374def : Pat<(sext_inreg GR32:$src, i16), 1375 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1376def : Pat<(sext_inreg GR32:$src, i8), 1377 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1378 GR32_ABCD)), 1379 sub_8bit))>, 1380 Requires<[Not64BitMode]>; 1381 1382def : Pat<(sext_inreg GR16:$src, i8), 1383 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1384 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1385 sub_16bit)>, 1386 Requires<[Not64BitMode]>; 1387 1388def : Pat<(sext_inreg GR64:$src, i32), 1389 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1390def : Pat<(sext_inreg GR64:$src, i16), 1391 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1392def : Pat<(sext_inreg GR64:$src, i8), 1393 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1394def : Pat<(sext_inreg GR32:$src, i8), 1395 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1396 Requires<[In64BitMode]>; 1397def : Pat<(sext_inreg GR16:$src, i8), 1398 (EXTRACT_SUBREG (MOVSX32rr8 1399 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1400 Requires<[In64BitMode]>; 1401 1402// sext, sext_load, zext, zext_load 1403def: Pat<(i16 (sext GR8:$src)), 1404 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1405def: Pat<(sextloadi16i8 addr:$src), 1406 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1407def: Pat<(i16 (zext GR8:$src)), 1408 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1409def: Pat<(zextloadi16i8 addr:$src), 1410 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1411 1412// trunc patterns 1413def : Pat<(i16 (trunc GR32:$src)), 1414 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1415def : Pat<(i8 (trunc GR32:$src)), 1416 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1417 sub_8bit)>, 1418 Requires<[Not64BitMode]>; 1419def : Pat<(i8 (trunc GR16:$src)), 1420 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1421 sub_8bit)>, 1422 Requires<[Not64BitMode]>; 1423def : Pat<(i32 (trunc GR64:$src)), 1424 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1425def : Pat<(i16 (trunc GR64:$src)), 1426 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1427def : Pat<(i8 (trunc GR64:$src)), 1428 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1429def : Pat<(i8 (trunc GR32:$src)), 1430 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1431 Requires<[In64BitMode]>; 1432def : Pat<(i8 (trunc GR16:$src)), 1433 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1434 Requires<[In64BitMode]>; 1435 1436// h-register tricks 1437def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1438 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1439 sub_8bit_hi)>, 1440 Requires<[Not64BitMode]>; 1441def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1442 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1443 sub_8bit_hi)>, 1444 Requires<[Not64BitMode]>; 1445def : Pat<(srl GR16:$src, (i8 8)), 1446 (EXTRACT_SUBREG 1447 (MOVZX32rr8 1448 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1449 sub_8bit_hi)), 1450 sub_16bit)>, 1451 Requires<[Not64BitMode]>; 1452def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1453 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1454 GR16_ABCD)), 1455 sub_8bit_hi))>, 1456 Requires<[Not64BitMode]>; 1457def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1458 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1459 GR16_ABCD)), 1460 sub_8bit_hi))>, 1461 Requires<[Not64BitMode]>; 1462def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1463 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1464 GR32_ABCD)), 1465 sub_8bit_hi))>, 1466 Requires<[Not64BitMode]>; 1467def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1468 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1469 GR32_ABCD)), 1470 sub_8bit_hi))>, 1471 Requires<[Not64BitMode]>; 1472 1473// h-register tricks. 1474// For now, be conservative on x86-64 and use an h-register extract only if the 1475// value is immediately zero-extended or stored, which are somewhat common 1476// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1477// from being allocated in the same instruction as the h register, as there's 1478// currently no way to describe this requirement to the register allocator. 1479 1480// h-register extract and zero-extend. 1481def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1482 (SUBREG_TO_REG 1483 (i64 0), 1484 (MOVZX32_NOREXrr8 1485 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1486 sub_8bit_hi)), 1487 sub_32bit)>; 1488def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1489 (MOVZX32_NOREXrr8 1490 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1491 sub_8bit_hi))>, 1492 Requires<[In64BitMode]>; 1493def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1494 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1495 GR32_ABCD)), 1496 sub_8bit_hi))>, 1497 Requires<[In64BitMode]>; 1498def : Pat<(srl GR16:$src, (i8 8)), 1499 (EXTRACT_SUBREG 1500 (MOVZX32_NOREXrr8 1501 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1502 sub_8bit_hi)), 1503 sub_16bit)>, 1504 Requires<[In64BitMode]>; 1505def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1506 (MOVZX32_NOREXrr8 1507 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1508 sub_8bit_hi))>, 1509 Requires<[In64BitMode]>; 1510def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1511 (MOVZX32_NOREXrr8 1512 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1513 sub_8bit_hi))>, 1514 Requires<[In64BitMode]>; 1515def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1516 (SUBREG_TO_REG 1517 (i64 0), 1518 (MOVZX32_NOREXrr8 1519 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1520 sub_8bit_hi)), 1521 sub_32bit)>; 1522def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1523 (SUBREG_TO_REG 1524 (i64 0), 1525 (MOVZX32_NOREXrr8 1526 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1527 sub_8bit_hi)), 1528 sub_32bit)>; 1529 1530// h-register extract and store. 1531def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1532 (MOV8mr_NOREX 1533 addr:$dst, 1534 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1535 sub_8bit_hi))>; 1536def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1537 (MOV8mr_NOREX 1538 addr:$dst, 1539 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1540 sub_8bit_hi))>, 1541 Requires<[In64BitMode]>; 1542def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1543 (MOV8mr_NOREX 1544 addr:$dst, 1545 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1546 sub_8bit_hi))>, 1547 Requires<[In64BitMode]>; 1548 1549 1550// (shl x, 1) ==> (add x, x) 1551// Note that if x is undef (immediate or otherwise), we could theoretically 1552// end up with the two uses of x getting different values, producing a result 1553// where the least significant bit is not 0. However, the probability of this 1554// happening is considered low enough that this is officially not a 1555// "real problem". 1556def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1557def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1558def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1559def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1560 1561// Helper imms that check if a mask doesn't change significant shift bits. 1562def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>; 1563def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>; 1564 1565// Shift amount is implicitly masked. 1566multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1567 // (shift x (and y, 31)) ==> (shift x, y) 1568 def : Pat<(frag GR8:$src1, (and CL, immShift32)), 1569 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1570 def : Pat<(frag GR16:$src1, (and CL, immShift32)), 1571 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1572 def : Pat<(frag GR32:$src1, (and CL, immShift32)), 1573 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1574 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1575 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1576 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1577 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1578 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1579 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1580 1581 // (shift x (and y, 63)) ==> (shift x, y) 1582 def : Pat<(frag GR64:$src1, (and CL, immShift64)), 1583 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1584 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1585 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1586} 1587 1588defm : MaskedShiftAmountPats<shl, "SHL">; 1589defm : MaskedShiftAmountPats<srl, "SHR">; 1590defm : MaskedShiftAmountPats<sra, "SAR">; 1591defm : MaskedShiftAmountPats<rotl, "ROL">; 1592defm : MaskedShiftAmountPats<rotr, "ROR">; 1593 1594// (anyext (setcc_carry)) -> (setcc_carry) 1595def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1596 (SETB_C16r)>; 1597def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1598 (SETB_C32r)>; 1599def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1600 (SETB_C32r)>; 1601 1602 1603 1604 1605//===----------------------------------------------------------------------===// 1606// EFLAGS-defining Patterns 1607//===----------------------------------------------------------------------===// 1608 1609// add reg, reg 1610def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1611def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1612def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1613 1614// add reg, mem 1615def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1616 (ADD8rm GR8:$src1, addr:$src2)>; 1617def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1618 (ADD16rm GR16:$src1, addr:$src2)>; 1619def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1620 (ADD32rm GR32:$src1, addr:$src2)>; 1621 1622// add reg, imm 1623def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1624def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1625def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1626def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1627 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1628def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1629 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1630 1631// sub reg, reg 1632def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1633def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1634def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1635 1636// sub reg, mem 1637def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1638 (SUB8rm GR8:$src1, addr:$src2)>; 1639def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1640 (SUB16rm GR16:$src1, addr:$src2)>; 1641def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1642 (SUB32rm GR32:$src1, addr:$src2)>; 1643 1644// sub reg, imm 1645def : Pat<(sub GR8:$src1, imm:$src2), 1646 (SUB8ri GR8:$src1, imm:$src2)>; 1647def : Pat<(sub GR16:$src1, imm:$src2), 1648 (SUB16ri GR16:$src1, imm:$src2)>; 1649def : Pat<(sub GR32:$src1, imm:$src2), 1650 (SUB32ri GR32:$src1, imm:$src2)>; 1651def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1652 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1653def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1654 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1655 1656// sub 0, reg 1657def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1658def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1659def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1660def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1661 1662// mul reg, reg 1663def : Pat<(mul GR16:$src1, GR16:$src2), 1664 (IMUL16rr GR16:$src1, GR16:$src2)>; 1665def : Pat<(mul GR32:$src1, GR32:$src2), 1666 (IMUL32rr GR32:$src1, GR32:$src2)>; 1667 1668// mul reg, mem 1669def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1670 (IMUL16rm GR16:$src1, addr:$src2)>; 1671def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1672 (IMUL32rm GR32:$src1, addr:$src2)>; 1673 1674// mul reg, imm 1675def : Pat<(mul GR16:$src1, imm:$src2), 1676 (IMUL16rri GR16:$src1, imm:$src2)>; 1677def : Pat<(mul GR32:$src1, imm:$src2), 1678 (IMUL32rri GR32:$src1, imm:$src2)>; 1679def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1680 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1681def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1682 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1683 1684// reg = mul mem, imm 1685def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1686 (IMUL16rmi addr:$src1, imm:$src2)>; 1687def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1688 (IMUL32rmi addr:$src1, imm:$src2)>; 1689def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1690 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1691def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1692 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1693 1694// Patterns for nodes that do not produce flags, for instructions that do. 1695 1696// addition 1697def : Pat<(add GR64:$src1, GR64:$src2), 1698 (ADD64rr GR64:$src1, GR64:$src2)>; 1699def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1700 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1701def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1702 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1703def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1704 (ADD64rm GR64:$src1, addr:$src2)>; 1705 1706// subtraction 1707def : Pat<(sub GR64:$src1, GR64:$src2), 1708 (SUB64rr GR64:$src1, GR64:$src2)>; 1709def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1710 (SUB64rm GR64:$src1, addr:$src2)>; 1711def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1712 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1713def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1714 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1715 1716// Multiply 1717def : Pat<(mul GR64:$src1, GR64:$src2), 1718 (IMUL64rr GR64:$src1, GR64:$src2)>; 1719def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1720 (IMUL64rm GR64:$src1, addr:$src2)>; 1721def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1722 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1723def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1724 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1725def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1726 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1727def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1728 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1729 1730// Increment/Decrement reg. 1731// Do not make INC/DEC if it is slow 1732let Predicates = [NotSlowIncDec] in { 1733 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 1734 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 1735 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 1736 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1737 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 1738 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 1739 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 1740 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1741} 1742 1743// or reg/reg. 1744def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1745def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1746def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1747def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1748 1749// or reg/mem 1750def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1751 (OR8rm GR8:$src1, addr:$src2)>; 1752def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1753 (OR16rm GR16:$src1, addr:$src2)>; 1754def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1755 (OR32rm GR32:$src1, addr:$src2)>; 1756def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1757 (OR64rm GR64:$src1, addr:$src2)>; 1758 1759// or reg/imm 1760def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1761def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1762def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1763def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1764 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1765def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1766 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1767def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1768 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1769def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1770 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1771 1772// xor reg/reg 1773def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1774def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1775def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1776def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1777 1778// xor reg/mem 1779def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1780 (XOR8rm GR8:$src1, addr:$src2)>; 1781def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1782 (XOR16rm GR16:$src1, addr:$src2)>; 1783def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1784 (XOR32rm GR32:$src1, addr:$src2)>; 1785def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1786 (XOR64rm GR64:$src1, addr:$src2)>; 1787 1788// xor reg/imm 1789def : Pat<(xor GR8:$src1, imm:$src2), 1790 (XOR8ri GR8:$src1, imm:$src2)>; 1791def : Pat<(xor GR16:$src1, imm:$src2), 1792 (XOR16ri GR16:$src1, imm:$src2)>; 1793def : Pat<(xor GR32:$src1, imm:$src2), 1794 (XOR32ri GR32:$src1, imm:$src2)>; 1795def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1796 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1797def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1798 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1799def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1800 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1801def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1802 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1803 1804// and reg/reg 1805def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1806def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1807def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1808def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1809 1810// and reg/mem 1811def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1812 (AND8rm GR8:$src1, addr:$src2)>; 1813def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1814 (AND16rm GR16:$src1, addr:$src2)>; 1815def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1816 (AND32rm GR32:$src1, addr:$src2)>; 1817def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1818 (AND64rm GR64:$src1, addr:$src2)>; 1819 1820// and reg/imm 1821def : Pat<(and GR8:$src1, imm:$src2), 1822 (AND8ri GR8:$src1, imm:$src2)>; 1823def : Pat<(and GR16:$src1, imm:$src2), 1824 (AND16ri GR16:$src1, imm:$src2)>; 1825def : Pat<(and GR32:$src1, imm:$src2), 1826 (AND32ri GR32:$src1, imm:$src2)>; 1827def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1828 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1829def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1830 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1831def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1832 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1833def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1834 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1835 1836// Bit scan instruction patterns to match explicit zero-undef behavior. 1837def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1838def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1839def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1840def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1841def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1842def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1843 1844// When HasMOVBE is enabled it is possible to get a non-legalized 1845// register-register 16 bit bswap. This maps it to a ROL instruction. 1846let Predicates = [HasMOVBE] in { 1847 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 1848} 1849