1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 x87 FPU instruction set, defining the 11// instructions, and properties of the instructions which are needed for code 12// generation, machine code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// FPStack specific DAG Nodes. 18//===----------------------------------------------------------------------===// 19 20def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, 21 SDTCisVT<1, f80>]>; 22def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, 23 SDTCisPtrTy<1>, 24 SDTCisVT<2, OtherVT>]>; 25def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, 26 SDTCisPtrTy<1>, 27 SDTCisVT<2, OtherVT>]>; 28def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, 29 SDTCisVT<2, OtherVT>]>; 30def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 31def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 32 33def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 34 35def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 36 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 37def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 38 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 39 SDNPMemOperand]>; 40def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 41 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 42def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 43 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 44 SDNPMemOperand]>; 45def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 46def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, 47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 48def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, 49 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 50def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, 51 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 52def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 53 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 54 SDNPMemOperand]>; 55 56//===----------------------------------------------------------------------===// 57// FPStack pattern fragments 58//===----------------------------------------------------------------------===// 59 60def fpimm0 : PatLeaf<(fpimm), [{ 61 return N->isExactlyValue(+0.0); 62}]>; 63 64def fpimmneg0 : PatLeaf<(fpimm), [{ 65 return N->isExactlyValue(-0.0); 66}]>; 67 68def fpimm1 : PatLeaf<(fpimm), [{ 69 return N->isExactlyValue(+1.0); 70}]>; 71 72def fpimmneg1 : PatLeaf<(fpimm), [{ 73 return N->isExactlyValue(-1.0); 74}]>; 75 76// Some 'special' instructions 77let usesCustomInserter = 1 in { // Expanded after instruction selection. 78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 79 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 81 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 83 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 85 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 87 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 89 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 91 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 93 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 95 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 96} 97 98// All FP Stack operations are represented with four instructions here. The 99// first three instructions, generated by the instruction selector, use "RFP32" 100// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 101// 64-bit or 80-bit floating point values. These sizes apply to the values, 102// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 103// copied to each other without losing information. These instructions are all 104// pseudo instructions and use the "_Fp" suffix. 105// In some cases there are additional variants with a mixture of different 106// register sizes. 107// The second instruction is defined with FPI, which is the actual instruction 108// emitted by the assembler. These use "RST" registers, although frequently 109// the actual register(s) used are implicit. These are always 80 bits. 110// The FP stackifier pass converts one to the other after register allocation 111// occurs. 112// 113// Note that the FpI instruction should have instruction selection info (e.g. 114// a pattern) and the FPI instruction should have emission info (e.g. opcode 115// encoding and asm printing info). 116 117// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 118// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 119// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 120// f80 instructions cannot use SSE and use neither of these. 121class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 122 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 123class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 124 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 125 126// Factoring for arithmetic. 127multiclass FPBinary_rr<SDNode OpNode> { 128// Register op register -> register 129// These are separated out because they have no reversed form. 130def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 132def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 134def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 136} 137// The FopST0 series are not included here because of the irregularities 138// in where the 'r' goes in assembly output. 139// These instructions cannot address 80-bit memory. 140multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> { 141// ST(0) = ST(0) + [mem] 142def _Fp32m : FpIf32<(outs RFP32:$dst), 143 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 144 [(set RFP32:$dst, 145 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; 146def _Fp64m : FpIf64<(outs RFP64:$dst), 147 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 148 [(set RFP64:$dst, 149 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; 150def _Fp64m32: FpIf64<(outs RFP64:$dst), 151 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 152 [(set RFP64:$dst, 153 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>; 154def _Fp80m32: FpI_<(outs RFP80:$dst), 155 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 156 [(set RFP80:$dst, 157 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>; 158def _Fp80m64: FpI_<(outs RFP80:$dst), 159 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 160 [(set RFP80:$dst, 161 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>; 162def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 163 !strconcat("f", asmstring, "{s}\t$src")> { 164 let mayLoad = 1; 165} 166def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 167 !strconcat("f", asmstring, "{l}\t$src")> { 168 let mayLoad = 1; 169} 170// ST(0) = ST(0) + [memint] 171def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 172 OneArgFPRW, 173 [(set RFP32:$dst, (OpNode RFP32:$src1, 174 (X86fild addr:$src2, i16)))]>; 175def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 176 OneArgFPRW, 177 [(set RFP32:$dst, (OpNode RFP32:$src1, 178 (X86fild addr:$src2, i32)))]>; 179def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 180 OneArgFPRW, 181 [(set RFP64:$dst, (OpNode RFP64:$src1, 182 (X86fild addr:$src2, i16)))]>; 183def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 184 OneArgFPRW, 185 [(set RFP64:$dst, (OpNode RFP64:$src1, 186 (X86fild addr:$src2, i32)))]>; 187def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 188 OneArgFPRW, 189 [(set RFP80:$dst, (OpNode RFP80:$src1, 190 (X86fild addr:$src2, i16)))]>; 191def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 192 OneArgFPRW, 193 [(set RFP80:$dst, (OpNode RFP80:$src1, 194 (X86fild addr:$src2, i32)))]>; 195def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 196 !strconcat("fi", asmstring, "{s}\t$src")> { 197 let mayLoad = 1; 198} 199def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 200 !strconcat("fi", asmstring, "{l}\t$src")> { 201 let mayLoad = 1; 202} 203} 204 205let Defs = [FPSW] in { 206// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 207// resources. 208defm ADD : FPBinary_rr<fadd>; 209defm SUB : FPBinary_rr<fsub>; 210defm MUL : FPBinary_rr<fmul>; 211defm DIV : FPBinary_rr<fdiv>; 212// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 213let SchedRW = [WriteFAddLd] in { 214defm ADD : FPBinary<fadd, MRM0m, "add">; 215defm SUB : FPBinary<fsub, MRM4m, "sub">; 216defm SUBR: FPBinary<fsub ,MRM5m, "subr">; 217} 218let SchedRW = [WriteFMulLd] in { 219defm MUL : FPBinary<fmul, MRM1m, "mul">; 220} 221let SchedRW = [WriteFDivLd] in { 222defm DIV : FPBinary<fdiv, MRM6m, "div">; 223defm DIVR: FPBinary<fdiv, MRM7m, "divr">; 224} 225} 226 227class FPST0rInst<Format fp, string asm> 228 : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; 229class FPrST0Inst<Format fp, string asm> 230 : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; 231class FPrST0PInst<Format fp, string asm> 232 : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; 233 234// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 235// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 236// we have to put some 'r's in and take them out of weird places. 237let SchedRW = [WriteFAdd] in { 238def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; 239def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; 240def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; 241def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">; 242def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">; 243def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; 244def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; 245def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; 246def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; 247} // SchedRW 248let SchedRW = [WriteFMul] in { 249def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; 250def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; 251def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; 252} // SchedRW 253let SchedRW = [WriteFDiv] in { 254def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; 255def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; 256def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; 257def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; 258def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; 259def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; 260} // SchedRW 261 262def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 263def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 264 265// Unary operations. 266multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 267def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 268 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 269def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 270 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 271def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 272 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 273def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 274} 275 276let Defs = [FPSW] in { 277defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 278defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 279let SchedRW = [WriteFSqrt] in { 280defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; 281} 282defm SIN : FPUnary<fsin, MRM_FE, "fsin">; 283defm COS : FPUnary<fcos, MRM_FF, "fcos">; 284 285let hasSideEffects = 0 in { 286def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 287def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 288def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 289} 290def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 291} // Defs = [FPSW] 292 293// Versions of FP instructions that take a single memory operand. Added for the 294// disassembler; remove as they are included with patterns elsewhere. 295def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 296def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 297 298def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 299def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">; 300 301def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 302def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 303 304def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 305def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 306 307def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">; 308def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">; 309def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">; 310 311def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 312def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 313 314def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">; 315def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">; 316 317// Floating point cmovs. 318class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 319 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 320class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 321 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 322 323multiclass FPCMov<PatLeaf cc> { 324 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 325 CondMovFP, 326 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 327 cc, EFLAGS))]>; 328 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 329 CondMovFP, 330 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 331 cc, EFLAGS))]>; 332 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 333 CondMovFP, 334 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 335 cc, EFLAGS))]>, 336 Requires<[HasCMov]>; 337} 338 339let Defs = [FPSW] in { 340let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 341defm CMOVB : FPCMov<X86_COND_B>; 342defm CMOVBE : FPCMov<X86_COND_BE>; 343defm CMOVE : FPCMov<X86_COND_E>; 344defm CMOVP : FPCMov<X86_COND_P>; 345defm CMOVNB : FPCMov<X86_COND_AE>; 346defm CMOVNBE: FPCMov<X86_COND_A>; 347defm CMOVNE : FPCMov<X86_COND_NE>; 348defm CMOVNP : FPCMov<X86_COND_NP>; 349} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 350 351let Predicates = [HasCMov] in { 352// These are not factored because there's no clean way to pass DA/DB. 353def CMOVB_F : FPI<0xDA, MRM0r, (outs RST:$op), (ins), 354 "fcmovb\t{$op, %st(0)|st(0), $op}">; 355def CMOVBE_F : FPI<0xDA, MRM2r, (outs RST:$op), (ins), 356 "fcmovbe\t{$op, %st(0)|st(0), $op}">; 357def CMOVE_F : FPI<0xDA, MRM1r, (outs RST:$op), (ins), 358 "fcmove\t{$op, %st(0)|st(0), $op}">; 359def CMOVP_F : FPI<0xDA, MRM3r, (outs RST:$op), (ins), 360 "fcmovu\t{$op, %st(0)|st(0), $op}">; 361def CMOVNB_F : FPI<0xDB, MRM0r, (outs RST:$op), (ins), 362 "fcmovnb\t{$op, %st(0)|st(0), $op}">; 363def CMOVNBE_F: FPI<0xDB, MRM2r, (outs RST:$op), (ins), 364 "fcmovnbe\t{$op, %st(0)|st(0), $op}">; 365def CMOVNE_F : FPI<0xDB, MRM1r, (outs RST:$op), (ins), 366 "fcmovne\t{$op, %st(0)|st(0), $op}">; 367def CMOVNP_F : FPI<0xDB, MRM3r, (outs RST:$op), (ins), 368 "fcmovnu\t{$op, %st(0)|st(0), $op}">; 369} // Predicates = [HasCMov] 370 371// Floating point loads & stores. 372let canFoldAsLoad = 1 in { 373def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 374 [(set RFP32:$dst, (loadf32 addr:$src))]>; 375let isReMaterializable = 1 in 376 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 377 [(set RFP64:$dst, (loadf64 addr:$src))]>; 378def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 379 [(set RFP80:$dst, (loadf80 addr:$src))]>; 380} 381def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 382 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 383def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 384 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 385def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 386 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 387def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 388 [(set RFP32:$dst, (X86fild addr:$src, i16))]>; 389def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 390 [(set RFP32:$dst, (X86fild addr:$src, i32))]>; 391def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 392 [(set RFP32:$dst, (X86fild addr:$src, i64))]>; 393def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 394 [(set RFP64:$dst, (X86fild addr:$src, i16))]>; 395def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 396 [(set RFP64:$dst, (X86fild addr:$src, i32))]>; 397def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 398 [(set RFP64:$dst, (X86fild addr:$src, i64))]>; 399def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 400 [(set RFP80:$dst, (X86fild addr:$src, i16))]>; 401def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 402 [(set RFP80:$dst, (X86fild addr:$src, i32))]>; 403def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 404 [(set RFP80:$dst, (X86fild addr:$src, i64))]>; 405 406def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 407 [(store RFP32:$src, addr:$op)]>; 408def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 409 [(truncstoref32 RFP64:$src, addr:$op)]>; 410def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 411 [(store RFP64:$src, addr:$op)]>; 412def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 413 [(truncstoref32 RFP80:$src, addr:$op)]>; 414def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 415 [(truncstoref64 RFP80:$src, addr:$op)]>; 416// FST does not support 80-bit memory target; FSTP must be used. 417 418let mayStore = 1, hasSideEffects = 0 in { 419def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 420def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 421def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 422def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 423def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 424} 425def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 426 [(store RFP80:$src, addr:$op)]>; 427let mayStore = 1, hasSideEffects = 0 in { 428def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 429def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 430def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 431def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 432def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 433def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 434def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 435def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 436def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 437} 438 439let mayLoad = 1, SchedRW = [WriteLoad] in { 440def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src", 441 IIC_FLD>; 442def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src", 443 IIC_FLD>; 444def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src", 445 IIC_FLD80>; 446def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src", 447 IIC_FILD>; 448def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src", 449 IIC_FILD>; 450def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src", 451 IIC_FILD>; 452} 453let mayStore = 1, SchedRW = [WriteStore] in { 454def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst", 455 IIC_FST>; 456def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst", 457 IIC_FST>; 458def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst", 459 IIC_FST>; 460def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst", 461 IIC_FST>; 462def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst", 463 IIC_FST80>; 464def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst", 465 IIC_FIST>; 466def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst", 467 IIC_FIST>; 468def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst", 469 IIC_FIST>; 470def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst", 471 IIC_FIST>; 472def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst", 473 IIC_FIST>; 474} 475 476// FISTTP requires SSE3 even though it's a FPStack op. 477let Predicates = [HasSSE3] in { 478def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 479 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 480def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 481 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 482def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 483 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 484def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 485 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 486def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 487 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 488def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 489 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 490def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 491 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 492def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 493 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 494def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 495 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 496} // Predicates = [HasSSE3] 497 498let mayStore = 1, SchedRW = [WriteStore] in { 499def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst", 500 IIC_FST>; 501def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst", 502 IIC_FST>; 503def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), 504 "fisttp{ll}\t$dst", IIC_FST>; 505} 506 507// FP Stack manipulation instructions. 508let SchedRW = [WriteMove] in { 509def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>; 510def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>; 511def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>; 512def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>; 513} 514 515// Floating point constant loads. 516let isReMaterializable = 1 in { 517def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 518 [(set RFP32:$dst, fpimm0)]>; 519def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 520 [(set RFP32:$dst, fpimm1)]>; 521def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 522 [(set RFP64:$dst, fpimm0)]>; 523def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 524 [(set RFP64:$dst, fpimm1)]>; 525def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 526 [(set RFP80:$dst, fpimm0)]>; 527def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 528 [(set RFP80:$dst, fpimm1)]>; 529} 530 531let SchedRW = [WriteZero] in { 532def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>; 533def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>; 534} 535 536// Floating point compares. 537let SchedRW = [WriteFAdd] in { 538def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 539 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 540def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 541 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 542def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 543 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 544} // SchedRW 545} // Defs = [FPSW] 546 547let SchedRW = [WriteFAdd] in { 548// CC = ST(0) cmp ST(i) 549let Defs = [EFLAGS, FPSW] in { 550def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 551 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; 552def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 553 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; 554def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 555 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; 556} 557 558let Defs = [FPSW], Uses = [ST0] in { 559def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 560 (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>; 561def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 562 (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>; 563def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 564 (outs), (ins), "fucompp", IIC_FUCOM>; 565} 566 567let Defs = [EFLAGS, FPSW], Uses = [ST0] in { 568def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 569 (outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>; 570def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 571 (outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>; 572} 573 574let Defs = [EFLAGS, FPSW] in { 575def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), 576 "fcomi\t$reg", IIC_FCOMI>; 577def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), 578 "fcompi\t$reg", IIC_FCOMI>; 579} 580} // SchedRW 581 582// Floating point flag ops. 583let SchedRW = [WriteALU] in { 584let Defs = [AX], Uses = [FPSW] in 585def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 586 (outs), (ins), "fnstsw\t{%ax|ax}", 587 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>; 588 589def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 590 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 591 [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>; 592} // SchedRW 593let mayLoad = 1 in 594def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 595 (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>, 596 Sched<[WriteLoad]>; 597 598// FPU control instructions 599let SchedRW = [WriteMicrocoded] in { 600let Defs = [FPSW] in 601def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>; 602def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), 603 "ffree\t$reg", IIC_FFREE>; 604// Clear exceptions 605 606let Defs = [FPSW] in 607def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; 608} // SchedRW 609 610// Operandless floating-point instructions for the disassembler. 611let SchedRW = [WriteMicrocoded] in { 612def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>; 613 614def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>; 615def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>; 616def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>; 617def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>; 618def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>; 619def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>; 620def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>; 621def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>; 622def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>; 623def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>; 624def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>; 625def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>; 626def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>; 627def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>; 628def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>; 629def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>; 630def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>; 631def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>; 632def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>; 633def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>; 634def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>; 635 636def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), 637 "fxsave\t$dst", [], IIC_FXSAVE>, TB; 638def FXSAVE64 : RI<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), 639 "fxsave{q|64}\t$dst", [], IIC_FXSAVE>, TB, 640 Requires<[In64BitMode]>; 641def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 642 "fxrstor\t$src", [], IIC_FXRSTOR>, TB; 643def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 644 "fxrstor{q|64}\t$src", [], IIC_FXRSTOR>, TB, 645 Requires<[In64BitMode]>; 646} // SchedRW 647 648//===----------------------------------------------------------------------===// 649// Non-Instruction Patterns 650//===----------------------------------------------------------------------===// 651 652// Required for RET of f32 / f64 / f80 values. 653def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; 654def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; 655def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; 656 657// Required for CALL which return f32 / f64 / f80 values. 658def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; 659def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, 660 RFP64:$src)>; 661def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; 662def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, 663 RFP80:$src)>; 664def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, 665 RFP80:$src)>; 666def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, 667 RFP80:$src)>; 668 669// Floating point constant -0.0 and -1.0 670def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 671def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 672def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 673def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 674def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 675def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 676 677// Used to conv. i64 to f64 since there isn't a SSE version. 678def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; 679 680// FP extensions map onto simple pseudo-value conversions if they are to/from 681// the FP stack. 682def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 683 Requires<[FPStackf32]>; 684def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 685 Requires<[FPStackf32]>; 686def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 687 Requires<[FPStackf64]>; 688 689// FP truncations map onto simple pseudo-value conversions if they are to/from 690// the FP stack. We have validated that only value-preserving truncations make 691// it through isel. 692def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 693 Requires<[FPStackf32]>; 694def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 695 Requires<[FPStackf32]>; 696def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 697 Requires<[FPStackf64]>; 698