1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instruction set, defining the instructions, and 11// properties of the instructions which are needed for code generation, machine 12// code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// X86 specific DAG Nodes. 18// 19 20def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33// Unary and binary operator instructions that set EFLAGS as a side-effect. 34def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisSameAs<0, 2>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 39 [SDTCisSameAs<0, 2>, 40 SDTCisSameAs<0, 3>, 41 SDTCisInt<0>, SDTCisVT<1, i32>]>; 42 43// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 44def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 45 [SDTCisSameAs<0, 2>, 46 SDTCisSameAs<0, 3>, 47 SDTCisInt<0>, 48 SDTCisVT<1, i32>, 49 SDTCisVT<4, i32>]>; 50// RES1, RES2, FLAGS = op LHS, RHS 51def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 52 [SDTCisSameAs<0, 1>, 53 SDTCisSameAs<0, 2>, 54 SDTCisSameAs<0, 3>, 55 SDTCisInt<0>, SDTCisVT<1, i32>]>; 56def SDTX86BrCond : SDTypeProfile<0, 3, 57 [SDTCisVT<0, OtherVT>, 58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 59 60def SDTX86SetCC : SDTypeProfile<1, 2, 61 [SDTCisVT<0, i8>, 62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 63def SDTX86SetCC_C : SDTypeProfile<1, 2, 64 [SDTCisInt<0>, 65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 66 67def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 68 69def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 70 71def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 72 SDTCisVT<2, i8>]>; 73def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 74 75def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 77def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 78 79def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 80def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 81 SDTCisVT<1, i32>]>; 82 83def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 84 85def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 86 SDTCisVT<1, iPTR>, 87 SDTCisVT<2, iPTR>]>; 88 89def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 90 SDTCisPtrTy<1>, 91 SDTCisVT<2, i32>, 92 SDTCisVT<3, i8>, 93 SDTCisVT<4, i32>]>; 94 95def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 96 97def SDTX86Void : SDTypeProfile<0, 0, []>; 98 99def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 100 101def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 102 103def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 104 105def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 106 107def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 108 109def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 110 111def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 112 113def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 114 115def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 116 117def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 118 [SDNPHasChain,SDNPSideEffect]>; 119def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 120 [SDNPHasChain]>; 121def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 122 [SDNPHasChain]>; 123def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 124 [SDNPHasChain]>; 125 126 127def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 128def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 129def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 130def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 131 132def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 133def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 134 135def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 136def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 137 [SDNPHasChain]>; 138def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 139def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 140 141def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 142 143def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 144 [SDNPHasChain, SDNPSideEffect]>; 145 146def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 147 [SDNPHasChain, SDNPSideEffect]>; 148 149def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 151 SDNPMayLoad, SDNPMemOperand]>; 152def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 154 SDNPMayLoad, SDNPMemOperand]>; 155def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 157 SDNPMayLoad, SDNPMemOperand]>; 158 159def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 161 162def X86vastart_save_xmm_regs : 163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 164 SDT_X86VASTART_SAVE_XMM_REGS, 165 [SDNPHasChain, SDNPVariadic]>; 166def X86vaarg64 : 167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 169 SDNPMemOperand]>; 170def X86callseq_start : 171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 172 [SDNPHasChain, SDNPOutGlue]>; 173def X86callseq_end : 174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 176 177def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 179 SDNPVariadic]>; 180 181def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 183def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 185 SDNPMayLoad]>; 186 187def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 189def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 191def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, 192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 193 194def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 195def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 196 197def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER", 198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 199 SDTCisInt<1>]>>; 200 201def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 203 204def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 206 207def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 208 [SDNPHasChain]>; 209 210def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 211 SDTypeProfile<1, 1, [SDTCisInt<0>, 212 SDTCisPtrTy<1>]>, 213 [SDNPHasChain, SDNPSideEffect]>; 214def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 216 [SDNPHasChain, SDNPSideEffect]>; 217 218def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 220 221def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 222 [SDNPCommutative]>; 223def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 224def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 225 [SDNPCommutative]>; 226def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 227 [SDNPCommutative]>; 228def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 229def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 230 231def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 232def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 233def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 234 [SDNPCommutative]>; 235def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 236 [SDNPCommutative]>; 237def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 238 [SDNPCommutative]>; 239 240def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 241 242def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 243 244def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 246 247def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 248 [SDNPHasChain]>; 249 250def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 252 253def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, 254 [SDNPHasChain, SDNPOutGlue]>; 255 256//===----------------------------------------------------------------------===// 257// X86 Operand Definitions. 258// 259 260// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 261// the index operand of an address, to conform to x86 encoding restrictions. 262def ptr_rc_nosp : PointerLikeRegClass<1>; 263 264// *mem - Operand definitions for the funky X86 addressing mode operands. 265// 266def X86MemAsmOperand : AsmOperandClass { 267 let Name = "Mem"; 268} 269let RenderMethod = "addMemOperands" in { 270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 278 // Gather mem operands 279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; } 280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; } 281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; } 282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; } 283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; } 284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; } 285} 286 287def X86AbsMemAsmOperand : AsmOperandClass { 288 let Name = "AbsMem"; 289 let SuperClasses = [X86MemAsmOperand]; 290} 291 292class X86MemOperand<string printMethod, 293 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { 294 let PrintMethod = printMethod; 295 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 296 let ParserMatchClass = parserMatchClass; 297 let OperandType = "OPERAND_MEMORY"; 298} 299 300// Gather mem operands 301class X86VMemOperand<RegisterClass RC, string printMethod, 302 AsmOperandClass parserMatchClass> 303 : X86MemOperand<printMethod, parserMatchClass> { 304 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm); 305} 306 307def anymem : X86MemOperand<"printanymem">; 308 309def opaque32mem : X86MemOperand<"printopaquemem">; 310def opaque48mem : X86MemOperand<"printopaquemem">; 311def opaque80mem : X86MemOperand<"printopaquemem">; 312def opaque512mem : X86MemOperand<"printopaquemem">; 313 314def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; 315def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; 316def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; 317def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; 318def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; 319def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; 320def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; 321def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; 322def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; 323def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; 324def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; 325def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; 326def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; 327 328def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>; 329 330// Gather mem operands 331def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>; 332def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>; 333def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>; 334def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>; 335def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>; 336def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>; 337def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>; 338 339// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 340// plain GR64, so that it doesn't potentially require a REX prefix. 341def i8mem_NOREX : Operand<i64> { 342 let PrintMethod = "printi8mem"; 343 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 344 let ParserMatchClass = X86Mem8AsmOperand; 345 let OperandType = "OPERAND_MEMORY"; 346} 347 348// GPRs available for tailcall. 349// It represents GR32_TC, GR64_TC or GR64_TCW64. 350def ptr_rc_tailcall : PointerLikeRegClass<2>; 351 352// Special i32mem for addresses of load folding tail calls. These are not 353// allowed to use callee-saved registers since they must be scheduled 354// after callee-saved register are popped. 355def i32mem_TC : Operand<i32> { 356 let PrintMethod = "printi32mem"; 357 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 358 i32imm, i8imm); 359 let ParserMatchClass = X86Mem32AsmOperand; 360 let OperandType = "OPERAND_MEMORY"; 361} 362 363// Special i64mem for addresses of load folding tail calls. These are not 364// allowed to use callee-saved registers since they must be scheduled 365// after callee-saved register are popped. 366def i64mem_TC : Operand<i64> { 367 let PrintMethod = "printi64mem"; 368 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 369 ptr_rc_tailcall, i32imm, i8imm); 370 let ParserMatchClass = X86Mem64AsmOperand; 371 let OperandType = "OPERAND_MEMORY"; 372} 373 374let OperandType = "OPERAND_PCREL", 375 ParserMatchClass = X86AbsMemAsmOperand, 376 PrintMethod = "printPCRelImm" in { 377def i32imm_pcrel : Operand<i32>; 378def i16imm_pcrel : Operand<i16>; 379 380// Branch targets have OtherVT type and print as pc-relative values. 381def brtarget : Operand<OtherVT>; 382def brtarget8 : Operand<OtherVT>; 383 384} 385 386// Special parsers to detect mode to disambiguate. 387def X86AbsMem16AsmOperand : AsmOperandClass { 388 let Name = "AbsMem16"; 389 let RenderMethod = "addAbsMemOperands"; 390 let SuperClasses = [X86AbsMemAsmOperand]; 391} 392 393def X86AbsMem32AsmOperand : AsmOperandClass { 394 let Name = "AbsMem32"; 395 let RenderMethod = "addAbsMemOperands"; 396 let SuperClasses = [X86AbsMemAsmOperand]; 397} 398 399// Branch targets have OtherVT type and print as pc-relative values. 400let OperandType = "OPERAND_PCREL", 401 PrintMethod = "printPCRelImm" in { 402let ParserMatchClass = X86AbsMem16AsmOperand in 403 def brtarget16 : Operand<OtherVT>; 404let ParserMatchClass = X86AbsMem32AsmOperand in 405 def brtarget32 : Operand<OtherVT>; 406} 407 408let RenderMethod = "addSrcIdxOperands" in { 409 def X86SrcIdx8Operand : AsmOperandClass { 410 let Name = "SrcIdx8"; 411 let SuperClasses = [X86Mem8AsmOperand]; 412 } 413 def X86SrcIdx16Operand : AsmOperandClass { 414 let Name = "SrcIdx16"; 415 let SuperClasses = [X86Mem16AsmOperand]; 416 } 417 def X86SrcIdx32Operand : AsmOperandClass { 418 let Name = "SrcIdx32"; 419 let SuperClasses = [X86Mem32AsmOperand]; 420 } 421 def X86SrcIdx64Operand : AsmOperandClass { 422 let Name = "SrcIdx64"; 423 let SuperClasses = [X86Mem64AsmOperand]; 424 } 425} // RenderMethod = "addSrcIdxOperands" 426 427let RenderMethod = "addDstIdxOperands" in { 428 def X86DstIdx8Operand : AsmOperandClass { 429 let Name = "DstIdx8"; 430 let SuperClasses = [X86Mem8AsmOperand]; 431 } 432 def X86DstIdx16Operand : AsmOperandClass { 433 let Name = "DstIdx16"; 434 let SuperClasses = [X86Mem16AsmOperand]; 435 } 436 def X86DstIdx32Operand : AsmOperandClass { 437 let Name = "DstIdx32"; 438 let SuperClasses = [X86Mem32AsmOperand]; 439 } 440 def X86DstIdx64Operand : AsmOperandClass { 441 let Name = "DstIdx64"; 442 let SuperClasses = [X86Mem64AsmOperand]; 443 } 444} // RenderMethod = "addDstIdxOperands" 445 446let RenderMethod = "addMemOffsOperands" in { 447 def X86MemOffs16_8AsmOperand : AsmOperandClass { 448 let Name = "MemOffs16_8"; 449 let SuperClasses = [X86Mem8AsmOperand]; 450 } 451 def X86MemOffs16_16AsmOperand : AsmOperandClass { 452 let Name = "MemOffs16_16"; 453 let SuperClasses = [X86Mem16AsmOperand]; 454 } 455 def X86MemOffs16_32AsmOperand : AsmOperandClass { 456 let Name = "MemOffs16_32"; 457 let SuperClasses = [X86Mem32AsmOperand]; 458 } 459 def X86MemOffs32_8AsmOperand : AsmOperandClass { 460 let Name = "MemOffs32_8"; 461 let SuperClasses = [X86Mem8AsmOperand]; 462 } 463 def X86MemOffs32_16AsmOperand : AsmOperandClass { 464 let Name = "MemOffs32_16"; 465 let SuperClasses = [X86Mem16AsmOperand]; 466 } 467 def X86MemOffs32_32AsmOperand : AsmOperandClass { 468 let Name = "MemOffs32_32"; 469 let SuperClasses = [X86Mem32AsmOperand]; 470 } 471 def X86MemOffs32_64AsmOperand : AsmOperandClass { 472 let Name = "MemOffs32_64"; 473 let SuperClasses = [X86Mem64AsmOperand]; 474 } 475 def X86MemOffs64_8AsmOperand : AsmOperandClass { 476 let Name = "MemOffs64_8"; 477 let SuperClasses = [X86Mem8AsmOperand]; 478 } 479 def X86MemOffs64_16AsmOperand : AsmOperandClass { 480 let Name = "MemOffs64_16"; 481 let SuperClasses = [X86Mem16AsmOperand]; 482 } 483 def X86MemOffs64_32AsmOperand : AsmOperandClass { 484 let Name = "MemOffs64_32"; 485 let SuperClasses = [X86Mem32AsmOperand]; 486 } 487 def X86MemOffs64_64AsmOperand : AsmOperandClass { 488 let Name = "MemOffs64_64"; 489 let SuperClasses = [X86Mem64AsmOperand]; 490 } 491} // RenderMethod = "addMemOffsOperands" 492 493class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 494 : X86MemOperand<printMethod, parserMatchClass> { 495 let MIOperandInfo = (ops ptr_rc, i8imm); 496} 497 498class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 499 : X86MemOperand<printMethod, parserMatchClass> { 500 let MIOperandInfo = (ops ptr_rc); 501} 502 503def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 504def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 505def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 506def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 507def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 508def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 509def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 510def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 511 512class X86MemOffsOperand<Operand immOperand, string printMethod, 513 AsmOperandClass parserMatchClass> 514 : X86MemOperand<printMethod, parserMatchClass> { 515 let MIOperandInfo = (ops immOperand, i8imm); 516} 517 518def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 519 X86MemOffs16_8AsmOperand>; 520def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 521 X86MemOffs16_16AsmOperand>; 522def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 523 X86MemOffs16_32AsmOperand>; 524def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 525 X86MemOffs32_8AsmOperand>; 526def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 527 X86MemOffs32_16AsmOperand>; 528def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 529 X86MemOffs32_32AsmOperand>; 530def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 531 X86MemOffs32_64AsmOperand>; 532def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 533 X86MemOffs64_8AsmOperand>; 534def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 535 X86MemOffs64_16AsmOperand>; 536def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 537 X86MemOffs64_32AsmOperand>; 538def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 539 X86MemOffs64_64AsmOperand>; 540 541def SSECC : Operand<i8> { 542 let PrintMethod = "printSSECC"; 543 let OperandType = "OPERAND_IMMEDIATE"; 544} 545 546def i8immZExt3 : ImmLeaf<i8, [{ 547 return Imm >= 0 && Imm < 8; 548}]>; 549 550def AVXCC : Operand<i8> { 551 let PrintMethod = "printAVXCC"; 552 let OperandType = "OPERAND_IMMEDIATE"; 553} 554 555def i8immZExt5 : ImmLeaf<i8, [{ 556 return Imm >= 0 && Imm < 32; 557}]>; 558// AVX-512 uses a 32-bit immediate in their intrinsics 559def i32immZExt5 : ImmLeaf<i32, [{ 560 return Imm >= 0 && Imm < 32; 561}]>; 562 563class ImmSExtAsmOperandClass : AsmOperandClass { 564 let SuperClasses = [ImmAsmOperand]; 565 let RenderMethod = "addImmOperands"; 566} 567 568def X86GR32orGR64AsmOperand : AsmOperandClass { 569 let Name = "GR32orGR64"; 570} 571 572def GR32orGR64 : RegisterOperand<GR32> { 573 let ParserMatchClass = X86GR32orGR64AsmOperand; 574} 575 576def AVX512RC : Operand<i32> { 577 let PrintMethod = "printRoundingControl"; 578 let OperandType = "OPERAND_IMMEDIATE"; 579} 580 581// Sign-extended immediate classes. We don't need to define the full lattice 582// here because there is no instruction with an ambiguity between ImmSExti64i32 583// and ImmSExti32i8. 584// 585// The strange ranges come from the fact that the assembler always works with 586// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 587// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 588 589// [0, 0x7FFFFFFF] | 590// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 591def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 592 let Name = "ImmSExti64i32"; 593} 594 595// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 596// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 597def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 598 let Name = "ImmSExti16i8"; 599 let SuperClasses = [ImmSExti64i32AsmOperand]; 600} 601 602// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 603// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 604def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 605 let Name = "ImmSExti32i8"; 606} 607 608// [0, 0x0000007F] | 609// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 610def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 611 let Name = "ImmSExti64i8"; 612 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 613 ImmSExti64i32AsmOperand]; 614} 615 616// A couple of more descriptive operand definitions. 617// 16-bits but only 8 bits are significant. 618def i16i8imm : Operand<i16> { 619 let ParserMatchClass = ImmSExti16i8AsmOperand; 620 let OperandType = "OPERAND_IMMEDIATE"; 621} 622// 32-bits but only 8 bits are significant. 623def i32i8imm : Operand<i32> { 624 let ParserMatchClass = ImmSExti32i8AsmOperand; 625 let OperandType = "OPERAND_IMMEDIATE"; 626} 627 628// 64-bits but only 32 bits are significant. 629def i64i32imm : Operand<i64> { 630 let ParserMatchClass = ImmSExti64i32AsmOperand; 631 let OperandType = "OPERAND_IMMEDIATE"; 632} 633 634// 64-bits but only 32 bits are significant, and those bits are treated as being 635// pc relative. 636def i64i32imm_pcrel : Operand<i64> { 637 let PrintMethod = "printPCRelImm"; 638 let ParserMatchClass = X86AbsMemAsmOperand; 639 let OperandType = "OPERAND_PCREL"; 640} 641 642// 64-bits but only 8 bits are significant. 643def i64i8imm : Operand<i64> { 644 let ParserMatchClass = ImmSExti64i8AsmOperand; 645 let OperandType = "OPERAND_IMMEDIATE"; 646} 647 648def lea64_32mem : Operand<i32> { 649 let PrintMethod = "printanymem"; 650 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 651 let ParserMatchClass = X86MemAsmOperand; 652} 653 654// Memory operands that use 64-bit pointers in both ILP32 and LP64. 655def lea64mem : Operand<i64> { 656 let PrintMethod = "printanymem"; 657 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 658 let ParserMatchClass = X86MemAsmOperand; 659} 660 661 662//===----------------------------------------------------------------------===// 663// X86 Complex Pattern Definitions. 664// 665 666// Define X86 specific addressing mode. 667def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 668def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 669 [add, sub, mul, X86mul_imm, shl, or, frameindex], 670 []>; 671// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 672def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr", 673 [add, sub, mul, X86mul_imm, shl, or, 674 frameindex, X86WrapperRIP], 675 []>; 676 677def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 678 [tglobaltlsaddr], []>; 679 680def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 681 [tglobaltlsaddr], []>; 682 683def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 684 [add, sub, mul, X86mul_imm, shl, or, frameindex, 685 X86WrapperRIP], []>; 686 687def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 688 [tglobaltlsaddr], []>; 689 690def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 691 [tglobaltlsaddr], []>; 692 693//===----------------------------------------------------------------------===// 694// X86 Instruction Predicate Definitions. 695def HasCMov : Predicate<"Subtarget->hasCMov()">; 696def NoCMov : Predicate<"!Subtarget->hasCMov()">; 697 698def HasMMX : Predicate<"Subtarget->hasMMX()">; 699def Has3DNow : Predicate<"Subtarget->has3DNow()">; 700def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 701def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 702def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 703def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 704def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 705def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 706def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 707def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 708def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 709def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 710def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 711def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 712def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 713def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 714def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 715def HasAVX : Predicate<"Subtarget->hasAVX()">; 716def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 717def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 718def HasAVX512 : Predicate<"Subtarget->hasAVX512()">, 719 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">; 720def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 721def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 722def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 723def HasCDI : Predicate<"Subtarget->hasCDI()">; 724def HasPFI : Predicate<"Subtarget->hasPFI()">; 725def HasERI : Predicate<"Subtarget->hasERI()">; 726def HasDQI : Predicate<"Subtarget->hasDQI()">; 727def NoDQI : Predicate<"!Subtarget->hasDQI()">; 728def HasBWI : Predicate<"Subtarget->hasBWI()">; 729def HasVLX : Predicate<"Subtarget->hasVLX()">, 730 AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">; 731def NoVLX : Predicate<"!Subtarget->hasVLX()">; 732 733def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 734def HasAES : Predicate<"Subtarget->hasAES()">; 735def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 736def HasFMA : Predicate<"Subtarget->hasFMA()">; 737def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; 738def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 739def HasXOP : Predicate<"Subtarget->hasXOP()">; 740def HasTBM : Predicate<"Subtarget->hasTBM()">; 741def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 742def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 743def HasF16C : Predicate<"Subtarget->hasF16C()">; 744def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 745def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 746def HasBMI : Predicate<"Subtarget->hasBMI()">; 747def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 748def HasRTM : Predicate<"Subtarget->hasRTM()">; 749def HasHLE : Predicate<"Subtarget->hasHLE()">; 750def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; 751def HasADX : Predicate<"Subtarget->hasADX()">; 752def HasSHA : Predicate<"Subtarget->hasSHA()">; 753def HasSGX : Predicate<"Subtarget->hasSGX()">; 754def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 755def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 756def HasSMAP : Predicate<"Subtarget->hasSMAP()">; 757def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 758def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 759def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 760def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 761def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 762 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 763def In64BitMode : Predicate<"Subtarget->is64Bit()">, 764 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 765def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 766def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 767def In16BitMode : Predicate<"Subtarget->is16Bit()">, 768 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 769def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 770 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 771def In32BitMode : Predicate<"Subtarget->is32Bit()">, 772 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 773def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 774def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 775def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 776def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 777def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 778def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 779 "TM.getCodeModel() != CodeModel::Kernel">; 780def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 781 "TM.getCodeModel() == CodeModel::Kernel">; 782def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 783def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 784def OptForSize : Predicate<"OptForSize">; 785def OptForSpeed : Predicate<"!OptForSize">; 786def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 787def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 788def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; 789def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">; 790def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 791 792//===----------------------------------------------------------------------===// 793// X86 Instruction Format Definitions. 794// 795 796include "X86InstrFormats.td" 797 798//===----------------------------------------------------------------------===// 799// Pattern fragments. 800// 801 802// X86 specific condition code. These correspond to CondCode in 803// X86InstrInfo.h. They must be kept in synch. 804def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 805def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 806def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 807def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 808def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 809def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 810def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 811def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 812def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 813def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 814def X86_COND_NO : PatLeaf<(i8 10)>; 815def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 816def X86_COND_NS : PatLeaf<(i8 12)>; 817def X86_COND_O : PatLeaf<(i8 13)>; 818def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 819def X86_COND_S : PatLeaf<(i8 15)>; 820 821// Predicate used to help when pattern matching LZCNT/TZCNT. 822def X86_COND_E_OR_NE : ImmLeaf<i8, [{ 823 return (Imm == X86::COND_E) || (Imm == X86::COND_NE); 824}]>; 825 826let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. 827 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 828 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 829 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 830} 831 832def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 833 834 835// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 836// unsigned field. 837def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 838 839def i64immZExt32SExt8 : ImmLeaf<i64, [{ 840 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 841}]>; 842 843// Helper fragments for loads. 844// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 845// known to be 32-bit aligned or better. Ditto for i8 to i16. 846def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 847 LoadSDNode *LD = cast<LoadSDNode>(N); 848 ISD::LoadExtType ExtType = LD->getExtensionType(); 849 if (ExtType == ISD::NON_EXTLOAD) 850 return true; 851 if (ExtType == ISD::EXTLOAD) 852 return LD->getAlignment() >= 2 && !LD->isVolatile(); 853 return false; 854}]>; 855 856def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 857 LoadSDNode *LD = cast<LoadSDNode>(N); 858 ISD::LoadExtType ExtType = LD->getExtensionType(); 859 if (ExtType == ISD::EXTLOAD) 860 return LD->getAlignment() >= 2 && !LD->isVolatile(); 861 return false; 862}]>; 863 864def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 865 LoadSDNode *LD = cast<LoadSDNode>(N); 866 ISD::LoadExtType ExtType = LD->getExtensionType(); 867 if (ExtType == ISD::NON_EXTLOAD) 868 return true; 869 if (ExtType == ISD::EXTLOAD) 870 return LD->getAlignment() >= 4 && !LD->isVolatile(); 871 return false; 872}]>; 873 874def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 875def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 876def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 877def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 878def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 879 880def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 881def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 882def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 883def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 884def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 885def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 886 887def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 888def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 889def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 890def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 891def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 892def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 893def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 894def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 895def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 896def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 897 898def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 899def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 900def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 901def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 902def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 903def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 904def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 905def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 906def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 907def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 908 909 910// An 'and' node with a single use. 911def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 912 return N->hasOneUse(); 913}]>; 914// An 'srl' node with a single use. 915def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 916 return N->hasOneUse(); 917}]>; 918// An 'trunc' node with a single use. 919def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 920 return N->hasOneUse(); 921}]>; 922 923//===----------------------------------------------------------------------===// 924// Instruction list. 925// 926 927// Nop 928let hasSideEffects = 0, SchedRW = [WriteZero] in { 929 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; 930 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 931 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16; 932 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 933 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32; 934} 935 936 937// Constructing a stack frame. 938def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 939 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; 940 941let SchedRW = [WriteALU] in { 942let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 943def LEAVE : I<0xC9, RawFrm, 944 (outs), (ins), "leave", [], IIC_LEAVE>, 945 Requires<[Not64BitMode]>; 946 947let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 948def LEAVE64 : I<0xC9, RawFrm, 949 (outs), (ins), "leave", [], IIC_LEAVE>, 950 Requires<[In64BitMode]>; 951} // SchedRW 952 953//===----------------------------------------------------------------------===// 954// Miscellaneous Instructions. 955// 956 957let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 958let mayLoad = 1, SchedRW = [WriteLoad] in { 959def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 960 IIC_POP_REG16>, OpSize16; 961def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 962 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 963def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 964 IIC_POP_REG>, OpSize16; 965def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], 966 IIC_POP_MEM>, OpSize16; 967def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 968 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 969def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], 970 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; 971} // mayLoad, SchedRW 972 973let mayStore = 1, SchedRW = [WriteStore] in { 974def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 975 IIC_PUSH_REG>, OpSize16; 976def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 977 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 978def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 979 IIC_PUSH_REG>, OpSize16; 980def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], 981 IIC_PUSH_MEM>, OpSize16; 982def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 983 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 984def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], 985 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>; 986 987def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 988 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 989 Requires<[Not64BitMode]>; 990def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 991 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 992 Requires<[Not64BitMode]>; 993def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 994 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 995 Requires<[Not64BitMode]>; 996def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 997 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 998 Requires<[Not64BitMode]>; 999} // mayStore, SchedRW 1000} 1001 1002let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1003 SchedRW = [WriteLoad] in { 1004def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, 1005 OpSize16; 1006def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, 1007 OpSize32, Requires<[Not64BitMode]>; 1008} 1009 1010let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0, 1011 SchedRW = [WriteStore] in { 1012def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, 1013 OpSize16; 1014def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, 1015 OpSize32, Requires<[Not64BitMode]>; 1016} 1017 1018let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1019let mayLoad = 1, SchedRW = [WriteLoad] in { 1020def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1021 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1022def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1023 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1024def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], 1025 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>; 1026} // mayLoad, SchedRW 1027let mayStore = 1, SchedRW = [WriteStore] in { 1028def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1029 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1030def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1031 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1032def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], 1033 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>; 1034} // mayStore, SchedRW 1035} 1036 1037let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1038 SchedRW = [WriteStore] in { 1039def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1040 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>; 1041def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1042 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 1043 Requires<[In64BitMode]>; 1044def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1045 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1046 Requires<[In64BitMode]>; 1047} 1048 1049let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1050def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, 1051 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1052let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in 1053def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, 1054 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1055 1056let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1057 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1058def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, 1059 OpSize32, Requires<[Not64BitMode]>; 1060def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, 1061 OpSize16, Requires<[Not64BitMode]>; 1062} 1063let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1064 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1065def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, 1066 OpSize32, Requires<[Not64BitMode]>; 1067def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, 1068 OpSize16, Requires<[Not64BitMode]>; 1069} 1070 1071let Constraints = "$src = $dst", SchedRW = [WriteALU] in { 1072// GR32 = bswap GR32 1073def BSWAP32r : I<0xC8, AddRegFrm, 1074 (outs GR32:$dst), (ins GR32:$src), 1075 "bswap{l}\t$dst", 1076 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB; 1077 1078def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1079 "bswap{q}\t$dst", 1080 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; 1081} // Constraints = "$src = $dst", SchedRW 1082 1083// Bit scan instructions. 1084let Defs = [EFLAGS] in { 1085def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1086 "bsf{w}\t{$src, $dst|$dst, $src}", 1087 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], 1088 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1089def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1090 "bsf{w}\t{$src, $dst|$dst, $src}", 1091 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], 1092 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1093def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1094 "bsf{l}\t{$src, $dst|$dst, $src}", 1095 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], 1096 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1097def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1098 "bsf{l}\t{$src, $dst|$dst, $src}", 1099 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], 1100 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1101def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1102 "bsf{q}\t{$src, $dst|$dst, $src}", 1103 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], 1104 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1105def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1106 "bsf{q}\t{$src, $dst|$dst, $src}", 1107 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], 1108 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1109 1110def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1111 "bsr{w}\t{$src, $dst|$dst, $src}", 1112 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], 1113 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1114def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1115 "bsr{w}\t{$src, $dst|$dst, $src}", 1116 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], 1117 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1118def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1119 "bsr{l}\t{$src, $dst|$dst, $src}", 1120 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], 1121 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1122def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1123 "bsr{l}\t{$src, $dst|$dst, $src}", 1124 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], 1125 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1126def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1127 "bsr{q}\t{$src, $dst|$dst, $src}", 1128 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], 1129 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1130def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1131 "bsr{q}\t{$src, $dst|$dst, $src}", 1132 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], 1133 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1134} // Defs = [EFLAGS] 1135 1136let SchedRW = [WriteMicrocoded] in { 1137// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1138let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 1139def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src), 1140 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1141def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src), 1142 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16; 1143def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src), 1144 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32; 1145def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src), 1146 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1147} 1148 1149// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1150let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 1151def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins), 1152 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>; 1153let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 1154def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins), 1155 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16; 1156let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 1157def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins), 1158 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32; 1159let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 1160def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins), 1161 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>; 1162 1163// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1164let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in 1165def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1166 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>; 1167let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in 1168def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1169 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16; 1170let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in 1171def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1172 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32; 1173let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in 1174def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1175 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>; 1176 1177// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1178let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in { 1179def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1180 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1181def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1182 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16; 1183def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1184 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32; 1185def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1186 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1187} 1188} // SchedRW 1189 1190//===----------------------------------------------------------------------===// 1191// Move Instructions. 1192// 1193let SchedRW = [WriteMove] in { 1194let hasSideEffects = 0 in { 1195def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1196 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1197def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1198 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1199def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1200 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1201def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1202 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1203} 1204 1205let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1206def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1207 "mov{b}\t{$src, $dst|$dst, $src}", 1208 [(set GR8:$dst, imm:$src)], IIC_MOV>; 1209def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1210 "mov{w}\t{$src, $dst|$dst, $src}", 1211 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16; 1212def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1213 "mov{l}\t{$src, $dst|$dst, $src}", 1214 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32; 1215def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1216 "mov{q}\t{$src, $dst|$dst, $src}", 1217 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; 1218} 1219let isReMaterializable = 1 in { 1220def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1221 "movabs{q}\t{$src, $dst|$dst, $src}", 1222 [(set GR64:$dst, imm:$src)], IIC_MOV>; 1223} 1224 1225// Longer forms that use a ModR/M byte. Needed for disassembler 1226let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1227def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1228 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1229def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1230 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1231def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1232 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1233} 1234} // SchedRW 1235 1236let SchedRW = [WriteStore] in { 1237def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1238 "mov{b}\t{$src, $dst|$dst, $src}", 1239 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>; 1240def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1241 "mov{w}\t{$src, $dst|$dst, $src}", 1242 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16; 1243def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1244 "mov{l}\t{$src, $dst|$dst, $src}", 1245 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32; 1246def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1247 "mov{q}\t{$src, $dst|$dst, $src}", 1248 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; 1249} // SchedRW 1250 1251let hasSideEffects = 0 in { 1252 1253/// Memory offset versions of moves. The immediate is an address mode sized 1254/// offset from the segment base. 1255let SchedRW = [WriteALU] in { 1256let mayLoad = 1 in { 1257let Defs = [AL] in 1258def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1259 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1260 AdSize32; 1261let Defs = [AX] in 1262def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1263 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1264 OpSize16, AdSize32; 1265let Defs = [EAX] in 1266def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1267 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1268 OpSize32, AdSize32; 1269let Defs = [RAX] in 1270def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1271 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>, 1272 AdSize32; 1273 1274let Defs = [AL] in 1275def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1276 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16; 1277let Defs = [AX] in 1278def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1279 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1280 OpSize16, AdSize16; 1281let Defs = [EAX] in 1282def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1283 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1284 AdSize16, OpSize32; 1285} 1286let mayStore = 1 in { 1287let Uses = [AL] in 1288def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins), 1289 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32; 1290let Uses = [AX] in 1291def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins), 1292 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1293 OpSize16, AdSize32; 1294let Uses = [EAX] in 1295def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins), 1296 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1297 OpSize32, AdSize32; 1298let Uses = [RAX] in 1299def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins), 1300 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>, 1301 AdSize32; 1302 1303let Uses = [AL] in 1304def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins), 1305 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16; 1306let Uses = [AX] in 1307def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins), 1308 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1309 OpSize16, AdSize16; 1310let Uses = [EAX] in 1311def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins), 1312 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1313 OpSize32, AdSize16; 1314} 1315} 1316 1317// These forms all have full 64-bit absolute addresses in their instructions 1318// and use the movabs mnemonic to indicate this specific form. 1319let mayLoad = 1 in { 1320let Defs = [AL] in 1321def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1322 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64; 1323let Defs = [AX] in 1324def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1325 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64; 1326let Defs = [EAX] in 1327def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1328 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, 1329 AdSize64; 1330let Defs = [RAX] in 1331def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1332 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64; 1333} 1334 1335let mayStore = 1 in { 1336let Uses = [AL] in 1337def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins), 1338 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64; 1339let Uses = [AX] in 1340def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins), 1341 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64; 1342let Uses = [EAX] in 1343def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins), 1344 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, 1345 AdSize64; 1346let Uses = [RAX] in 1347def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins), 1348 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64; 1349} 1350} // hasSideEffects = 0 1351 1352let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1353 SchedRW = [WriteMove] in { 1354def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1355 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1356def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1357 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1358def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1359 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1360def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1361 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1362} 1363 1364let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1365def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1366 "mov{b}\t{$src, $dst|$dst, $src}", 1367 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; 1368def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1369 "mov{w}\t{$src, $dst|$dst, $src}", 1370 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16; 1371def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1372 "mov{l}\t{$src, $dst|$dst, $src}", 1373 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; 1374def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1375 "mov{q}\t{$src, $dst|$dst, $src}", 1376 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; 1377} 1378 1379let SchedRW = [WriteStore] in { 1380def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1381 "mov{b}\t{$src, $dst|$dst, $src}", 1382 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; 1383def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1384 "mov{w}\t{$src, $dst|$dst, $src}", 1385 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; 1386def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1387 "mov{l}\t{$src, $dst|$dst, $src}", 1388 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; 1389def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1390 "mov{q}\t{$src, $dst|$dst, $src}", 1391 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; 1392} // SchedRW 1393 1394// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1395// that they can be used for copying and storing h registers, which can't be 1396// encoded when a REX prefix is present. 1397let isCodeGenOnly = 1 in { 1398let hasSideEffects = 0 in 1399def MOV8rr_NOREX : I<0x88, MRMDestReg, 1400 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1401 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, 1402 Sched<[WriteMove]>; 1403let mayStore = 1, hasSideEffects = 0 in 1404def MOV8mr_NOREX : I<0x88, MRMDestMem, 1405 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1406 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1407 IIC_MOV_MEM>, Sched<[WriteStore]>; 1408let mayLoad = 1, hasSideEffects = 0, 1409 canFoldAsLoad = 1, isReMaterializable = 1 in 1410def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1411 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1412 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1413 IIC_MOV_MEM>, Sched<[WriteLoad]>; 1414} 1415 1416 1417// Condition code ops, incl. set if equal/not equal/... 1418let SchedRW = [WriteALU] in { 1419let Defs = [EFLAGS], Uses = [AH] in 1420def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1421 [(set EFLAGS, (X86sahf AH))], IIC_AHF>; 1422let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1423def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], 1424 IIC_AHF>; // AH = flags 1425} // SchedRW 1426 1427//===----------------------------------------------------------------------===// 1428// Bit tests instructions: BT, BTS, BTR, BTC. 1429 1430let Defs = [EFLAGS] in { 1431let SchedRW = [WriteALU] in { 1432def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1433 "bt{w}\t{$src2, $src1|$src1, $src2}", 1434 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, 1435 OpSize16, TB; 1436def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1437 "bt{l}\t{$src2, $src1|$src1, $src2}", 1438 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, 1439 OpSize32, TB; 1440def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1441 "bt{q}\t{$src2, $src1|$src1, $src2}", 1442 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; 1443} // SchedRW 1444 1445// Unlike with the register+register form, the memory+register form of the 1446// bt instruction does not ignore the high bits of the index. From ISel's 1447// perspective, this is pretty bizarre. Make these instructions disassembly 1448// only for now. 1449 1450let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1451 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1452 "bt{w}\t{$src2, $src1|$src1, $src2}", 1453 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1454 // (implicit EFLAGS)] 1455 [], IIC_BT_MR 1456 >, OpSize16, TB, Requires<[FastBTMem]>; 1457 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1458 "bt{l}\t{$src2, $src1|$src1, $src2}", 1459 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1460 // (implicit EFLAGS)] 1461 [], IIC_BT_MR 1462 >, OpSize32, TB, Requires<[FastBTMem]>; 1463 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1464 "bt{q}\t{$src2, $src1|$src1, $src2}", 1465 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1466 // (implicit EFLAGS)] 1467 [], IIC_BT_MR 1468 >, TB; 1469} 1470 1471let SchedRW = [WriteALU] in { 1472def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1473 "bt{w}\t{$src2, $src1|$src1, $src2}", 1474 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], 1475 IIC_BT_RI>, OpSize16, TB; 1476def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1477 "bt{l}\t{$src2, $src1|$src1, $src2}", 1478 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], 1479 IIC_BT_RI>, OpSize32, TB; 1480def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1481 "bt{q}\t{$src2, $src1|$src1, $src2}", 1482 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], 1483 IIC_BT_RI>, TB; 1484} // SchedRW 1485 1486// Note that these instructions don't need FastBTMem because that 1487// only applies when the other operand is in a register. When it's 1488// an immediate, bt is still fast. 1489let SchedRW = [WriteALU] in { 1490def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1491 "bt{w}\t{$src2, $src1|$src1, $src2}", 1492 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1493 ], IIC_BT_MI>, OpSize16, TB; 1494def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1495 "bt{l}\t{$src2, $src1|$src1, $src2}", 1496 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1497 ], IIC_BT_MI>, OpSize32, TB; 1498def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1499 "bt{q}\t{$src2, $src1|$src1, $src2}", 1500 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1501 i64immSExt8:$src2))], IIC_BT_MI>, TB; 1502} // SchedRW 1503 1504let hasSideEffects = 0 in { 1505let SchedRW = [WriteALU] in { 1506def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1507 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1508 OpSize16, TB; 1509def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1510 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1511 OpSize32, TB; 1512def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1513 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1514} // SchedRW 1515 1516let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1517def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1518 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1519 OpSize16, TB; 1520def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1521 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1522 OpSize32, TB; 1523def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1524 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1525} 1526 1527let SchedRW = [WriteALU] in { 1528def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1529 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1530 OpSize16, TB; 1531def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1532 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1533 OpSize32, TB; 1534def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1535 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1536} // SchedRW 1537 1538let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1539def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1540 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1541 OpSize16, TB; 1542def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1543 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1544 OpSize32, TB; 1545def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1546 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1547} 1548 1549let SchedRW = [WriteALU] in { 1550def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1551 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1552 OpSize16, TB; 1553def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1554 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1555 OpSize32, TB; 1556def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1557 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1558} // SchedRW 1559 1560let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1561def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1562 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1563 OpSize16, TB; 1564def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1565 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1566 OpSize32, TB; 1567def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1568 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1569} 1570 1571let SchedRW = [WriteALU] in { 1572def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1573 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1574 OpSize16, TB; 1575def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1576 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1577 OpSize32, TB; 1578def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1579 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1580} // SchedRW 1581 1582let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1583def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1584 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1585 OpSize16, TB; 1586def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1587 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1588 OpSize32, TB; 1589def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1590 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1591} 1592 1593let SchedRW = [WriteALU] in { 1594def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1595 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1596 OpSize16, TB; 1597def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1598 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1599 OpSize32, TB; 1600def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1601 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1602} // SchedRW 1603 1604let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1605def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1606 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1607 OpSize16, TB; 1608def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1609 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1610 OpSize32, TB; 1611def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1612 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1613} 1614 1615let SchedRW = [WriteALU] in { 1616def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1617 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1618 OpSize16, TB; 1619def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1620 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1621 OpSize32, TB; 1622def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1623 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1624} // SchedRW 1625 1626let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1627def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1628 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1629 OpSize16, TB; 1630def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1631 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1632 OpSize32, TB; 1633def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1634 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1635} 1636} // hasSideEffects = 0 1637} // Defs = [EFLAGS] 1638 1639 1640//===----------------------------------------------------------------------===// 1641// Atomic support 1642// 1643 1644// Atomic swap. These are just normal xchg instructions. But since a memory 1645// operand is referenced, the atomicity is ensured. 1646multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, 1647 InstrItinClass itin> { 1648 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 1649 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 1650 (ins GR8:$val, i8mem:$ptr), 1651 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1652 [(set 1653 GR8:$dst, 1654 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 1655 itin>; 1656 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 1657 (ins GR16:$val, i16mem:$ptr), 1658 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1659 [(set 1660 GR16:$dst, 1661 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 1662 itin>, OpSize16; 1663 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 1664 (ins GR32:$val, i32mem:$ptr), 1665 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1666 [(set 1667 GR32:$dst, 1668 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 1669 itin>, OpSize32; 1670 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 1671 (ins GR64:$val, i64mem:$ptr), 1672 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1673 [(set 1674 GR64:$dst, 1675 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 1676 itin>; 1677 } 1678} 1679 1680defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; 1681 1682// Swap between registers. 1683let SchedRW = [WriteALU] in { 1684let Constraints = "$val = $dst" in { 1685def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1686 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1687def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1688 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1689 OpSize16; 1690def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1691 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1692 OpSize32; 1693def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1694 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1695} 1696 1697// Swap between EAX and other registers. 1698let Uses = [AX], Defs = [AX] in 1699def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1700 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; 1701let Uses = [EAX], Defs = [EAX] in 1702def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1703 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1704 OpSize32, Requires<[Not64BitMode]>; 1705let Uses = [EAX], Defs = [EAX] in 1706// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1707// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1708def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1709 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1710 OpSize32, Requires<[In64BitMode]>; 1711let Uses = [RAX], Defs = [RAX] in 1712def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1713 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; 1714} // SchedRW 1715 1716let SchedRW = [WriteALU] in { 1717def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1718 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1719def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1720 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1721 OpSize16; 1722def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1723 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1724 OpSize32; 1725def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1726 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1727} // SchedRW 1728 1729let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1730def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1731 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1732def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1733 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1734 OpSize16; 1735def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1736 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1737 OpSize32; 1738def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1739 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1740 1741} 1742 1743let SchedRW = [WriteALU] in { 1744def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1745 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1746 IIC_CMPXCHG_REG8>, TB; 1747def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1748 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1749 IIC_CMPXCHG_REG>, TB, OpSize16; 1750def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1751 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1752 IIC_CMPXCHG_REG>, TB, OpSize32; 1753def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1754 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1755 IIC_CMPXCHG_REG>, TB; 1756} // SchedRW 1757 1758let SchedRW = [WriteALULd, WriteRMW] in { 1759let mayLoad = 1, mayStore = 1 in { 1760def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1761 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1762 IIC_CMPXCHG_MEM8>, TB; 1763def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1764 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1765 IIC_CMPXCHG_MEM>, TB, OpSize16; 1766def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1767 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1768 IIC_CMPXCHG_MEM>, TB, OpSize32; 1769def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1770 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1771 IIC_CMPXCHG_MEM>, TB; 1772} 1773 1774let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1775def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1776 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; 1777 1778let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1779def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1780 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, 1781 TB, Requires<[HasCmpxchg16b]>; 1782} // SchedRW 1783 1784 1785// Lock instruction prefix 1786def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1787 1788// Rex64 instruction prefix 1789def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 1790 Requires<[In64BitMode]>; 1791 1792// Data16 instruction prefix 1793def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1794 1795// Repeat string operation instruction prefixes 1796// These uses the DF flag in the EFLAGS register to inc or dec ECX 1797let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1798// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1799def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1800// Repeat while not equal (used with CMPS and SCAS) 1801def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1802} 1803 1804 1805// String manipulation instructions 1806let SchedRW = [WriteMicrocoded] in { 1807// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1808let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in 1809def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 1810 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>; 1811let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in 1812def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 1813 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16; 1814let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in 1815def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 1816 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32; 1817let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in 1818def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 1819 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>; 1820} 1821 1822let SchedRW = [WriteSystem] in { 1823// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1824let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in { 1825def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 1826 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>; 1827def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 1828 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16; 1829def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 1830 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32; 1831} 1832 1833// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1834let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in { 1835def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins), 1836 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>; 1837def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins), 1838 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16; 1839def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins), 1840 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32; 1841} 1842} 1843 1844// Flag instructions 1845let SchedRW = [WriteALU] in { 1846def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; 1847def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; 1848def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; 1849def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; 1850def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; 1851def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; 1852def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; 1853 1854def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; 1855} 1856 1857// Table lookup instructions 1858def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, 1859 Sched<[WriteLoad]>; 1860 1861let SchedRW = [WriteMicrocoded] in { 1862// ASCII Adjust After Addition 1863// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1864def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, 1865 Requires<[Not64BitMode]>; 1866 1867// ASCII Adjust AX Before Division 1868// sets AL, AH and EFLAGS and uses AL and AH 1869def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1870 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>; 1871 1872// ASCII Adjust AX After Multiply 1873// sets AL, AH and EFLAGS and uses AL 1874def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1875 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>; 1876 1877// ASCII Adjust AL After Subtraction - sets 1878// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1879def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, 1880 Requires<[Not64BitMode]>; 1881 1882// Decimal Adjust AL after Addition 1883// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1884def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, 1885 Requires<[Not64BitMode]>; 1886 1887// Decimal Adjust AL after Subtraction 1888// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1889def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, 1890 Requires<[Not64BitMode]>; 1891} // SchedRW 1892 1893let SchedRW = [WriteSystem] in { 1894// Check Array Index Against Bounds 1895def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1896 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16, 1897 Requires<[Not64BitMode]>; 1898def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1899 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32, 1900 Requires<[Not64BitMode]>; 1901 1902// Adjust RPL Field of Segment Selector 1903def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1904 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, 1905 Requires<[Not64BitMode]>; 1906def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1907 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, 1908 Requires<[Not64BitMode]>; 1909} // SchedRW 1910 1911//===----------------------------------------------------------------------===// 1912// MOVBE Instructions 1913// 1914let Predicates = [HasMOVBE] in { 1915 let SchedRW = [WriteALULd] in { 1916 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1917 "movbe{w}\t{$src, $dst|$dst, $src}", 1918 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, 1919 OpSize16, T8PS; 1920 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1921 "movbe{l}\t{$src, $dst|$dst, $src}", 1922 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, 1923 OpSize32, T8PS; 1924 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1925 "movbe{q}\t{$src, $dst|$dst, $src}", 1926 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, 1927 T8PS; 1928 } 1929 let SchedRW = [WriteStore] in { 1930 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1931 "movbe{w}\t{$src, $dst|$dst, $src}", 1932 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, 1933 OpSize16, T8PS; 1934 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1935 "movbe{l}\t{$src, $dst|$dst, $src}", 1936 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, 1937 OpSize32, T8PS; 1938 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1939 "movbe{q}\t{$src, $dst|$dst, $src}", 1940 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, 1941 T8PS; 1942 } 1943} 1944 1945//===----------------------------------------------------------------------===// 1946// RDRAND Instruction 1947// 1948let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 1949 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1950 "rdrand{w}\t$dst", 1951 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB; 1952 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1953 "rdrand{l}\t$dst", 1954 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB; 1955 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1956 "rdrand{q}\t$dst", 1957 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; 1958} 1959 1960//===----------------------------------------------------------------------===// 1961// RDSEED Instruction 1962// 1963let Predicates = [HasRDSEED], Defs = [EFLAGS] in { 1964 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), 1965 "rdseed{w}\t$dst", 1966 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB; 1967 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 1968 "rdseed{l}\t$dst", 1969 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB; 1970 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), 1971 "rdseed{q}\t$dst", 1972 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB; 1973} 1974 1975//===----------------------------------------------------------------------===// 1976// LZCNT Instruction 1977// 1978let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 1979 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1980 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1981 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 1982 OpSize16; 1983 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1984 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1985 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 1986 (implicit EFLAGS)]>, XS, OpSize16; 1987 1988 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1989 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1990 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS, 1991 OpSize32; 1992 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1993 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1994 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 1995 (implicit EFLAGS)]>, XS, OpSize32; 1996 1997 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1998 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1999 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2000 XS; 2001 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2002 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2003 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2004 (implicit EFLAGS)]>, XS; 2005} 2006 2007let Predicates = [HasLZCNT] in { 2008 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2009 (X86cmp GR16:$src, (i16 0))), 2010 (LZCNT16rr GR16:$src)>; 2011 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2012 (X86cmp GR32:$src, (i32 0))), 2013 (LZCNT32rr GR32:$src)>; 2014 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2015 (X86cmp GR64:$src, (i64 0))), 2016 (LZCNT64rr GR64:$src)>; 2017 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE), 2018 (X86cmp GR16:$src, (i16 0))), 2019 (LZCNT16rr GR16:$src)>; 2020 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE), 2021 (X86cmp GR32:$src, (i32 0))), 2022 (LZCNT32rr GR32:$src)>; 2023 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE), 2024 (X86cmp GR64:$src, (i64 0))), 2025 (LZCNT64rr GR64:$src)>; 2026 2027 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2028 (X86cmp (loadi16 addr:$src), (i16 0))), 2029 (LZCNT16rm addr:$src)>; 2030 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2031 (X86cmp (loadi32 addr:$src), (i32 0))), 2032 (LZCNT32rm addr:$src)>; 2033 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2034 (X86cmp (loadi64 addr:$src), (i64 0))), 2035 (LZCNT64rm addr:$src)>; 2036 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2037 (X86cmp (loadi16 addr:$src), (i16 0))), 2038 (LZCNT16rm addr:$src)>; 2039 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2040 (X86cmp (loadi32 addr:$src), (i32 0))), 2041 (LZCNT32rm addr:$src)>; 2042 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2043 (X86cmp (loadi64 addr:$src), (i64 0))), 2044 (LZCNT64rm addr:$src)>; 2045} 2046 2047//===----------------------------------------------------------------------===// 2048// BMI Instructions 2049// 2050let Predicates = [HasBMI], Defs = [EFLAGS] in { 2051 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2052 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2053 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 2054 OpSize16; 2055 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2056 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2057 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2058 (implicit EFLAGS)]>, XS, OpSize16; 2059 2060 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2061 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2062 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS, 2063 OpSize32; 2064 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2065 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2066 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2067 (implicit EFLAGS)]>, XS, OpSize32; 2068 2069 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2070 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2071 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2072 XS; 2073 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2074 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2075 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2076 (implicit EFLAGS)]>, XS; 2077} 2078 2079multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2080 RegisterClass RC, X86MemOperand x86memop> { 2081let hasSideEffects = 0 in { 2082 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2083 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2084 []>, T8PS, VEX_4V; 2085 let mayLoad = 1 in 2086 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2087 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2088 []>, T8PS, VEX_4V; 2089} 2090} 2091 2092let Predicates = [HasBMI], Defs = [EFLAGS] in { 2093 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2094 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2095 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2096 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2097 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2098 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2099} 2100 2101//===----------------------------------------------------------------------===// 2102// Pattern fragments to auto generate BMI instructions. 2103//===----------------------------------------------------------------------===// 2104 2105let Predicates = [HasBMI] in { 2106 // FIXME: patterns for the load versions are not implemented 2107 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2108 (BLSR32rr GR32:$src)>; 2109 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2110 (BLSR64rr GR64:$src)>; 2111 2112 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2113 (BLSMSK32rr GR32:$src)>; 2114 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2115 (BLSMSK64rr GR64:$src)>; 2116 2117 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2118 (BLSI32rr GR32:$src)>; 2119 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2120 (BLSI64rr GR64:$src)>; 2121} 2122 2123let Predicates = [HasBMI] in { 2124 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2125 (X86cmp GR16:$src, (i16 0))), 2126 (TZCNT16rr GR16:$src)>; 2127 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2128 (X86cmp GR32:$src, (i32 0))), 2129 (TZCNT32rr GR32:$src)>; 2130 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2131 (X86cmp GR64:$src, (i64 0))), 2132 (TZCNT64rr GR64:$src)>; 2133 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE), 2134 (X86cmp GR16:$src, (i16 0))), 2135 (TZCNT16rr GR16:$src)>; 2136 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE), 2137 (X86cmp GR32:$src, (i32 0))), 2138 (TZCNT32rr GR32:$src)>; 2139 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE), 2140 (X86cmp GR64:$src, (i64 0))), 2141 (TZCNT64rr GR64:$src)>; 2142 2143 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2144 (X86cmp (loadi16 addr:$src), (i16 0))), 2145 (TZCNT16rm addr:$src)>; 2146 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2147 (X86cmp (loadi32 addr:$src), (i32 0))), 2148 (TZCNT32rm addr:$src)>; 2149 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2150 (X86cmp (loadi64 addr:$src), (i64 0))), 2151 (TZCNT64rm addr:$src)>; 2152 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2153 (X86cmp (loadi16 addr:$src), (i16 0))), 2154 (TZCNT16rm addr:$src)>; 2155 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2156 (X86cmp (loadi32 addr:$src), (i32 0))), 2157 (TZCNT32rm addr:$src)>; 2158 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2159 (X86cmp (loadi64 addr:$src), (i64 0))), 2160 (TZCNT64rm addr:$src)>; 2161} 2162 2163 2164multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2165 X86MemOperand x86memop, Intrinsic Int, 2166 PatFrag ld_frag> { 2167 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2168 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2169 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2170 T8PS, VEX_4VOp3; 2171 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2172 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2173 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2174 (implicit EFLAGS)]>, T8PS, VEX_4VOp3; 2175} 2176 2177let Predicates = [HasBMI], Defs = [EFLAGS] in { 2178 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 2179 int_x86_bmi_bextr_32, loadi32>; 2180 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 2181 int_x86_bmi_bextr_64, loadi64>, VEX_W; 2182} 2183 2184let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2185 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2186 int_x86_bmi_bzhi_32, loadi32>; 2187 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2188 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 2189} 2190 2191 2192def CountTrailingOnes : SDNodeXForm<imm, [{ 2193 // Count the trailing ones in the immediate. 2194 return getI8Imm(CountTrailingOnes_64(N->getZExtValue())); 2195}]>; 2196 2197def BZHIMask : ImmLeaf<i64, [{ 2198 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32); 2199}]>; 2200 2201let Predicates = [HasBMI2] in { 2202 def : Pat<(and GR64:$src, BZHIMask:$mask), 2203 (BZHI64rr GR64:$src, 2204 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2205 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2206 2207 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)), 2208 (BZHI32rr GR32:$src, 2209 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2210 2211 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)), 2212 (BZHI32rm addr:$src, 2213 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2214 2215 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)), 2216 (BZHI64rr GR64:$src, 2217 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2218 2219 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)), 2220 (BZHI64rm addr:$src, 2221 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2222} // HasBMI2 2223 2224let Predicates = [HasBMI] in { 2225 def : Pat<(X86bextr GR32:$src1, GR32:$src2), 2226 (BEXTR32rr GR32:$src1, GR32:$src2)>; 2227 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2), 2228 (BEXTR32rm addr:$src1, GR32:$src2)>; 2229 def : Pat<(X86bextr GR64:$src1, GR64:$src2), 2230 (BEXTR64rr GR64:$src1, GR64:$src2)>; 2231 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2), 2232 (BEXTR64rm addr:$src1, GR64:$src2)>; 2233} // HasBMI 2234 2235multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2236 X86MemOperand x86memop, Intrinsic Int, 2237 PatFrag ld_frag> { 2238 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2239 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2240 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2241 VEX_4V; 2242 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2243 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2244 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 2245} 2246 2247let Predicates = [HasBMI2] in { 2248 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2249 int_x86_bmi_pdep_32, loadi32>, T8XD; 2250 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2251 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2252 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2253 int_x86_bmi_pext_32, loadi32>, T8XS; 2254 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2255 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2256} 2257 2258//===----------------------------------------------------------------------===// 2259// TBM Instructions 2260// 2261let Predicates = [HasTBM], Defs = [EFLAGS] in { 2262 2263multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr, 2264 X86MemOperand x86memop, PatFrag ld_frag, 2265 Intrinsic Int, Operand immtype, 2266 SDPatternOperator immoperator> { 2267 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2268 !strconcat(OpcodeStr, 2269 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2270 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>, 2271 XOP, XOPA; 2272 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2273 (ins x86memop:$src1, immtype:$cntl), 2274 !strconcat(OpcodeStr, 2275 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2276 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>, 2277 XOP, XOPA; 2278} 2279 2280defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, 2281 int_x86_tbm_bextri_u32, i32imm, imm>; 2282let ImmT = Imm32S in 2283defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, 2284 int_x86_tbm_bextri_u64, i64i32imm, 2285 i64immSExt32>, VEX_W; 2286 2287multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2288 RegisterClass RC, string OpcodeStr, 2289 X86MemOperand x86memop, PatFrag ld_frag> { 2290let hasSideEffects = 0 in { 2291 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2292 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2293 []>, XOP_4V, XOP9; 2294 let mayLoad = 1 in 2295 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2296 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2297 []>, XOP_4V, XOP9; 2298} 2299} 2300 2301multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2302 Format FormReg, Format FormMem> { 2303 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem, 2304 loadi32>; 2305 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem, 2306 loadi64>, VEX_W; 2307} 2308 2309defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>; 2310defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>; 2311defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>; 2312defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>; 2313defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>; 2314defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>; 2315defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>; 2316defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>; 2317defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>; 2318} // HasTBM, EFLAGS 2319 2320//===----------------------------------------------------------------------===// 2321// Pattern fragments to auto generate TBM instructions. 2322//===----------------------------------------------------------------------===// 2323 2324let Predicates = [HasTBM] in { 2325 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), 2326 (BEXTRI32ri GR32:$src1, imm:$src2)>; 2327 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), 2328 (BEXTRI32mi addr:$src1, imm:$src2)>; 2329 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2), 2330 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>; 2331 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2), 2332 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>; 2333 2334 // FIXME: patterns for the load versions are not implemented 2335 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2336 (BLCFILL32rr GR32:$src)>; 2337 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2338 (BLCFILL64rr GR64:$src)>; 2339 2340 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2341 (BLCI32rr GR32:$src)>; 2342 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2343 (BLCI64rr GR64:$src)>; 2344 2345 // Extra patterns because opt can optimize the above patterns to this. 2346 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2347 (BLCI32rr GR32:$src)>; 2348 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2349 (BLCI64rr GR64:$src)>; 2350 2351 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2352 (BLCIC32rr GR32:$src)>; 2353 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2354 (BLCIC64rr GR64:$src)>; 2355 2356 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2357 (BLCMSK32rr GR32:$src)>; 2358 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2359 (BLCMSK64rr GR64:$src)>; 2360 2361 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2362 (BLCS32rr GR32:$src)>; 2363 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2364 (BLCS64rr GR64:$src)>; 2365 2366 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2367 (BLSFILL32rr GR32:$src)>; 2368 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2369 (BLSFILL64rr GR64:$src)>; 2370 2371 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2372 (BLSIC32rr GR32:$src)>; 2373 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2374 (BLSIC64rr GR64:$src)>; 2375 2376 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2377 (T1MSKC32rr GR32:$src)>; 2378 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2379 (T1MSKC64rr GR64:$src)>; 2380 2381 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2382 (TZMSK32rr GR32:$src)>; 2383 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2384 (TZMSK64rr GR64:$src)>; 2385} // HasTBM 2386 2387//===----------------------------------------------------------------------===// 2388// Subsystems. 2389//===----------------------------------------------------------------------===// 2390 2391include "X86InstrArithmetic.td" 2392include "X86InstrCMovSetCC.td" 2393include "X86InstrExtension.td" 2394include "X86InstrControl.td" 2395include "X86InstrShiftRotate.td" 2396 2397// X87 Floating Point Stack. 2398include "X86InstrFPStack.td" 2399 2400// SIMD support (SSE, MMX and AVX) 2401include "X86InstrFragmentsSIMD.td" 2402 2403// FMA - Fused Multiply-Add support (requires FMA) 2404include "X86InstrFMA.td" 2405 2406// XOP 2407include "X86InstrXOP.td" 2408 2409// SSE, MMX and 3DNow! vector support. 2410include "X86InstrSSE.td" 2411include "X86InstrAVX512.td" 2412include "X86InstrMMX.td" 2413include "X86Instr3DNow.td" 2414 2415include "X86InstrVMX.td" 2416include "X86InstrSVM.td" 2417 2418include "X86InstrTSX.td" 2419include "X86InstrSGX.td" 2420 2421// System instructions. 2422include "X86InstrSystem.td" 2423 2424// Compiler Pseudo Instructions and Pat Patterns 2425include "X86InstrCompiler.td" 2426 2427//===----------------------------------------------------------------------===// 2428// Assembler Mnemonic Aliases 2429//===----------------------------------------------------------------------===// 2430 2431def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 2432def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 2433def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 2434 2435def : MnemonicAlias<"cbw", "cbtw", "att">; 2436def : MnemonicAlias<"cwde", "cwtl", "att">; 2437def : MnemonicAlias<"cwd", "cwtd", "att">; 2438def : MnemonicAlias<"cdq", "cltd", "att">; 2439def : MnemonicAlias<"cdqe", "cltq", "att">; 2440def : MnemonicAlias<"cqo", "cqto", "att">; 2441 2442// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 2443def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 2444def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 2445 2446def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 2447def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 2448 2449def : MnemonicAlias<"loopz", "loope", "att">; 2450def : MnemonicAlias<"loopnz", "loopne", "att">; 2451 2452def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 2453def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 2454def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 2455def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 2456def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 2457def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 2458def : MnemonicAlias<"popfd", "popfl", "att">; 2459 2460// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 2461// all modes. However: "push (addr)" and "push $42" should default to 2462// pushl/pushq depending on the current mode. Similar for "pop %bx" 2463def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 2464def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 2465def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 2466def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 2467def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 2468def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 2469def : MnemonicAlias<"pushfd", "pushfl", "att">; 2470 2471def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 2472def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 2473def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 2474def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 2475def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 2476def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 2477 2478def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 2479def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 2480def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 2481def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 2482 2483def : MnemonicAlias<"repe", "rep", "att">; 2484def : MnemonicAlias<"repz", "rep", "att">; 2485def : MnemonicAlias<"repnz", "repne", "att">; 2486 2487def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 2488def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 2489def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 2490 2491def : MnemonicAlias<"salb", "shlb", "att">; 2492def : MnemonicAlias<"salw", "shlw", "att">; 2493def : MnemonicAlias<"sall", "shll", "att">; 2494def : MnemonicAlias<"salq", "shlq", "att">; 2495 2496def : MnemonicAlias<"smovb", "movsb", "att">; 2497def : MnemonicAlias<"smovw", "movsw", "att">; 2498def : MnemonicAlias<"smovl", "movsl", "att">; 2499def : MnemonicAlias<"smovq", "movsq", "att">; 2500 2501def : MnemonicAlias<"ud2a", "ud2", "att">; 2502def : MnemonicAlias<"verrw", "verr", "att">; 2503 2504// System instruction aliases. 2505def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 2506def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 2507def : MnemonicAlias<"sysret", "sysretl", "att">; 2508def : MnemonicAlias<"sysexit", "sysexitl", "att">; 2509 2510def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 2511def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 2512def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 2513def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 2514def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 2515def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 2516def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 2517def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 2518def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 2519def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 2520def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 2521def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 2522 2523 2524// Floating point stack aliases. 2525def : MnemonicAlias<"fcmovz", "fcmove", "att">; 2526def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 2527def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 2528def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 2529def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 2530def : MnemonicAlias<"fcomip", "fcompi", "att">; 2531def : MnemonicAlias<"fildq", "fildll", "att">; 2532def : MnemonicAlias<"fistpq", "fistpll", "att">; 2533def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 2534def : MnemonicAlias<"fldcww", "fldcw", "att">; 2535def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 2536def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 2537def : MnemonicAlias<"fucomip", "fucompi", "att">; 2538def : MnemonicAlias<"fwait", "wait">; 2539 2540 2541class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 2542 string VariantName> 2543 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 2544 !strconcat(Prefix, NewCond, Suffix), VariantName>; 2545 2546/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 2547/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 2548/// example "setz" -> "sete". 2549multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 2550 string V = ""> { 2551 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 2552 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 2553 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 2554 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 2555 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 2556 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 2557 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 2558 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 2559 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 2560 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 2561 2562 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 2563 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 2564 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 2565 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 2566} 2567 2568// Aliases for set<CC> 2569defm : IntegerCondCodeMnemonicAlias<"set", "">; 2570// Aliases for j<CC> 2571defm : IntegerCondCodeMnemonicAlias<"j", "">; 2572// Aliases for cmov<CC>{w,l,q} 2573defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 2574defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 2575defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 2576// No size suffix for intel-style asm. 2577defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 2578 2579 2580//===----------------------------------------------------------------------===// 2581// Assembler Instruction Aliases 2582//===----------------------------------------------------------------------===// 2583 2584// aad/aam default to base 10 if no operand is specified. 2585def : InstAlias<"aad", (AAD8i8 10)>; 2586def : InstAlias<"aam", (AAM8i8 10)>; 2587 2588// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 2589// Likewise for btc/btr/bts. 2590def : InstAlias<"bt {$imm, $mem|$mem, $imm}", 2591 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2592def : InstAlias<"btc {$imm, $mem|$mem, $imm}", 2593 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2594def : InstAlias<"btr {$imm, $mem|$mem, $imm}", 2595 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2596def : InstAlias<"bts {$imm, $mem|$mem, $imm}", 2597 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2598 2599// clr aliases. 2600def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 2601def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 2602def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 2603def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 2604 2605// lods aliases. Accept the destination being omitted because it's implicit 2606// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2607// in the destination. 2608def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>; 2609def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>; 2610def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>; 2611def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2612def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 2613def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 2614def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 2615def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2616 2617// stos aliases. Accept the source being omitted because it's implicit in 2618// the mnemonic, or the mnemonic suffix being omitted because it's implicit 2619// in the source. 2620def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>; 2621def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>; 2622def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>; 2623def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2624def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 2625def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 2626def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 2627def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2628 2629// scas aliases. Accept the destination being omitted because it's implicit 2630// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2631// in the destination. 2632def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>; 2633def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>; 2634def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>; 2635def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2636def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 2637def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 2638def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 2639def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2640 2641// div and idiv aliases for explicit A register. 2642def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 2643def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 2644def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 2645def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 2646def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 2647def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 2648def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 2649def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 2650def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 2651def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 2652def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 2653def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 2654def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 2655def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 2656def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 2657def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 2658 2659 2660 2661// Various unary fpstack operations default to operating on on ST1. 2662// For example, "fxch" -> "fxch %st(1)" 2663def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 2664def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 2665def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 2666def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 2667def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 2668def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 2669def : InstAlias<"fxch", (XCH_F ST1), 0>; 2670def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 2671def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 2672def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 2673def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 2674def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 2675def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 2676def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 2677def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 2678 2679// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 2680// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 2681// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 2682// gas. 2683multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 2684 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 2685 (Inst RST:$op), EmitAlias>; 2686 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 2687 (Inst ST0), EmitAlias>; 2688} 2689 2690defm : FpUnaryAlias<"fadd", ADD_FST0r>; 2691defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 2692defm : FpUnaryAlias<"fsub", SUB_FST0r>; 2693defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 2694defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 2695defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 2696defm : FpUnaryAlias<"fmul", MUL_FST0r>; 2697defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 2698defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 2699defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 2700defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 2701defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 2702defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 2703defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 2704defm : FpUnaryAlias<"fcompi", COM_FIPr>; 2705defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 2706 2707 2708// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 2709// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 2710// solely because gas supports it. 2711def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 2712def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 2713def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 2714def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 2715def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 2716def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 2717 2718// We accept "fnstsw %eax" even though it only writes %ax. 2719def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>; 2720def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>; 2721def : InstAlias<"fnstsw" , (FNSTSW16r)>; 2722 2723// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 2724// this is compatible with what GAS does. 2725def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2726def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2727def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2728def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2729def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2730def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2731def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2732def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2733 2734def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2735def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2736def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2737def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2738def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2739def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2740 2741 2742// "imul <imm>, B" is an alias for "imul <imm>, B, B". 2743def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 2744def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 2745def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 2746def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 2747def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 2748def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 2749 2750// inb %dx -> inb %al, %dx 2751def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 2752def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 2753def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 2754def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>; 2755def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>; 2756def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>; 2757 2758 2759// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 2760def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2761def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2762def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2763def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2764def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 2765def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 2766def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2767def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2768 2769// Force mov without a suffix with a segment and mem to prefer the 'l' form of 2770// the move. All segment/mem forms are equivalent, this has the shortest 2771// encoding. 2772def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; 2773def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; 2774 2775// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 2776def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 2777 2778// Match 'movq GR64, MMX' as an alias for movd. 2779def : InstAlias<"movq {$src, $dst|$dst, $src}", 2780 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 2781def : InstAlias<"movq {$src, $dst|$dst, $src}", 2782 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 2783 2784// movsx aliases 2785def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 2786def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 2787def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 2788def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 2789def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 2790def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 2791def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 2792 2793// movzx aliases 2794def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 2795def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 2796def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 2797def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 2798def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 2799def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 2800// Note: No GR32->GR64 movzx form. 2801 2802// outb %dx -> outb %al, %dx 2803def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 2804def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 2805def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 2806def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>; 2807def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>; 2808def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>; 2809 2810// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 2811// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 2812// errors, since its encoding is the most compact. 2813def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 2814 2815// shld/shrd op,op -> shld op, op, CL 2816def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 2817def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 2818def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 2819def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 2820def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 2821def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 2822 2823def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 2824def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 2825def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 2826def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 2827def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 2828def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 2829 2830/* FIXME: This is disabled because the asm matcher is currently incapable of 2831 * matching a fixed immediate like $1. 2832// "shl X, $1" is an alias for "shl X". 2833multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 2834 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2835 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 2836 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2837 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 2838 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2839 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 2840 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2841 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 2842 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2843 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 2844 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2845 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 2846 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2847 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 2848 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2849 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 2850} 2851 2852defm : ShiftRotateByOneAlias<"rcl", "RCL">; 2853defm : ShiftRotateByOneAlias<"rcr", "RCR">; 2854defm : ShiftRotateByOneAlias<"rol", "ROL">; 2855defm : ShiftRotateByOneAlias<"ror", "ROR">; 2856FIXME */ 2857 2858// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 2859def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", 2860 (TEST8rm GR8 :$val, i8mem :$mem), 0>; 2861def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", 2862 (TEST16rm GR16:$val, i16mem:$mem), 0>; 2863def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", 2864 (TEST32rm GR32:$val, i32mem:$mem), 0>; 2865def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", 2866 (TEST64rm GR64:$val, i64mem:$mem), 0>; 2867 2868// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 2869def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 2870 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 2871def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 2872 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 2873def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 2874 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 2875def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 2876 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 2877 2878// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 2879def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 2880def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2881 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>; 2882def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2883 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>; 2884def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 2885