1; RUN: opt < %s  -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 | FileCheck %s
2
3define <2 x i8> @sdiv_v2_i8(<2 x i8>  %a, <2 x i8> %b) {
4  ; CHECK: sdiv_v2_i8
5  ; CHECK: cost of 40 {{.*}} sdiv
6
7  %1 = sdiv <2 x i8>  %a, %b
8  ret <2 x i8> %1
9}
10define <2 x i16> @sdiv_v2_i16(<2 x i16>  %a, <2 x i16> %b) {
11  ; CHECK: sdiv_v2_i16
12  ; CHECK: cost of 40 {{.*}} sdiv
13
14  %1 = sdiv <2 x i16>  %a, %b
15  ret <2 x i16> %1
16}
17define <2 x i32> @sdiv_v2_i32(<2 x i32>  %a, <2 x i32> %b) {
18  ; CHECK: sdiv_v2_i32
19  ; CHECK: cost of 40 {{.*}} sdiv
20
21  %1 = sdiv <2 x i32>  %a, %b
22  ret <2 x i32> %1
23}
24define <2 x i64> @sdiv_v2_i64(<2 x i64>  %a, <2 x i64> %b) {
25  ; CHECK: sdiv_v2_i64
26  ; CHECK: cost of 40 {{.*}} sdiv
27
28  %1 = sdiv <2 x i64>  %a, %b
29  ret <2 x i64> %1
30}
31define <4 x i8> @sdiv_v4_i8(<4 x i8>  %a, <4 x i8> %b) {
32  ; CHECK: sdiv_v4_i8
33  ; CHECK: cost of 10 {{.*}} sdiv
34
35  %1 = sdiv <4 x i8>  %a, %b
36  ret <4 x i8> %1
37}
38define <4 x i16> @sdiv_v4_i16(<4 x i16>  %a, <4 x i16> %b) {
39  ; CHECK: sdiv_v4_i16
40  ; CHECK: cost of 10 {{.*}} sdiv
41
42  %1 = sdiv <4 x i16>  %a, %b
43  ret <4 x i16> %1
44}
45define <4 x i32> @sdiv_v4_i32(<4 x i32>  %a, <4 x i32> %b) {
46  ; CHECK: sdiv_v4_i32
47  ; CHECK: cost of 80 {{.*}} sdiv
48
49  %1 = sdiv <4 x i32>  %a, %b
50  ret <4 x i32> %1
51}
52define <4 x i64> @sdiv_v4_i64(<4 x i64>  %a, <4 x i64> %b) {
53  ; CHECK: sdiv_v4_i64
54  ; CHECK: cost of 80 {{.*}} sdiv
55
56  %1 = sdiv <4 x i64>  %a, %b
57  ret <4 x i64> %1
58}
59define <8 x i8> @sdiv_v8_i8(<8 x i8>  %a, <8 x i8> %b) {
60  ; CHECK: sdiv_v8_i8
61  ; CHECK: cost of 10 {{.*}} sdiv
62
63  %1 = sdiv <8 x i8>  %a, %b
64  ret <8 x i8> %1
65}
66define <8 x i16> @sdiv_v8_i16(<8 x i16>  %a, <8 x i16> %b) {
67  ; CHECK: sdiv_v8_i16
68  ; CHECK: cost of 160 {{.*}} sdiv
69
70  %1 = sdiv <8 x i16>  %a, %b
71  ret <8 x i16> %1
72}
73define <8 x i32> @sdiv_v8_i32(<8 x i32>  %a, <8 x i32> %b) {
74  ; CHECK: sdiv_v8_i32
75  ; CHECK: cost of 160 {{.*}} sdiv
76
77  %1 = sdiv <8 x i32>  %a, %b
78  ret <8 x i32> %1
79}
80define <8 x i64> @sdiv_v8_i64(<8 x i64>  %a, <8 x i64> %b) {
81  ; CHECK: sdiv_v8_i64
82  ; CHECK: cost of 160 {{.*}} sdiv
83
84  %1 = sdiv <8 x i64>  %a, %b
85  ret <8 x i64> %1
86}
87define <16 x i8> @sdiv_v16_i8(<16 x i8>  %a, <16 x i8> %b) {
88  ; CHECK: sdiv_v16_i8
89  ; CHECK: cost of 320 {{.*}} sdiv
90
91  %1 = sdiv <16 x i8>  %a, %b
92  ret <16 x i8> %1
93}
94define <16 x i16> @sdiv_v16_i16(<16 x i16>  %a, <16 x i16> %b) {
95  ; CHECK: sdiv_v16_i16
96  ; CHECK: cost of 320 {{.*}} sdiv
97
98  %1 = sdiv <16 x i16>  %a, %b
99  ret <16 x i16> %1
100}
101define <16 x i32> @sdiv_v16_i32(<16 x i32>  %a, <16 x i32> %b) {
102  ; CHECK: sdiv_v16_i32
103  ; CHECK: cost of 320 {{.*}} sdiv
104
105  %1 = sdiv <16 x i32>  %a, %b
106  ret <16 x i32> %1
107}
108define <16 x i64> @sdiv_v16_i64(<16 x i64>  %a, <16 x i64> %b) {
109  ; CHECK: sdiv_v16_i64
110  ; CHECK: cost of 320 {{.*}} sdiv
111
112  %1 = sdiv <16 x i64>  %a, %b
113  ret <16 x i64> %1
114}
115define <2 x i8> @udiv_v2_i8(<2 x i8>  %a, <2 x i8> %b) {
116  ; CHECK: udiv_v2_i8
117  ; CHECK: cost of 40 {{.*}} udiv
118
119  %1 = udiv <2 x i8>  %a, %b
120  ret <2 x i8> %1
121}
122define <2 x i16> @udiv_v2_i16(<2 x i16>  %a, <2 x i16> %b) {
123  ; CHECK: udiv_v2_i16
124  ; CHECK: cost of 40 {{.*}} udiv
125
126  %1 = udiv <2 x i16>  %a, %b
127  ret <2 x i16> %1
128}
129define <2 x i32> @udiv_v2_i32(<2 x i32>  %a, <2 x i32> %b) {
130  ; CHECK: udiv_v2_i32
131  ; CHECK: cost of 40 {{.*}} udiv
132
133  %1 = udiv <2 x i32>  %a, %b
134  ret <2 x i32> %1
135}
136define <2 x i64> @udiv_v2_i64(<2 x i64>  %a, <2 x i64> %b) {
137  ; CHECK: udiv_v2_i64
138  ; CHECK: cost of 40 {{.*}} udiv
139
140  %1 = udiv <2 x i64>  %a, %b
141  ret <2 x i64> %1
142}
143define <4 x i8> @udiv_v4_i8(<4 x i8>  %a, <4 x i8> %b) {
144  ; CHECK: udiv_v4_i8
145  ; CHECK: cost of 10 {{.*}} udiv
146
147  %1 = udiv <4 x i8>  %a, %b
148  ret <4 x i8> %1
149}
150define <4 x i16> @udiv_v4_i16(<4 x i16>  %a, <4 x i16> %b) {
151  ; CHECK: udiv_v4_i16
152  ; CHECK: cost of 10 {{.*}} udiv
153
154  %1 = udiv <4 x i16>  %a, %b
155  ret <4 x i16> %1
156}
157define <4 x i32> @udiv_v4_i32(<4 x i32>  %a, <4 x i32> %b) {
158  ; CHECK: udiv_v4_i32
159  ; CHECK: cost of 80 {{.*}} udiv
160
161  %1 = udiv <4 x i32>  %a, %b
162  ret <4 x i32> %1
163}
164define <4 x i64> @udiv_v4_i64(<4 x i64>  %a, <4 x i64> %b) {
165  ; CHECK: udiv_v4_i64
166  ; CHECK: cost of 80 {{.*}} udiv
167
168  %1 = udiv <4 x i64>  %a, %b
169  ret <4 x i64> %1
170}
171define <8 x i8> @udiv_v8_i8(<8 x i8>  %a, <8 x i8> %b) {
172  ; CHECK: udiv_v8_i8
173  ; CHECK: cost of 10 {{.*}} udiv
174
175  %1 = udiv <8 x i8>  %a, %b
176  ret <8 x i8> %1
177}
178define <8 x i16> @udiv_v8_i16(<8 x i16>  %a, <8 x i16> %b) {
179  ; CHECK: udiv_v8_i16
180  ; CHECK: cost of 160 {{.*}} udiv
181
182  %1 = udiv <8 x i16>  %a, %b
183  ret <8 x i16> %1
184}
185define <8 x i32> @udiv_v8_i32(<8 x i32>  %a, <8 x i32> %b) {
186  ; CHECK: udiv_v8_i32
187  ; CHECK: cost of 160 {{.*}} udiv
188
189  %1 = udiv <8 x i32>  %a, %b
190  ret <8 x i32> %1
191}
192define <8 x i64> @udiv_v8_i64(<8 x i64>  %a, <8 x i64> %b) {
193  ; CHECK: udiv_v8_i64
194  ; CHECK: cost of 160 {{.*}} udiv
195
196  %1 = udiv <8 x i64>  %a, %b
197  ret <8 x i64> %1
198}
199define <16 x i8> @udiv_v16_i8(<16 x i8>  %a, <16 x i8> %b) {
200  ; CHECK: udiv_v16_i8
201  ; CHECK: cost of 320 {{.*}} udiv
202
203  %1 = udiv <16 x i8>  %a, %b
204  ret <16 x i8> %1
205}
206define <16 x i16> @udiv_v16_i16(<16 x i16>  %a, <16 x i16> %b) {
207  ; CHECK: udiv_v16_i16
208  ; CHECK: cost of 320 {{.*}} udiv
209
210  %1 = udiv <16 x i16>  %a, %b
211  ret <16 x i16> %1
212}
213define <16 x i32> @udiv_v16_i32(<16 x i32>  %a, <16 x i32> %b) {
214  ; CHECK: udiv_v16_i32
215  ; CHECK: cost of 320 {{.*}} udiv
216
217  %1 = udiv <16 x i32>  %a, %b
218  ret <16 x i32> %1
219}
220define <16 x i64> @udiv_v16_i64(<16 x i64>  %a, <16 x i64> %b) {
221  ; CHECK: udiv_v16_i64
222  ; CHECK: cost of 320 {{.*}} udiv
223
224  %1 = udiv <16 x i64>  %a, %b
225  ret <16 x i64> %1
226}
227define <2 x i8> @srem_v2_i8(<2 x i8>  %a, <2 x i8> %b) {
228  ; CHECK: srem_v2_i8
229  ; CHECK: cost of 40 {{.*}} srem
230
231  %1 = srem <2 x i8>  %a, %b
232  ret <2 x i8> %1
233}
234define <2 x i16> @srem_v2_i16(<2 x i16>  %a, <2 x i16> %b) {
235  ; CHECK: srem_v2_i16
236  ; CHECK: cost of 40 {{.*}} srem
237
238  %1 = srem <2 x i16>  %a, %b
239  ret <2 x i16> %1
240}
241define <2 x i32> @srem_v2_i32(<2 x i32>  %a, <2 x i32> %b) {
242  ; CHECK: srem_v2_i32
243  ; CHECK: cost of 40 {{.*}} srem
244
245  %1 = srem <2 x i32>  %a, %b
246  ret <2 x i32> %1
247}
248define <2 x i64> @srem_v2_i64(<2 x i64>  %a, <2 x i64> %b) {
249  ; CHECK: srem_v2_i64
250  ; CHECK: cost of 40 {{.*}} srem
251
252  %1 = srem <2 x i64>  %a, %b
253  ret <2 x i64> %1
254}
255define <4 x i8> @srem_v4_i8(<4 x i8>  %a, <4 x i8> %b) {
256  ; CHECK: srem_v4_i8
257  ; CHECK: cost of 80 {{.*}} srem
258
259  %1 = srem <4 x i8>  %a, %b
260  ret <4 x i8> %1
261}
262define <4 x i16> @srem_v4_i16(<4 x i16>  %a, <4 x i16> %b) {
263  ; CHECK: srem_v4_i16
264  ; CHECK: cost of 80 {{.*}} srem
265
266  %1 = srem <4 x i16>  %a, %b
267  ret <4 x i16> %1
268}
269define <4 x i32> @srem_v4_i32(<4 x i32>  %a, <4 x i32> %b) {
270  ; CHECK: srem_v4_i32
271  ; CHECK: cost of 80 {{.*}} srem
272
273  %1 = srem <4 x i32>  %a, %b
274  ret <4 x i32> %1
275}
276define <4 x i64> @srem_v4_i64(<4 x i64>  %a, <4 x i64> %b) {
277  ; CHECK: srem_v4_i64
278  ; CHECK: cost of 80 {{.*}} srem
279
280  %1 = srem <4 x i64>  %a, %b
281  ret <4 x i64> %1
282}
283define <8 x i8> @srem_v8_i8(<8 x i8>  %a, <8 x i8> %b) {
284  ; CHECK: srem_v8_i8
285  ; CHECK: cost of 160 {{.*}} srem
286
287  %1 = srem <8 x i8>  %a, %b
288  ret <8 x i8> %1
289}
290define <8 x i16> @srem_v8_i16(<8 x i16>  %a, <8 x i16> %b) {
291  ; CHECK: srem_v8_i16
292  ; CHECK: cost of 160 {{.*}} srem
293
294  %1 = srem <8 x i16>  %a, %b
295  ret <8 x i16> %1
296}
297define <8 x i32> @srem_v8_i32(<8 x i32>  %a, <8 x i32> %b) {
298  ; CHECK: srem_v8_i32
299  ; CHECK: cost of 160 {{.*}} srem
300
301  %1 = srem <8 x i32>  %a, %b
302  ret <8 x i32> %1
303}
304define <8 x i64> @srem_v8_i64(<8 x i64>  %a, <8 x i64> %b) {
305  ; CHECK: srem_v8_i64
306  ; CHECK: cost of 160 {{.*}} srem
307
308  %1 = srem <8 x i64>  %a, %b
309  ret <8 x i64> %1
310}
311define <16 x i8> @srem_v16_i8(<16 x i8>  %a, <16 x i8> %b) {
312  ; CHECK: srem_v16_i8
313  ; CHECK: cost of 320 {{.*}} srem
314
315  %1 = srem <16 x i8>  %a, %b
316  ret <16 x i8> %1
317}
318define <16 x i16> @srem_v16_i16(<16 x i16>  %a, <16 x i16> %b) {
319  ; CHECK: srem_v16_i16
320  ; CHECK: cost of 320 {{.*}} srem
321
322  %1 = srem <16 x i16>  %a, %b
323  ret <16 x i16> %1
324}
325define <16 x i32> @srem_v16_i32(<16 x i32>  %a, <16 x i32> %b) {
326  ; CHECK: srem_v16_i32
327  ; CHECK: cost of 320 {{.*}} srem
328
329  %1 = srem <16 x i32>  %a, %b
330  ret <16 x i32> %1
331}
332define <16 x i64> @srem_v16_i64(<16 x i64>  %a, <16 x i64> %b) {
333  ; CHECK: srem_v16_i64
334  ; CHECK: cost of 320 {{.*}} srem
335
336  %1 = srem <16 x i64>  %a, %b
337  ret <16 x i64> %1
338}
339define <2 x i8> @urem_v2_i8(<2 x i8>  %a, <2 x i8> %b) {
340  ; CHECK: urem_v2_i8
341  ; CHECK: cost of 40 {{.*}} urem
342
343  %1 = urem <2 x i8>  %a, %b
344  ret <2 x i8> %1
345}
346define <2 x i16> @urem_v2_i16(<2 x i16>  %a, <2 x i16> %b) {
347  ; CHECK: urem_v2_i16
348  ; CHECK: cost of 40 {{.*}} urem
349
350  %1 = urem <2 x i16>  %a, %b
351  ret <2 x i16> %1
352}
353define <2 x i32> @urem_v2_i32(<2 x i32>  %a, <2 x i32> %b) {
354  ; CHECK: urem_v2_i32
355  ; CHECK: cost of 40 {{.*}} urem
356
357  %1 = urem <2 x i32>  %a, %b
358  ret <2 x i32> %1
359}
360define <2 x i64> @urem_v2_i64(<2 x i64>  %a, <2 x i64> %b) {
361  ; CHECK: urem_v2_i64
362  ; CHECK: cost of 40 {{.*}} urem
363
364  %1 = urem <2 x i64>  %a, %b
365  ret <2 x i64> %1
366}
367define <4 x i8> @urem_v4_i8(<4 x i8>  %a, <4 x i8> %b) {
368  ; CHECK: urem_v4_i8
369  ; CHECK: cost of 80 {{.*}} urem
370
371  %1 = urem <4 x i8>  %a, %b
372  ret <4 x i8> %1
373}
374define <4 x i16> @urem_v4_i16(<4 x i16>  %a, <4 x i16> %b) {
375  ; CHECK: urem_v4_i16
376  ; CHECK: cost of 80 {{.*}} urem
377
378  %1 = urem <4 x i16>  %a, %b
379  ret <4 x i16> %1
380}
381define <4 x i32> @urem_v4_i32(<4 x i32>  %a, <4 x i32> %b) {
382  ; CHECK: urem_v4_i32
383  ; CHECK: cost of 80 {{.*}} urem
384
385  %1 = urem <4 x i32>  %a, %b
386  ret <4 x i32> %1
387}
388define <4 x i64> @urem_v4_i64(<4 x i64>  %a, <4 x i64> %b) {
389  ; CHECK: urem_v4_i64
390  ; CHECK: cost of 80 {{.*}} urem
391
392  %1 = urem <4 x i64>  %a, %b
393  ret <4 x i64> %1
394}
395define <8 x i8> @urem_v8_i8(<8 x i8>  %a, <8 x i8> %b) {
396  ; CHECK: urem_v8_i8
397  ; CHECK: cost of 160 {{.*}} urem
398
399  %1 = urem <8 x i8>  %a, %b
400  ret <8 x i8> %1
401}
402define <8 x i16> @urem_v8_i16(<8 x i16>  %a, <8 x i16> %b) {
403  ; CHECK: urem_v8_i16
404  ; CHECK: cost of 160 {{.*}} urem
405
406  %1 = urem <8 x i16>  %a, %b
407  ret <8 x i16> %1
408}
409define <8 x i32> @urem_v8_i32(<8 x i32>  %a, <8 x i32> %b) {
410  ; CHECK: urem_v8_i32
411  ; CHECK: cost of 160 {{.*}} urem
412
413  %1 = urem <8 x i32>  %a, %b
414  ret <8 x i32> %1
415}
416define <8 x i64> @urem_v8_i64(<8 x i64>  %a, <8 x i64> %b) {
417  ; CHECK: urem_v8_i64
418  ; CHECK: cost of 160 {{.*}} urem
419
420  %1 = urem <8 x i64>  %a, %b
421  ret <8 x i64> %1
422}
423define <16 x i8> @urem_v16_i8(<16 x i8>  %a, <16 x i8> %b) {
424  ; CHECK: urem_v16_i8
425  ; CHECK: cost of 320 {{.*}} urem
426
427  %1 = urem <16 x i8>  %a, %b
428  ret <16 x i8> %1
429}
430define <16 x i16> @urem_v16_i16(<16 x i16>  %a, <16 x i16> %b) {
431  ; CHECK: urem_v16_i16
432  ; CHECK: cost of 320 {{.*}} urem
433
434  %1 = urem <16 x i16>  %a, %b
435  ret <16 x i16> %1
436}
437define <16 x i32> @urem_v16_i32(<16 x i32>  %a, <16 x i32> %b) {
438  ; CHECK: urem_v16_i32
439  ; CHECK: cost of 320 {{.*}} urem
440
441  %1 = urem <16 x i32>  %a, %b
442  ret <16 x i32> %1
443}
444define <16 x i64> @urem_v16_i64(<16 x i64>  %a, <16 x i64> %b) {
445  ; CHECK: urem_v16_i64
446  ; CHECK: cost of 320 {{.*}} urem
447
448  %1 = urem <16 x i64>  %a, %b
449  ret <16 x i64> %1
450}
451