1; RUN: llc < %s -march=arm64 | FileCheck %s
2
3;==--------------------------------------------------------------------------==
4; Tests for MOV-immediate implemented with ORR-immediate.
5;==--------------------------------------------------------------------------==
6
7; 64-bit immed with 32-bit pattern size, rotated by 0.
8define i64 @test64_32_rot0() nounwind {
9; CHECK-LABEL: test64_32_rot0:
10; CHECK: orr x0, xzr, #0x700000007
11  ret i64 30064771079
12}
13
14; 64-bit immed with 32-bit pattern size, rotated by 2.
15define i64 @test64_32_rot2() nounwind {
16; CHECK-LABEL: test64_32_rot2:
17; CHECK: orr x0, xzr, #0xc0000003c0000003
18  ret i64 13835058071388291075
19}
20
21; 64-bit immed with 4-bit pattern size, rotated by 3.
22define i64 @test64_4_rot3() nounwind {
23; CHECK-LABEL: test64_4_rot3:
24; CHECK: orr  x0, xzr, #0xeeeeeeeeeeeeeeee
25  ret i64 17216961135462248174
26}
27
28; 32-bit immed with 32-bit pattern size, rotated by 16.
29define i32 @test32_32_rot16() nounwind {
30; CHECK-LABEL: test32_32_rot16:
31; CHECK: orr w0, wzr, #0xff0000
32  ret i32 16711680
33}
34
35; 32-bit immed with 2-bit pattern size, rotated by 1.
36define i32 @test32_2_rot1() nounwind {
37; CHECK-LABEL: test32_2_rot1:
38; CHECK: orr w0, wzr, #0xaaaaaaaa
39  ret i32 2863311530
40}
41
42;==--------------------------------------------------------------------------==
43; Tests for MOVZ with MOVK.
44;==--------------------------------------------------------------------------==
45
46define i32 @movz() nounwind {
47; CHECK-LABEL: movz:
48; CHECK: movz w0, #0x5
49  ret i32 5
50}
51
52define i64 @movz_3movk() nounwind {
53; CHECK-LABEL: movz_3movk:
54; CHECK:      movz x0, #0x5, lsl #48
55; CHECK-NEXT: movk x0, #0x1234, lsl #32
56; CHECK-NEXT: movk x0, #0xabcd, lsl #16
57; CHECK-NEXT: movk x0, #0x5678
58  ret i64 1427392313513592
59}
60
61define i64 @movz_movk_skip1() nounwind {
62; CHECK-LABEL: movz_movk_skip1:
63; CHECK:      movz x0, #0x5, lsl #32
64; CHECK-NEXT: movk x0, #0x4321, lsl #16
65  ret i64 22601072640
66}
67
68define i64 @movz_skip1_movk() nounwind {
69; CHECK-LABEL: movz_skip1_movk:
70; CHECK:      movz x0, #0x8654, lsl #32
71; CHECK-NEXT: movk x0, #0x1234
72  ret i64 147695335379508
73}
74
75;==--------------------------------------------------------------------------==
76; Tests for MOVN with MOVK.
77;==--------------------------------------------------------------------------==
78
79define i64 @movn() nounwind {
80; CHECK-LABEL: movn:
81; CHECK: movn x0, #0x29
82  ret i64 -42
83}
84
85define i64 @movn_skip1_movk() nounwind {
86; CHECK-LABEL: movn_skip1_movk:
87; CHECK:      movn x0, #0x29, lsl #32
88; CHECK-NEXT: movk x0, #0x1234
89  ret i64 -176093720012
90}
91
92;==--------------------------------------------------------------------------==
93; Tests for ORR with MOVK.
94;==--------------------------------------------------------------------------==
95; rdar://14987673
96
97define i64 @orr_movk1() nounwind {
98; CHECK-LABEL: orr_movk1:
99; CHECK: orr x0, xzr, #0xffff0000ffff0
100; CHECK: movk x0, #0xdead, lsl #16
101  ret i64 72056498262245120
102}
103
104define i64 @orr_movk2() nounwind {
105; CHECK-LABEL: orr_movk2:
106; CHECK: orr x0, xzr, #0xffff0000ffff0
107; CHECK: movk x0, #0xdead, lsl #48
108  ret i64 -2400982650836746496
109}
110
111define i64 @orr_movk3() nounwind {
112; CHECK-LABEL: orr_movk3:
113; CHECK: orr x0, xzr, #0xffff0000ffff0
114; CHECK: movk x0, #0xdead, lsl #32
115  ret i64 72020953688702720
116}
117
118define i64 @orr_movk4() nounwind {
119; CHECK-LABEL: orr_movk4:
120; CHECK: orr x0, xzr, #0xffff0000ffff0
121; CHECK: movk x0, #0xdead
122  ret i64 72056494543068845
123}
124
125; rdar://14987618
126define i64 @orr_movk5() nounwind {
127; CHECK-LABEL: orr_movk5:
128; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
129; CHECK: movk x0, #0xdead, lsl #16
130  ret i64 -71777214836900096
131}
132
133define i64 @orr_movk6() nounwind {
134; CHECK-LABEL: orr_movk6:
135; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
136; CHECK: movk x0, #0xdead, lsl #16
137; CHECK: movk x0, #0xdead, lsl #48
138  ret i64 -2400982647117578496
139}
140
141define i64 @orr_movk7() nounwind {
142; CHECK-LABEL: orr_movk7:
143; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
144; CHECK: movk x0, #0xdead, lsl #48
145  ret i64 -2400982646575268096
146}
147
148define i64 @orr_movk8() nounwind {
149; CHECK-LABEL: orr_movk8:
150; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
151; CHECK: movk x0, #0xdead
152; CHECK: movk x0, #0xdead, lsl #48
153  ret i64 -2400982646575276371
154}
155
156; rdar://14987715
157define i64 @orr_movk9() nounwind {
158; CHECK-LABEL: orr_movk9:
159; CHECK: orr x0, xzr, #0xffffff000000000
160; CHECK: movk x0, #0xff00
161; CHECK: movk x0, #0xdead, lsl #16
162  ret i64 1152921439623315200
163}
164
165define i64 @orr_movk10() nounwind {
166; CHECK-LABEL: orr_movk10:
167; CHECK: orr x0, xzr, #0xfffffffffffff00
168; CHECK: movk x0, #0xdead, lsl #16
169  ret i64 1152921504047824640
170}
171
172define i64 @orr_movk11() nounwind {
173; CHECK-LABEL: orr_movk11:
174; CHECK: orr x0, xzr, #0xfff00000000000ff
175; CHECK: movk x0, #0xdead, lsl #16
176; CHECK: movk x0, #0xffff, lsl #32
177  ret i64 -4222125209747201
178}
179
180define i64 @orr_movk12() nounwind {
181; CHECK-LABEL: orr_movk12:
182; CHECK: orr x0, xzr, #0xfff00000000000ff
183; CHECK: movk x0, #0xdead, lsl #32
184  ret i64 -4258765016661761
185}
186
187define i64 @orr_movk13() nounwind {
188; CHECK-LABEL: orr_movk13:
189; CHECK: orr x0, xzr, #0xfffff000000
190; CHECK: movk x0, #0xdead
191; CHECK: movk x0, #0xdead, lsl #48
192  ret i64 -2401245434149282131
193}
194
195; rdar://13944082
196define i64 @g() nounwind {
197; CHECK-LABEL: g:
198; CHECK: movz x0, #0xffff, lsl #48
199; CHECK: movk x0, #0x2
200entry:
201  ret i64 -281474976710654
202}
203